SBIR Phase II: Low-density parity-check error correction for enhanced reliability of flash memories

Information

  • NSF Award
  • 1534760
Owner
  • Award Id
    1534760
  • Award Effective Date
    8/15/2015 - 9 years ago
  • Award Expiration Date
    7/31/2017 - 7 years ago
  • Award Amount
    $ 750,000.00
  • Award Instrument
    Standard Grant

SBIR Phase II: Low-density parity-check error correction for enhanced reliability of flash memories

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project are both technical and economic. The developed error-correction solutions will enable flash-memory-based devices to have higher capacities, higher reliability, and faster speeds at lower power while driving down the cost. This will have a major impact on mobile computing capabilities and enterprise storage by improving the efficiency and reliability of data centers, servers, and mission-critical storage that incorporate flash memories. Improved enterprise storage boosts the efficiency and growth of IT businesses, e-commerce, and financial trade. The solutions will also enable reduced power consumption and heat dissipation leading to greener systems. The benefits of the error-correction solutions are also applicable to the hard disk drive and communications industries.<br/><br/>This Small Business Innovation Research (SBIR) Phase II project will develop and validate novel low-density parity-check (LDPC)-based error-correction for flash memory-based solid state drives (SSDs). SSDs are rapidly being deployed for both enterprise and consumer storage due to their fast speeds, low power, and low heat dissipation. But they bring numerous technical challenges stemming from the fact that reducing flash memory cell sizes leads to an unavoidable degradation in the reliability. With a trend of increasing die density to enable higher storage capacities, the industry is swiftly moving towards adopting LDPC codes to provide more powerful error-correction. However existing LDPC solutions use complex post-processing and multiple reads to bring down the error rates to the desired levels which lowers the read speeds, making them unattractive for future SSDs. Novel binary LDPC-based solutions will be developed for a range of parameters, and validated in hardware. The design method will be extended to develop new non-binary LDPC solutions which provide even greater reliability enhancements, leading to greater endurance in SSDs.

  • Program Officer
    Peter Atherton
  • Min Amd Letter Date
    8/12/2015 - 9 years ago
  • Max Amd Letter Date
    8/12/2015 - 9 years ago
  • ARRA Amount

Institutions

  • Name
    Codelucida, LLC
  • City
    Tucson
  • State
    AZ
  • Country
    United States
  • Address
    7479 N Calle Sin Celo
  • Postal Code
    857181256
  • Phone Number
    5202396653

Investigators

  • First Name
    Shiva
  • Last Name
    Planjery
  • Email Address
    planjery@codelucida.com
  • Start Date
    8/12/2015 12:00:00 AM

Program Element

  • Text
    SMALL BUSINESS PHASE II
  • Code
    5373

Program Reference

  • Text
    High Freq Devices & Circuits
  • Text
    Mixed signal technologies
  • Text
    SMALL BUSINESS PHASE II
  • Code
    5373
  • Text
    Hardware Devices
  • Code
    8035