SBIR/STTR Phase II: A Low Cost Semiconductor Metallization-Planarization Process

Information

  • NSF Award
  • 0131791
Owner
  • Award Id
    0131791
  • Award Effective Date
    3/15/2002 - 22 years ago
  • Award Expiration Date
    2/28/2005 - 19 years ago
  • Award Amount
    $ 530,042.00
  • Award Instrument
    Standard Grant

SBIR/STTR Phase II: A Low Cost Semiconductor Metallization-Planarization Process

This Small Business Innovation Research Phase II Project will establish market demand for a novel electrically mediated leveling technology and position the technology for market launch via a joint venture. The specific Phase II objectives are: 1. Scale-up and demonstration of the electrically mediated process on eight inch wafers, 2. Development of a process library for feature sizes 1-5 down to 0.17 microns, and lower, and 3. Design of a "proof of concept" plating tool. Preliminary concept design of a plating tool incorporating the electrically mediated process will be performed by an outside firm. <br/> The sustainable competitive advantage associated with the project for leveling is cost. Minimal overplate will eliminate or minimize the need for chemical/mechanical planarization (CMP) by reducing the copper waste slurry compared to the state-of-the-art copper metallization processes. This in turn would eliminate the associated control, environmental, and cost issues.

  • Program Officer
    Rosemarie D. Wesson
  • Min Amd Letter Date
    3/19/2002 - 22 years ago
  • Max Amd Letter Date
    7/13/2004 - 20 years ago
  • ARRA Amount

Institutions

  • Name
    FARADAY TECHNOLOGY, INC
  • City
    Englewood
  • State
    OH
  • Country
    United States
  • Address
    315 HULS
  • Postal Code
    453158983
  • Phone Number
    9378367749

Investigators

  • First Name
    E. Jennings
  • Last Name
    Taylor
  • Email Address
    jenningstaylor@faradaytechnology.com
  • Start Date
    3/19/2002 12:00:00 AM

FOA Information

  • Name
    Industrial Technology
  • Code
    308000