Claims
- 1. A method of sharing physically distinct memory resources, locally associated with each of a plurality of processing nodes, as a logically contiguous memory for the plurality of processing nodes, said method comprising:
initiating coherent memory transactions by which lines of memory resources locally associated with one of the plurality of processing nodes as a home node are fetched by one or more others of the plurality of processing nodes as a remote node; and transmitting commands comprising the initiated coherent memory transactions as coherency transaction packets over a packetized I/O link to which the plurality of processing nodes are coupled.
- 2. The method of claim 1 wherein the packetized I/O link comprises a plurality of virtual channels sufficient to transport coherent and non-coherent memory transactions between the processing nodes without experiencing deadlocks due to resource dependencies.
- 3. The method of claim 2 wherein a portion of the plurality of virtual channels are legacy I/O virtual channels and a portion of the plurality of virtual channels are coherency virtual channels over which coherent memory transactions are transported.
- 4. The method of claim 3 wherein one or more of the commands comprising the coherent memory transactions are transported over at least one of the I/O virtual channels, and one or more of the coherent memory legacy commands are transported over the coherency virtual channels.
- 5. The method of claim 4 wherein the coherent memory transactions implement a modified-shared-invalid (MSI) protocol.
- 6. The method of claim 4 wherein the plurality of the processing coherent memory transactions ensure that only one node may be an owner of a memory line, and only the owner may modify the line.
- 7. The method of claim 1 further comprising recording a coherency state in a directory associated with the home node for each line from the home node's memory resource that is fetched by a remote node.
- 14. The method of claim 7 further comprising recording a node identifier in the directory indicating to which of the remote nodes the line from the home node's memory resource has been fetched.
- 15. The method of claim 14 wherein each processing node comprises a processing resource, the processing resource comprising a plurality of parallel processors sharing the memory resource local to the processing node over a processor bus; and wherein each processing node maintains coherency of its local memory resource with a first coherency protocol and wherein the processing nodes maintain the coherency of the logical memory with a second coherency protocol.
- 16. The method of claim 15 further comprising translating processor bus transactions initiated within a remote processing node for accessing memory lines local to a home processing node to the coherent memory transactions; and translating the coherent memory transactions received by the home node into processor bus transactions for accessing the memory lines local to the home node.
- 17. A distributed shared memory system comprising:
a plurality of processing nodes, each of said processing nodes comprising:
local memory resources and a processing resource coupled to the local memory resources by a processor bus; a line directory having entries comprising coherency status for each of the lines from the local memory resources-for which copies have been provided to others of the processing resources; and a node controller coupled to the line directory for receiving coherent memory transactions from others of the processing nodes for lines from the local memory resources; and a packetized I/O link to which each of the processing nodes is coupled, said packetized I/O link for transmitting the coherent memory transactions by which lines of the memory resources are shared in accordance with a first coherency protocol.
- 18. The apparatus of claim 17 wherein the entries of the line directory further comprise a node identifier that identifies which of the processors has a copy of the line from the local memory resources represented by the entry.
- 19. The apparatus of claim 17 wherein the processing resource of the processing nodes further comprises a plurality of processors coupled to the local memory resources over the processor bus, and wherein the plurality of processors share access to the local memory resources over the processor bus in accordance with a second coherence protocol.
- 20. The apparatus of claim 19 wherein the node controller receives coherent memory transactions over the link and translates them into processor bus transactions and receives processor bus transactions over the processor bus and translates them into coherency memory transactions for transmission over the link.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims priority under 35 U.S.C. 119(e) to the following applications, each of which is incorporated herein for all purposes:
[0002] (1) provisional patent application entitled SYSTEM ON A CHIP FOR NETWORKING, having an application No. 60/380,740, and a filing date of May 15, 2002; and
[0003] (2) provisional patent application having the same title as above, having an application No. 60/419,033, and a filing date of Oct. 16, 2002.
Provisional Applications (2)
|
Number |
Date |
Country |
|
60380740 |
May 2002 |
US |
|
60419033 |
Oct 2002 |
US |