Patent Application
20230092548
The document pertains generally, but not by way of limitation, to integrated circuits, and more particularly, to techniques for a voltage level shifter.
Microprocessors and other data processing devices typically include core logic circuitry, such as circuitry that is configured to execute software applications or to perform data processing operations, and input-output (I/O) interface circuitry, such as circuitry that is configured to interface with, or to exchange data or other signals between, devices that are external or remote to the microprocessor. To reduce power dissipation and to, among other things, enable the continuing reduction in integrated circuitry device sizes, microprocessor core logic circuitry is typically operated at or about the minimum voltage (hereinafter, “core voltage”) allowable by a semiconductor fabrication process node. Input-output circuitry, however, generally operate at voltages (hereinafter, “I/O voltage” or “I/O voltages”) higher than this core voltage, such as to improve signal integrity or to enable high speed communication over the relatively long distances between devices or components of a system. A voltage level shifter, such as the high-speed level shifters typically employed in high-speed memory I/O interface such as double data rate (DDR) memory and high bandwidth memory (HBM), are used in processors to convert, or shift the voltages of signals generated by core logic circuitry to voltages in the range of the I/O circuitry.
A concern in the implementation of level shifter circuitry is electrical over stress (EOS) and device aging, such as caused by applying a voltage a cross a device (e.g., across two terminals of a device) that exceeds an operating parameter of the devices, such as an EOS target or threshold voltage of a transistor. EOS can degrade the performance of a device and accelerate device aging. Several techniques for building level shifters attempt to address these concerns. One technique, for example, includes the use of thick gate devices, such as semiconductor devices that have a gate oxide that is suitably thick to cause the devices to have an EOS target of threshold that exceeds the range of I/O voltages used in I/O interface circuitry. Another technique includes the use of thin gate devices, such as devices that may be susceptible to EOS damage when operated at voltages in the range of I/O voltages used in I/O interface circuitry, along with an elevated ground signal, such as a reference signal that is offset to a higher voltage than a ground or reference used by the core logic, to protect devices that are exposed to I/O voltages. Such device protection includes using the elevated reference to limit maximum voltage across the device.
In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. Some examples are illustrated by way of example, and not limitation, in the figures of the accompanying drawings.
Aspects of the present disclosure are based on the inventors' realization that existing techniques for shifting the voltage level of signals in an integrated circuit from a low voltage range, such as a core voltage range, to a higher voltage range, such as an I/O voltage range, is not suitable for some applications and can inhibit or limit progress in current trends towards forming smaller, faster, and lower power integrated circuit devices and systems. In example, fabrication costs associated with level shifting techniques that use thick gate devices can be high as such techniques can require a semiconductor manufacturer to support or implement both thick gate and thin gate fabrication technologies. These costs can be prohibitive as many semiconductor manufacturers, such as companies having a microprocessor or device chipset business, prefer to use a single technology, such as thin gate device technology, to optimize manufacturing costs and to maximize device performance. In another example, level shifting techniques that use thin gate devices with an elevated reference can incur increased manufacturing costs, such as in terms of die area, power consumption, engineering design and support efforts. Additionally, such techniques may be challenging to scale higher data rates. In another example, generating and using an elevated reference can consume a large amount of die area due to the addition of analog circuitry, such as voltage regulators, added power supply tracks or wires, and the addition of capacitor banks and other devices for noise suppression. Such techniques can also experience increased power consumption, such as due to current leakage caused by the elevated reference leaving some devices partially turned on while a device is energized. This can require increases to a device's power budget which can limit the ability to scale such devices to higher data rates. Engineering costs can also be increased due to the need to design, validate, and tune the additional analog circuitry.
Aspects of the present disclosure include techniques (e.g., circuits, devices, systems, or methods) for an EOS and aging robust level shifter that addresses the disadvantages of existing level shifter techniques. In an example, the techniques disclosed herein include a level shifter formed using thin gate devices (e.g., transistors) that are protected from EOS by one or more thin gate p-channel field effect transistors (PFETs) that are configured as pulldown devices. Such PFETs are configured to limit or reduce the voltage across the protected devices by at least one PFET threshold voltage (Vtp) drop below the high voltage supply of the level shifter. In an example, the PFETs in the pulldown configuration (hereinafter, “pulldown PFET” or “pulldown PFETs”) generate gate signals for the protected PFET devices that have a voltage swing between the high supply voltage of the level shifter and at least one Vtp drop above the voltage reference or ground rail of the level shifter. This technique can be used, such as by adding one or more additional Vtp drops using one or more additional pulldown PFETs, to provide any suitable voltage drop to limit the EOS voltage across a protected device to an EOS target or threshold voltage.
In an example, a level shifter is fabricated using thin gate field effect transistors (FETs). The thin gate FETs include one or more pulldown PFETs that provide a constant voltage drop of at least one Vtp to limit the voltage across PFETs that are exposed to the high voltage supply of the level shifter to a voltage below the EOS target or threshold for the devices. The voltage across the protected PFETs is limited or obtained by using the pulldown PFETs to generate gate signals for the protected devices that are at least one Vtp drop above the reference voltage of the level shifter.
By using the pulldown PFETs to limit EOS voltage across thin FET devices, the level shifters formed according to the techniques described herein provide EOS and aging robustness without the use of thick gate devices or elevated ground supply references. This enables fabrication of EOS and aging robust level shifters using just a thin gate process, and eliminates the analog circuitry, increased die area, and associated analog design considerations that would otherwise be need for level shifters that use an elevated ground supply.
In an example, level shifter 100 includes control logic 105, insulated devices 110, exposed devices 115, and pulldown PFET 120. Each component of the level shifter 100, in various examples, is implemented using thin gate FETs. In other examples, level shifter 100 and one or more of its associated components are implemented using one or more other semiconductor device technology or process.
Control logic 105 includes circuitry that is configured to receive low voltage signal IN_LV (e.g., a signal in the core logic voltage domain) and to actuate, such as by providing biasing voltages or other control signals, one or more components of level shifter 100 to shift or convert IN_LV to high voltage output signal OUT_HV (e.g., a signal in the I/O voltage domain). In an example, the circuitry of control logic 105 is not exposed to VCC_HV. In other examples, control logic 105 includes devices is exposed to both VCC_HV and VCC_LV. In such examples, the exposed devices are protected by pulldown PFET 120, as described herein.
Insulated devices 110 include circuitry that is configured to be actuated or driven by control logic 105 to shift or convert IN_LV to high voltage output signal OUT_HV. In an example, insolated devices 110 includes devices that are coupled to VCC_LV and VSS and are insulated from, or are not exposed to, VCC_HV. Insulated devices 110 include, for example, control logic devices that are supplied by VCC_LV and VSS, and n-channel field effect transistors (NFETs) that form, or that are used to protect, the pulldown circuitry in the output stage of level shifter 100.
Exposed devices 115 include circuitry that is configured to be actuated or driven by control logic 105 to shift or convert IN_LV to high voltage output signal OUT_HV. Such circuitry, in various examples, include PFETs that are coupled to VCC_HV and VSS. Such PFETs can include PFETs that form the pullup circuitry in the output stage of the level shifter 100. Such PFETs can additionally include control logic PFETs that are configured to actuate the pullup circuitry or to steer signals to such circuitry.
Pulldown PFET 120 includes one or more PFETs that are configured as pulldown devices to provide EOS protection to exposed devices 115. Such protection includes, in various examples, pulldown PFET 120 generating gate signals that switch between VCC_HV and one or more Vtp drops above VSS. In an example pulldown PFET 120 can include two or more PFET devices that are cascaded to provide a suitable number of Vtp drops. ca Such protection includes, in other examples, pulldown PFET 120 providing a one or more Vtp drop between the drain of a PFET and a references node, such as VSS. This technique provides EOS protection by limiting the maximum gate-to-drain voltage VGD or gate-to-source voltage VGS a protected PFET to a value determined by VCC_HV and the number of Vtp drops provided by PFET 120. The number of Vtp drops (e.g., the number of cascaded PFETs) used to obtain a specified level of EOS protection can be determined based on, for example, the difference between VCC_HV (e.g., the maximum voltage that may be dropped across an exposed PFET in the level shifter 100) and an indicated EOS target or threshold voltage for the protected device. In an example, if VCC_HV is 1.133V and the PFETs in level shifter 100 has an EOS target of 0.9V, then two cascaded PFETs can be used to provide two Vtp voltage drop to satisfy the EOS target requirement. In some examples, pulldown PFET 120 includes one or more biasing or offsetting signals BIAS to adjust the level of EOS protection by selectively decreasing or increasing the gate biasing or drain voltage drop provided by pulldown FET 120.
Transistors MP1 and MP3 are examples of exposed PFET devices, such as exposed devices 115, that are exposed to a voltage supply having a reference voltage rail VSS and a high voltage rail VCC_HV that exceeds an EOS target or threshold voltage of the devices. Such devices may be susceptible to EOS due to their connection across VCC_HV and VSS.
Transistor MP2 is an example of a PFET, such as pulldown PFETs 120, that is configured or arranged in a pulldown configuration to provide EOS protection to MP1 and MP3. As shown in
In operation, transistors MP1, MP3 can experience EOS when a voltage across any two terminals of the devices exceeds an EOS target or threshold for the device. In a configuration of circuitry 200 where VCC_HV exceeds, or is higher than the EOS target of MP1 or MP3, transistor MP2 can protect each of these devices by ensuring a minimum voltage at node 210.
In an example, MP2 protects MP3 from gate-to-source voltage (VGS) EOS by providing or ensuring a specified minimum voltage at the gate of MP3 (e.g., the voltage at node 210). If, for example, VCC_HV is within one Vtp of the gate-to-source EOS target of MP3, then a one Vtp minimum voltage provided by MP2 at node 210 ensures that the VGS of MP3 doesn't exceed the EOS target, thereby limiting the likelihood of VGS EOS. Without MP2, VGS of MP3 could exceed the EOS target, such as when the VG of MP3 is driven to 0V to turn on the transistor. In another example, if VCC_HV is within two Vtp of the gate-to-source EOS target of MP3, then two transistors MP2 can be cascaded, such as shown in
In another example, MP2 protects MP3 from gate-to-drain (VGD) EOS by providing or ensuring a specified the minimum voltage at the drain of MP3 (e.g., node 210). In an example where MP2 is not included in circuitry 200, VGDcan exceed the gate-to-drain EOS target of MP1, such as when VG of MP1 is driven high to VCC_HV. Transistor MP2, or one or more cascaded versions of MP2, can protect MP1 from VGDby ensuring a specified minimum voltage at the drain of MP1 that is an indicated multiple of Vtp. A pulldown PFET mirroring MP2 disposed between the drain of MP3 and VS S can be used to provide similar VGD EOS protection to MP3.
In operation, the pulldown operation of MP4 provides a minimum voltage at node 305 of Vtp. This minimum voltage is coupled to the gate of MP2, thereby providing a minimum voltage at node 210 is 2×Vtp.
MP4 is additionally configured as an example of bias circuit 205, such as by providing a means to offset the voltage at the gate of MP2, or at nodes 210 or 305, by bias signal BIAS. In an example BIAS, as shown in
As shown in
In operation, level shifter 400 is configured to operate in a normal mode, such as for level shifters formed using FETs that have a low Vtp (e.g., thin FETS having a threshold voltage between 0.1-0.3V) and a bypass mode, such as for level shifters formed using FETs having a large Vtp (e.g., a threshold voltage that exceeds the low Vtp range). In an example, the level shifter mode of operation is selected through actuation of signal BYPASS.
Gate-to-source voltage EOS can be caused by a voltage between the gate and source of a PFET that exceeds an EOS target or threshold, such as when the transistors turned-on (e.g., VG is at or approaches a low voltage, such as VSS). In normal mode, VGS EOS protection for MP9, MP10, MP11, and MP12 is provided by gate signals that switch between VCC_HV and 2×Vtp above bias voltage pbias_ 2, where pbias_ 2 is a gate offset voltage such as BIAS (
A gate voltage OUT_ES_HV and OUTB_ES_HV that is 2×Vtp above pbias_ 2 is obtained at the gates of MP9, MP10, MP11, and MP12 are obtained as follows. Transistors MP1 and MP2 generates complementary signals OUT_ES_LV and OUTB_ES_LV at the source of these transistors. Signals OUT_ES_LV and OUTB_ES_LV switch between VCC_LV and pbias_2+Vtp, such as due to the pulldown configuration of the MP1 and MP2. Pulldown FETs MP7 and MP8 provide an additional Vtp to the voltage drop between their gate and source nodes to provide a minimum voltage of pbias_2+2×Vtp at their source, thereby ensuring that the gate voltages of MP9, MP10, MP11, and MP12 swing between VCC_HV and pbias_2+2×Vtp.
Gate-to-drain voltage VGDEOS can be caused by a voltage between the gate and drain of a PFET that exceeds an EOS target or threshold, such as when the transistors turned-off (e.g., VG is at a high voltage, such as VCC_HV). The normal mode VGDEOS protection provided to MP10 and MP11 is controlled by OUT_ES_HV and OUTB_ES_HV. As previously described, OUT_ES_HV and OUTB_ES_HV have a minimum voltage of pbias_2+2×Vtp., which ensures that the maximum VGDof MP10 or MP11 is VCC_HV- (pbias_2+2×Vtp).
The normal mode VGDEOS protection provided to MP9 and MP12 is controlled by pulldown FETs MP5, MP6, and bias or offset pbias_1. Due to the pulldown configuration of MP5 and MP6, the minimum value of the drain voltage of MP9 and MP12 is pbias_1+Vtp. Signal pbias_ 1 can be adjusted to control the level or margin of VGDEOS protection. In an example, pbias_ 1 has a value between 0V and 0.3×VCC_HV.
Transistors MP7 and MP8 may not require VGS EOS protection due to the source and gate voltages of these transistors tracking each other.
In bypass mode, EOS protection for MP9, MP10, MP11, and MP12 is provided by gate signals OUT_ES_HV and OUTB_ES_HV that switch between VCC_HV and Vtp. In this operating mode, NFETs MN3, MN4, MN10 and MN11 are used to pull OUT_ES_LV and OUTB_ES_LV to VSS, bypassing MP1 and MP2 and avoiding the Vtp drop obtained from MP1 and MP2. Signals OUT_ES_HV and OUTB_ES_HV are generated with a single Vtp drop at the source of MP7 and MP8, thereby ensuring a minimum VG of Vtp at the gates of MP9, MP10, MP11, and MP12.
Bypass mode VGDEOS protection for the remaining PFETs are the same as discussed for VGD EOS protection for these devices in normal mode.
As discussed herein, level shifter 400 implements the pulldown PFET provided EOS protection techniques described in the discussion of
The circuits, circuitry, or devices illustrated in the figures and described herein are illustrated or described with respect to a specified electrical polarity, such as positive or negative voltages or currents, and device dopant or charge carrier configurations, such as PFET verses NFET or n-type material verses p-type material, to improve the clarity of the discussion. Such electrical polarities or devices dopant or charge carrier configurations can be reversed or swapped where readily appreciable without loss of generally to the techniques of devices described herein. Additionally, the present disclosure is applicable to both NFET and PFET devices.
Example 1 is a level shifter circuit, comprising: one or more p-channel field effect transistors (PFETs) having source and drain terminals coupled, respectively, to a power supply node and a reference node, wherein the one or more PFETs have an electrical over stress (EOS) threshold voltage that is lower than a voltage difference between the power supply node and the reference node; and a PFET pulldown circuit coupled to a first transistor of the one or more PFETs to limit the voltage difference across at least two terminals of a second PFET of the one or more PFETs to a voltage below the EOS threshold voltage based on the threshold voltage the PFET.
In Example 2, the subject matter of Example 1 includes, wherein the PFET pulldown circuit includes a PFET that is configured to as pulldown transistor to provide an indicated minimum gate voltage to the second PFET.
In Example 3, the subject matter of Example 2 includes, wherein the indicated minimum gate voltage is an indicated integer multiple of the threshold voltage of the PFET.
In Example 4, the subject matter of Example 3 includes, wherein the indicated minimum gate voltage includes a selectable offset voltage.
In Example 5, the subject matter of Examples 2-4 includes, the PFET has an electrical over stress (EOS) threshold voltage that is lower than a voltage difference between the power supply node and the reference node.
In Example 6, the subject matter of Examples 1-5 includes, wherein the PFET pulldown circuit includes a PFET that is configured to as pulldown transistor having a source terminal coupled a drain terminal of the second PFET to provide an indicated minimum gate voltage at the drain terminal of the second PFET.
In Example 7, the subject matter of Examples 1-6 includes, wherein the reference node is a coupled to a zero-volt power supply reference.
In Example 8, the subject matter of Examples 1-7 includes, wherein the at least two terminals of a second PFET includes a gate and source of the second PFET or a gate and drain of the second PFET.
Example 9 is a level shifter device to shift a voltage of a signal from a voltage level of first logic interface to a voltage level of a second logic interface, the device comprising: first and second power supply nodes to couple, respectively, to first and second power supplies, wherein the first power supply has a voltage that is lower than a voltage of the second power supply; a reference node to couple to a power supply reference that is shared by the first power supply and the second power supply; one or more transistors having a source terminal coupled to the second power supply node and a drain terminal coupled to the reference node to provide a shifted output signal responsive to an input signal, wherein the one or more transistors are degraded responsive to a voltage between at least two terminals of the one or more transistors exceeding a threshold value, the threshold value being smaller than a voltage difference between the second power supply and the power supply reference; and a pulldown transistor coupled to a first transistor of the one or more transistors to limit the voltage difference between the at least two terminals to a voltage below the threshold value based on the threshold voltage the pulldown transistor.
In Example 10, the subject matter of Example 9 includes, wherein at least one transistor of the one or more transistors is a p-channel field effect transistor (PFET).
In Example 11, the subject matter of Examples 9-10 includes, wherein the pulldown transistor includes a PFET having a first drain terminal coupled to the second power supply node and a first source terminal coupled to the reference node.
In Example 12, the subject matter of Example 11 includes, wherein the pulldown transistor is coupled between a first drain terminal of the first transistor and the reference node to limit a voltage at the first drain terminal of the first transistor to at least the threshold voltage the pulldown transistor.
In Example 13, the subject matter of Examples 11-12 includes, wherein: the pulldown transistor is coupled to a gate terminal of the first transistor; and to limit the voltage difference between the at least two terminals, the pulldown transistor is configured to limit a voltage at a first terminal of the at least two terminals to at least the threshold voltage the pulldown transistor.
In Example 14, the subject matter of Examples 9-13 includes, wherein the pulldown transistor is coupled between a pullup and pulldown transistor of a buffer circuit.
In Example 15, the subject matter of Examples 10-14 includes, wherein the pulldown transistor includes first and second PFETs, the first PFET having a first drain coupled to the first power supply node and a first source coupled to the reference node, the second PFET having a second drain coupled to the second power supply node and a second source coupled to the reference node.
In Example 16, the subject matter of Example 15 includes, a switching element that is configured to selectively bypass the first PFET.
Example 17 is a level shifter circuit, comprising: first and second power supply nodes to couple, respectively, to first and second power supplies, wherein the first power supply has a voltage that is lower than a voltage of the second power supply; a reference node to couple to a power supply reference that is shared by the first power supply and the second power supply; one or more p-channel field effect transistors (PFETs) having a source terminal coupled to the second power supply node and a drain terminal coupled to the reference node to provide a shifted output signal responsive to an input signal, wherein the one or more PFETs have an electrical over stress (EOS) threshold voltage that is lower than a voltage difference between the second power supply and the power supply reference; and a pulldown PFET coupled to a first transistor of the one or more PFETs to limit the voltage difference between the two terminals of the one or more PFETs to a voltage level below the EOS threshold voltage based on the threshold voltage the pulldown PFET.
In Example 18, the subject matter of Example 17 includes, wherein the reference node is coupled to a zero-volt power supply reference and pulldown PFET has an EOS threshold voltage that is lower than a voltage difference between the second power supply and the power supply reference.
In Example 19, the subject matter of Examples 17-18 includes, wherein the two terminals of the one or more PFETs includes a gate and source of the one or more PFETs or a gate and drain of the one or more PFETs.
In Example 20, the subject matter of Examples 17-19 includes, wherein: the pulldown PFET has a source terminal coupled to a drain or gate terminal of the one or more PFETs; and to limit the voltage difference between the two terminals of the one or more PFETs, the pulldown PFET is configured to limit a voltage at the drain or gate terminal the two terminals of the one or more PFETs to at least the threshold voltage the pulldown transistor.
Example 21 is at least one machine-readable medium including instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement of any of Examples 1-20.
Example 22 is an apparatus comprising means to implement of any of Examples 1-20.
Example 23 is a system to implement of any of Examples 1-20.
Example 24 is a method to implement of any of Examples 1-20.
In the present disclosure, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of some example examples. It will be evident, however, to one skilled in the art that the present disclosure may be practiced without these specific details.
Examples, as described herein, may include, or may operate on, logic or a number of components, modules, or mechanisms. Modules may be hardware, software, or firmware communicatively coupled to one or more processors in order to carry out the operations described herein. Modules may be hardware modules, and as such modules may be considered tangible entities capable of performing specified operations and may be configured or arranged in a certain manner. In an example, circuits may be arranged (e.g., internally or with respect to external entities such as other circuits) in a specified manner as a module. In an example, the whole or part of one or more computer systems (e.g., a standalone, client or server computer system) or one or more hardware processors may be configured by firmware or software (e.g., instructions, an application portion, or an application) as a module that operates to perform specified operations. In an example, the software may reside on a machine-readable medium. In an example, the software, when executed by the underlying hardware of the module, causes the hardware to perform the specified operations. Accordingly, the term hardware module is understood to encompass a tangible entity, be that an entity that is physically constructed, specifically configured (e.g., hardwired), or temporarily (e.g., transitorily) configured (e.g., programmed) to operate in a specified manner or to perform part or all of any operation described herein. Considering examples in which modules are temporarily configured, each of the modules need not be instantiated at any one moment in time. For example, where the modules comprise a general-purpose hardware processor configured using software; the general-purpose hardware processor may be configured as respective different modules at different times. Software may accordingly configure a hardware processor, for example, to constitute a particular module at one instance of time and to constitute a different module at a different instance of time. Modules may also be software or firmware modules, which operate to perform the methodologies described herein.
Circuitry or circuits, as used in this document, may comprise, for example, singly or in any combination, hardwired circuitry, programmable circuitry such as computer processors comprising one or more individual instruction processing cores, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. The circuits, circuitry, or modules may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system on-chip (SoC), desktop computers, laptop computers, tablet computers, servers, smart phones, etc.
As used in any example herein, the term “logic” may refer to firmware and/or circuitry configured to perform any of the aforementioned operations. Firmware may be embodied as code, instructions or instruction sets and/or data that are hard-coded (e.g., nonvolatile) in memory devices and/or circuitry.
“Circuitry,” as used in any example herein, may comprise, for example, singly or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, logic and/or firmware that stores instructions executed by programmable circuitry. The circuitry may be embodied as an integrated circuit, such as an integrated circuit chip. In some examples, the circuitry may be formed, at least in part, by the processor circuitry executing code and/or instructions sets (e.g., software, firmware, etc.) corresponding to the functionality described herein, thus transforming a general-purpose processor into a specific-purpose processing environment to perform one or more of the operations described herein. In some examples, the processor circuitry may be embodied as a stand-alone integrated circuit or may be incorporated as one of several components on an integrated circuit. In some examples, the various components and circuitry of the node or other systems may be combined in a SoC architecture.
The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific examples that may be practiced. These examples are also referred to herein as “examples.” Such examples may include elements in addition to those shown or described. However, also contemplated are examples that include the elements shown or described. Moreover, also contemplated are examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.
Publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) are supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.
In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to suggest a numerical order for their objects.
The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with others. Other examples may be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. However, the claims may not set forth every feature disclosed herein as examples may feature a subset of said features. Further, examples may include fewer features than those disclosed in a particular example. Thus, the following claims are hereby incorporated into the Detailed Description, with a claim standing on its own as a separate example. The scope of the examples disclosed herein is to be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
