Patent Application
20250087392
The field relates to semiconductors, and more specifically, to techniques for forming semiconductor structures including thin-film resistors.
The present application relates to semiconductors, and more specifically, to techniques for forming semiconductor structures. Semiconductors and integrated circuit chips have become ubiquitous within many products, particularly as they continue to decrease in cost and size. There is a continued desire to reduce the size of structural features and/or to provide a greater amount of structural features for a given chip size. Miniaturization, in general, allows for increased performance at lower power levels and lower cost. Present technology is at or approaching atomic level scaling of certain micro-devices such as logic gates, field-effect transistors (FETs), and capacitors.
Embodiments of the invention provide structures and techniques for forming scalable thin-film resistors.
In one embodiment, a semiconductor device includes a first metallization level comprising a first electrode and a second metallization level comprising a second electrode. A resistor structure is disposed between the first electrode and the second electrode. The resistor structure comprises a first resistor element comprising a first side and a second side, wherein the first side has a larger area than an area of the second side, and a second resistor element stacked on the first resistor element, wherein the second resistor element contacts the second side of the first resistor element.
In another embodiment, a semiconductor device includes a first electrode disposed in a first a dielectric layer, a second electrode disposed in a second dielectric layer, and at least one resistor structure between the first electrode and the second electrode. The at least one resistor structure is disposed in a third dielectric layer, the at least one resistor structure comprising a first resistor element, and a second resistor element stacked on the first resistor element. A shape of the first resistor element widens in a direction away from the second resistor element, and a shape of the second resistor element narrows in a direction toward the first resistor element.
In another embodiment, a semiconductor device includes a first metallization level comprising a first electrode, a second metallization level comprising a second electrode, and a resistor structure disposed between the first electrode and the second electrode. The resistor structure comprises a first resistor element comprising a subtractive portion, and a second resistor element comprising a trench liner portion stacked on the subtractive portion. The subtractive portion comprises one of a conical shape and a trapezoidal shape and the trench liner portion comprises a V-shape.
These and other features and advantages of embodiments described herein will become more apparent from the accompanying drawings and the following detailed description.
Illustrative embodiments of the invention may be described herein in the context of illustrative structures and techniques for forming scalable thin-film resistors with varying critical dimensions, along with illustrative apparatus, systems and devices formed using such methods. However, it is to be understood that embodiments of the invention are not limited to the illustrative methods, apparatus, systems and devices but instead are more broadly applicable to other suitable methods, apparatus, systems and devices.
It is to be understood that the various features shown in the accompanying drawings are schematic illustrations that are not necessarily drawn to scale. Moreover, the same or similar reference numbers may be used throughout the drawings to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each of the drawings. Further, the terms “exemplary” and “illustrative” as used herein mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “illustrative” is not to be construed as preferred or advantageous over other embodiments or designs.
A resistor is a common electrical component used in electrical circuits, and can be found in most electrical devices. In semiconductor devices, thin-film resistors may be embedded in a chip. In illustrative embodiments, resistor structures are formed within back-end-of-line (BEOL), middle-of-line (MOL) and/or front-end of line (FEOL) interconnect layers between electrodes in different metallization layers. Depending on application, the electrodes may be connected to conductive lines including, but not necessarily limited to, power supply lines such as, for example, positive power supply lines (e.g., VDD lines) and negative power supply lines (e.g., ground or VSS lines), bitlines, wordlines and/or other types of conductive lines. As discussed in further detail below, the resistor structures are fabricated using various types of via contact (or simply via) configurations within the BEOL, MOL and/or FEOL interconnect structures to be connected between electrodes, including gate electrodes of transistors.
In illustrative embodiments, a resistor structure includes a conical or trapezoidal shaped resistor element and a V-shaped resistor element with a small contact area between the resistor elements. The resistor structure may include multiple resistor structures with the conical or trapezoidal and V-shaped resistor elements in a stacked configuration. The resistor stacks may comprise the same or different materials as each other and the resistor elements may have varied thicknesses and resistivities. The multiple resistor structures can be implemented in FEOL, MOL and BEOL applications.
Advantageously, the embodiments provide resistor structures that can have a wide range of critical dimensions and that can be scaled to smaller dimensions. The resistor structures can advantageously be applied to circuits used in, for example, cloud, machine learning and/or artificial intelligence applications.
The first ILD layer 12 is formed of any suitable dielectric material that is commonly utilized in FEOL, MOL or BEOL fabrication technologies. For example, the first ILD layer 12 can be formed of a dielectric material including, but not limited to, silicon oxide (e.g., SiO2), silicon nitride (e.g., (Si3N4)), hydrogenated silicon carbon oxide (SiCOH), hydrogenated silicon carbide (SiCH), SiCNH, tetraethyl orthosilicate (TEOS), or other types of silicon-based low-k dielectrics (e.g., k less than about 4.0), porous dielectrics, or known ULK (ultra-low-k) dielectric materials (with k less than about 2.5). The first ILD layer 12 is deposited using known deposition techniques, such as, for example, ALD (atomic layer deposition), CVD (chemical vapor deposition), PECVD (plasma-enhanced CVD), or PVD (physical vapor deposition), or spin-on deposition.
The first electrode 15 (e.g., bottom electrode) is formed by a process which comprises patterning a trench in the first ILD layer 12, lining the trench with a liner layer (e.g., diffusion barrier and/or seed layer), and filling the trench with metallic material such as copper or other suitable metallic materials. In one embodiment, the first electrode 15 is formed as part of a lower metallization level (e.g., MX-1 (see
The first resistor layer 21 is formed by depositing a layer of metallic material on the first ILD layer 12. In illustrative embodiments, the first resistor layer 21 is formed of tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN) or other metal nitrides or metal oxides, which are suitable for the given application.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
A fourth resistor layer 61 is deposited on the third ILD layer 31′ and in the trench 33′. The fourth resistor layer 61 is formed by depositing a layer of metallic material on the third ILD layer 31′ and in the trench 33′. In illustrative embodiments, the fourth resistor layer 61 is formed from the same or similar material as that of the first, second and third resistor layers 21, 41 and 51 such as, for example, TaN, TiN, WN or other metal nitrides or metal oxides, which are suitable for the given application. A thickness (e.g., height with respect to the third ILD layer 31′) of the fourth resistor layer 61 can be, for example, in the range of about 1 nm to about 200 nm. As can be seen, a portion of the fourth resistor layer 61 in the trench 33′ comprises the fourth resistor element 63 stacked on and contacting the top side of the third resistor element 52. The fourth resistor element 63 contacts the top side of the third resistor element 52 and comprises a conductive liner layer disposed in the trench 33′ in the third ILD layer 31′. The trench 33′ is disposed over the third resistor element 52. The portion of the fourth resistor layer 61 in the trench 33′ lines side surfaces and a bottom surface of the trench 33′ to form a V-shape, with the narrow portion (e.g., small area portion) of the V-shape of the fourth resistor element 63 contacting the narrow portion (e.g., small area portion) of the trapezoidal or conical shape of the third resistor element 52. As can be seen in
A fourth ILD layer 12′ is deposited on the fourth resistor layer 61, and the fourth resistor element 63 in the trench 33′. The fourth ILD layer 12′ fills in a remaining portion of the trench 33′. The fourth ILD layer 12′ may be formed of a dielectric material the same as or similar to the dielectric material of the first, second and/or third ILD layers 12, 31 and 31′, and may be deposited using the same or similar techniques as those used for deposition of the first, second and/or third ILD layers 12, 31 and 31′.
A second electrode 75 formed in the fourth ILD layer 12′. The second electrode may also be referred to herein as a top electrode. The second electrode 75 (e.g., top electrode) is formed by a process which comprises patterning a trench in the fourth ILD layer 12′, lining the trench with a liner layer (e.g., diffusion barrier and/or seed layer), and filling the trench with metallic material such as copper or other suitable metallic materials. In one embodiment, the second electrode 75 is formed as part of an upper metallization level (e.g., MX). Although third and fourth resistor elements 52 and 63 are shown in addition to the first and second resistor elements 22 and 43 disposed between the first and second electrodes 15 and 75, the embodiments are not necessarily limited thereto. Additional pairs of resistor elements in a stacked configuration similar to the pairs of first and second resistor elements 22 and 43, and third and fourth resistor elements 52 and 63 may be formed between and connected to the first and second electrodes 15 and 75.
As can be seen in
A dimension (e.g., width, diameter) of the first and third resistor elements 22 and 52 increases along a direction from the upper metallization level MX to the lower metallization level MX-1. A dimension (e.g., width) of the trenches 33 and 33′ decreases along the direction from the upper metallization level MX to the lower metallization level MX-1. A shape of the second and fourth resistor elements 43 and 63 narrows along a direction from the upper metallization level MX to the lower metallization level MX-1, and a shape of the first and third resistor elements 22 and 52 widens along a direction from the upper metallization level MX to the lower metallization level MX-1.
A shape of the first resistor element 22 widens in a direction away from the second resistor element 43, and a shape of the second resistor element 43 narrows in a direction toward the first resistor element 22. Similarly, a shape of the third resistor element 52 widens in a direction away from the fourth resistor element 63, and a shape of the fourth resistor element 63 narrows in a direction toward the third resistor element 52. The first resistor layer 21 extended from the first resistor element 22 is disposed on the first ILD layer 12 and a portion of the first resistor layer 21 contacts the first electrode. The second resistor layer 41 extended from the second resistor element 43 is disposed on the second ILD layer 31 and a portion of the second resistor layer 41 contacts the third resistor element 52. The fourth resistor layer 61 extended from the fourth resistor element 63 is disposed on the third ILD layer 31′ and a portion of the fourth resistor layer 61 contacts the second electrode 75. The second and fourth resistor elements 43 and 63 may be referred to herein as trench liner portions.
Semiconductor devices and methods for forming the same in accordance with the above-described techniques can be employed in various applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating the semiconductor devices are contemplated embodiments of the invention. Given the teachings provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.
Various structures described above may be implemented in integrated circuits. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher-level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either: (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. An example integrated circuit includes one or more semiconductor devices with the above-described contact configurations and transistors stacked in a staggered configuration.
As noted above, illustrative embodiments correspond to structures and techniques for forming scalable resistor structures with reduced areas and increased resistance, along with illustrative apparatus, systems and devices formed using such methods. Multiple pairs of resistor structures between electrodes respectively include a conical or trapezoidal shaped resistor element and a V-shaped resistor element with a small contact area between the resistor elements. The embodiments permit resistor elements to have same or different materials as each other and the thicknesses and the resistivities of the resistor elements can vary. Advantageously, the embodiments provide scalable resistor structures that can be implemented in FEOL, MOL and BEOL applications with a wide range of critical dimensions.
It should be understood that the various layers, structures, and regions shown in the figures are schematic illustrations that are not drawn to scale. In addition, for ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given figure. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures. Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
Moreover, the same or similar reference numbers are used throughout the figures to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures are not repeated for each of the figures. It is to be understood that the terms “approximately” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, temperatures, times and other process parameters, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “approximately” or “substantially” as used herein implies that a small margin of error is present, such as +5%, preferably less than 2% or 1% or less than the stated amount.
In the description above, various materials, dimensions and processing parameters for different elements are provided. Unless otherwise noted, such materials are given by way of example only and embodiments are not limited solely to the specific examples given. Similarly, unless otherwise noted, all dimensions and process parameters are given by way of example and embodiments are not limited solely to the specific dimensions or ranges given.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
