Patent Application
20070097062
The entire disclosure of Japanese Patent Applications No. 2005-313943, filed on Oct. 28, 2005, and No. 2006-224216, filed on Aug. 21, 2006 are expressly incorporated by reference herein.
1. Technical Field
The invention relates to a technology for implementing DDS in a memory liquid crystal display device.
2. Related Art
DDS (Dynamic Drive Scheme) is a known method for driving at high speed a cholesteric liquid crystal display (for example, see U.S. Pat. No. 5,748,277). In employing DDS, a voltage pattern is divided into four phases: a non-selection phase, a preparation phase, a selection phase, and an evolution phase, for application to scanning electrodes and data electrodes in a cholesteric liquid crystal display. Each of the four phases of the voltage pattern includes at least one of eight voltage values (e.g., 0to 70 V). Content is displayed by varying a voltage pattern applied to pixels.
There exists in the art a problem that conventional display drivers are not suitable for use in a DDS. Specifically, no driver has existed which is capable of supplying to scanning and data electrodes each of the eight voltage values used in a DDS.
The invention provides a display driver that is capable of satisfactorily supplying each of a voltage used in a DDS.
One example of a driver used in the art that is capable of supplying each of the eight voltage values used in a DDS is a display driver having eight N-channel transistors (hereinafter “N-ch transistor(s)”). The eight N-ch transistors are respectively related to the eight voltage values. Each N-ch transistor has a switch function for connecting a voltage source of a related voltage to a scanning electrode or data electrode. However, such a display driver involves a problem in that it is not capable of satisfactorily supplying either a high or medium voltage. This problem is inherent to N-ch transistors in that they are capable of supplying low voltages, only.
An alternative driver used in the art for supplying the required eight voltage values is a display driver having eight P-channel transistors (hereinafter “P-ch transistors”). However, such a display driver involves a problem in that it is not capable of satisfactorily supplying low and medium voltages. Again, this problem is inherent to P-ch transistors in that they are capable of supplying high voltages, only.
Another alternative of a driver used in the art is a display driver having eight combinations of N-ch and P-ch transistors, the eight combinations each having a specific transmission configuration. While such a display driver is capable of supplying a relatively wide range of voltages, it requires a large chip area to operate, which gives rise to a problem of high manufacturing costs.
According to one aspect of the invention, there is provided a scanning electrode drive device for supplying a drive signal to plural scanning electrodes in a display device having plural display pixels. The plural display pixels include memory liquid crystal layers to which are applied drive voltages corresponding to data voltages and scanning voltages when the scanning voltages are applied to the scanning electrodes and the data voltages are applied to the data electrodes, the memory liquid crystal layers being provided corresponding to intersections between the plural scanning electrodes and the plural data electrodes, and the drive signal being divided into plural phases including at least four phases: a preparation phase, a selection phase, an evolution phase, and a non-selection phase, the four phases having different effective powers which are applied to the memory liquid crystal layers, and the scanning electrode driver comprising plural switch sections having at least one transistor related to one of the data voltages or one of the scanning voltages, the transistor being connected to a target scanning electrode among the plural scanning electrodes, and the switch sections each being related to any one of voltages VP1 and VP2 (which satisfy VP1<VP2) included at least in the drive signal during the preparation phase, voltages VS1, VS2, VS3, and VS4 (which satisfy VS1<VS2<VS3<VS4, VS1=VP1, and VS4=VP2) included at least in the drive signal during the selection phase, voltages VE1 and VE2 (which satisfy VE1<VE2) included at least in the drive signal during the evolution phase, and voltages VN1 and VN2 (which satisfy VN1<VN2) included at least in the drive signal during the non-selection phase, wherein each of those of the switch sections that are related to the voltages VP1 and VN1 has an N-ch transistor, each of those of the switch sections that are related to the voltages VS2, VS3, VE1, and VE2 has an N-ch transistor and a P-ch transistor which constitute a transmission configuration, and each of those of the switch sections that are related to the voltages VP2 and VN2 has a P-ch transistor. This scanning electrode drive device is able to supply eight kinds of voltages used for a DDS.
In the scanning electrode drive device, a gate width of the N-ch transistor related to the voltage VP1 may be smaller than a gate width of the N-ch transistor related to the voltage VN1. Use of this scanning electrode drive device enables a circuit area to be reduced.
Alternatively in the scanning electrode drive device, a gate width of the P-ch transistor related to the voltage VP2 may be smaller than a gate width of the P-ch transistor related to the voltage VN2. Use of this scanning electrode drive device enables a circuit area to be further reduced.
Also alternatively in the scanning electrode drive device, gate widths of the N-ch transistor and P-ch transistor related to the voltage VE1 or VE2 may be greater than gate widths of the N-ch transistor and P-ch transistor related to the voltage VS2 or VS3. Use of this scanning electrode drive device enables a circuit area to be further reduced.
According to another aspect of the invention, there is provided a display driver having one of the scanning electrode drive devices described above. According to yet another aspect of the invention, there is provided an electronic device comprising both a display device and the display driver described above.
Embodiments of the invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements:
An embodiment of the invention will now be described. In the embodiment, a display driver (display driver) is adopted in an electronic book reader. The electronic book reader is an electronic device having a cholesteric liquid crystal display, i.e., a display device that employs memory liquid crystal. The display device displays contents (texts or images) under control of the display driver.
1. Configuration of the Electronic Book Reader
A light reflectance of the cholesteric liquid crystal layer 1411 varies depending on orientations of cholesteric liquid crystal molecules.
Description will now be made referring again to
2. DDS
3. Configuration of the Display Driver
The logic section 2 generates control signals 51 to 58 to each of the scanning electrodes under control of a controller 133. The control signals 51 to 58 each are a signal for selecting a voltage value from among eight voltage values in a voltage pattern. That is, these control signals are for selecting voltages to be output to a scanning electrode. The control signals include a signal for inducing supply of a voltage and a signal for inhibiting it. The signal for inducing supply of a voltage is, for example, a high level signal. The signal for inhibiting supply of a voltage is, for example, a low level signal.
The level shifter 3 generates control signals 61 to 68. The control signals 61 to 68 are respectively related to the control signals 51 to 58 supplied from the logic section 2. That is, the control signals 61 to 68 each correspond to any of eight voltage values included in a voltage pattern. The control signals 61 to 68 are high level signals. A control signal 5x and a control signal 6x have different voltage values. The high level control signals 61 to 68 have higher voltages than a threshold voltage which turns on gates of N-ch transistors in the output transistor section 4. As the high level control signals 61 to 68 pass through an inversion circuit, these control signals have higher voltages than a threshold voltage which turns on gates of P-ch transistors. If the control signals 51 to 58 are low level signals, the control signals 61 to 68 are also low level signals. Though the control signal 5x and the control signal 6x are low level signals, these signals have different voltage values. The control signals 61 to 68 have lower voltages than the threshold voltage which turns on the gates of the N-ch transistors in the output transistor section 4. As the low level control signals 61 to 68 pass through an inversion circuit, these control signals have lower voltages than the threshold value which turns on the gates of the P-ch transistors.
More specifically, the output transistor section 4 has a configuration as follows. The switches 71 and 72 as the first and second switches each include an N-ch transistor 8. A drain of the N-ch transistor 8 is connected to a voltage source of a voltage V1 or V2. A source of the N-ch transistor 8 is connected to a scanning electrode or data electrode. A gate of the N-ch transistor 8 is connected to an output of the level shifter 3. A back gate of the N-ch transistor 8 is grounded. A gate width W1 (e.g., a channel region) of the N-ch transistor 8 connected to the voltage source of the voltage V2 (equivalent to a voltage VP1) may be smaller than a gate width W2 of the N-ch transistor connected to the voltage source of the voltage V2 (equivalent to a voltage VN1). That is, W1<W2 may be given.
If a high level control signal is inputted to the gate of an N-ch transistor 8 from a level shifter 3, the drain and source of the N-ch transistor 8 are electrically connected to each other. As a result, the voltage V1 or V2 supplied to the drain is then fed to a scanning electrode or data electrode connected to the source. Otherwise, if a low level control signal is inputted to the gate of the N-ch transistor 8, the drain and source of the N-ch transistor 8 are electrically disconnected from each other. As a result, the voltage V1 or V2 supplied to the drain is not fed to the scanning electrode or data electrode connected to the source.
The switches 73 to 76 as the third to sixth switches each have a transmission configuration including an N-ch transistor 9 and a P-ch transistor 10. The transmission configuration means a configuration in which an N-ch transistor and a P-ch transistor are connected in parallel. A drain of the N-ch transistor 9 is connected to a voltage source of voltages V3 to V6. A source of the N-ch transistor 9 is connected to a scanning electrode or data electrode. A gate of the N-ch transistor 9 is connected to an output of the level shifter 3. A back gate of the N-ch transistor 9 is grounded. A drain of the P-ch transistor 10 is connected to a voltage source of voltages V3 to V6. A source of the P-ch transistor 10 is connected to a scanning electrode or data electrode. A gate of the P-ch transistor 10 is connected to an output of the level shifter 3 through an inversion circuit 11 (which inverts a high level voltage to a low level voltage or visa versa). A back gate of the P-ch transistor 10 is connected to a voltage source VDDH.
If the control signals 63 to 66 are at a high level, the drain and source of each of the N-ch transistor 9 and P-ch transistor 10 are electrically connected to each other. As a result, each of the voltages V3 to V6 supplied to the drains is then fed to a scanning electrode or data electrode. Otherwise, if the control signals 63 to 66 are at a low level, the drain and source of each of the N-ch transistor 9 and P-ch transistor 10 are electrically disconnected from each other. As a result, each of the voltages V3 to V6 supplied to the drains is fed to neither a scanning electrode nor data electrode. Gate widths of the N-ch transistor and P-ch transistor which are related to the voltage V3 or V6 (equivalent to a voltage VE1 or VE2) may be greater than gate widths of the N-ch transistor and P-ch transistor which are related to the voltage V4 or V5 (equivalent to a voltage VS2 or VS3).
The switches 77 and 78 as the seventh and eighth switches each include a P-ch transistor 12. A drain of the P-ch transistor 12 is connected to a voltage source of the voltage V7 or V8. A source of the P-ch transistor 12 is electrically connected to a scanning electrode or data electrode. A gate of the P-ch transistor 12 is connected to the level shifter 3 through an inversion circuit 13 (which inverts and outputs high level and low level voltages). A back gate of the P-ch transistor 12 is connected to the voltage source VDDH. A gate width W7 of the P-ch transistor 12 connected to the voltage source of the voltage V7 (equivalent to VN2) may be greater than a gate width W8 of the P-ch transistor 12 connected to a voltage source of the voltage V8 (equivalent to VP2).
If the control signal 67 or 68 is at a high level, the source and drain of the P-ch transistor 12 are electrically connected to each other. As a result, the voltage V7 or V8 supplied to the drain is then fed to a scanning electrode or data electrode connected to the source. Otherwise, if the control signal 67 or 68 is at a low level, the source and drain of the P-ch transistor 12 are electrically disconnected from each other. As a result, the voltage V7 or V8 is supplied to neither a scanning electrode nor a data electrode.
The above description has been made of the scanning electrode driver 131. The data electrode driver 132 has the same configuration as the driver 131. However, the data electrode driver 132 need not output eight kinds of voltages and hence may have a smaller number of switches than eight. In the examples of the waveforms shown in
4. Operation of an Electronic Book Reader
Operation of an electronic book reader according to the present embodiment will be described next.
A case is first assumed where an input request for inputting a voltage V6 to a target scanning electrode is given according to a DDS. For example, this case takes place triggered by a content switch request for switching contents on the cholesteric liquid crystal display. The content switch request is inputted, for example, through the UI 160. The logic section 2 supplies a high level signal as a control signal 56 (which is a signal corresponding to the voltage V6). The logic section 2 supplies low level signals as control signals 51 to 55, 57, and 58 (which are signals corresponding to the other voltages than the voltage V6). That is, a signal for inducing supply of the voltage V6 is outputted as the control signal 56. Signals for inhibiting supply of voltages V1 to V5 and V7 to V8 are outputted as the control signals 51 to 55, 57, and 58.
The level shifter 3 supplies a high level signal as a control signal 66. The level shifter 3 also supplies low level signals as control signals 61 to 65 and 67 to 68. Low level voltages are inputted to the gates of N-ch transistors 8 in the switches 71 and 72 in the output transistor section 4. As a result, the drain and source of each N-ch transistor 8 are electrically disconnected from each other. That is, neither the voltage V1 nor V2 is supplied to the target scanning electrode.
In each of the switches 73 to 75, a low level voltage is inputted to the N-ch transistor 9, and a high level voltage is inputted to the gate of the P-ch transistor 10 from the inversion circuit 11. As a result, the drain and source of each of the N-ch transistor 9 and P-ch transistor 10 are electrically disconnected from each other. That is, none of the voltages V3 to V5 is supplied to the target scanning electrode.
In the switch 76, a high level voltage is inputted to the gate of the N-ch transistor, and a low level voltage is inputted to the gate of the P-ch transistor 10. As a result, the drain and source of each of the N-ch transistor 9 and P-ch transistor 10 are electrically connected to each other. That is, the voltage V6 is supplied to the target electrode.
In each of the switches 77 and 78, a low level voltage is inputted to the inversion circuit 13. A high level voltage is inputted to the gate of the P-ch transistor 12 from the inversion circuit 13. As a result, the drain and source of the P-ch transistor are electrically disconnected from each other. That is, neither the voltage V7 nor V8 is inputted to the target scanning electrode. To summarize the above, the target electrode is not supplied with any of the voltages V1 to V5 and V7 to V8 but is supplied only with the voltage V6.
The above description has been made of an example in which a drive signal is supplied to a scanning electrode. Drive signals for data electrodes are supplied in the same manner as described above. Desired voltages are thus applied to electrooptic elements. In other words, redrawing of the display can be achieved.
As has been described above, the display driver 130 according to this embodiment uses a switch having an N-ch transistor 8 for a voltage source of a lower voltage among eight kinds of voltages which the display driver 130 can supply, as well as a switch having a P-ch transistor 12 for a voltage source of a higher voltage. A switch having an N-ch transistor and a P-ch transistor, which form a transmission configuration, is used for a voltage source of an intermediate voltage between the higher and lower voltages. Compared with an N-ch transistor, a P-ch transistor is more suitable for supply of a high voltage. Therefore, the display driver 130 according to this embodiment is able to satisfactorily supply voltages used for driving the display device 140. Further, manufacturing costs for the display driver can be further reduced compared with a case that two transistors (an N-ch transistor and a P-ch transistor) forming a transmission configuration are used in every switch.
The gate width W1 of the N-ch transistor 8 related to the voltage V1 may be smaller than the gate width W2 of the N-ch transistor 8 related to the voltage V2. Further, the gate width W8 of the P-ch transistor 12 related to the voltage V8 may be smaller than the gate width W8 of the P-ch transistor related to the voltage V7. This configuration can allow the display driver to have a smaller chip area. For example, manufacturing costs can be further reduced compared with a method of using transistors having an equal gate width as the N-ch (or P-ch) transistors 8 (or transistors 12) related to voltages V1 and V2 (or V7 and V8).
Even when voltage values of V3 to V6 applied according to the DDS need to be changed, flexible changes can be made by use of an N-ch transistor and a P-ch transistor forming a transmission configuration.
5. Further Embodiments
The invention is not limited to the above embodiment but can be variously modified.
The voltage waveforms used in DDS are not limited to those shown in
In the above embodiment, voltage values used in the voltage patterns applied to data electrodes are the same as voltage values (or a part thereof) used in the voltage pattern applied to scanning electrodes. That is, voltages which the data electrode driver 132 is capable of supplying are the same as voltages (or parts thereof) which the scanning electrode driver 131 is capable of supplying. However, voltages which the data electrode driver 132 is capable of supplying need not always be the same as voltages (or parts thereof) which the data electrode driver 132 is capable of supplying. For example, if two voltage values are used for scanning electrodes during each of the preparation phase, selection phase, evolution phase, and non-selection phase, the scanning electrode driver 131 needs a function of supplying eight voltage values. If further two voltage values are used for data electrodes separately from these voltages, the data electrode driver 132 needs a function of supplying these two voltage values. In this case, the display driver 130 has a function capable of supplying ten voltage values in total.
The scanning electrode driver 131 (or data electrode driver 132) may further have a function of switching voltages according to an external signal. In this case, a switch (transistor) is provided in the driver to mutually switch voltage sources for VE1 and VE2, for example. This function is capable of replacing voltages of the VE1, and VE2 with each other. A similar function may be provided for VS1 and VS2.
The above embodiment has been described with reference to an example in which a scanning electrode drive device is applied to an electronic book reader. However, the scanning electrode drive device according to the invention may be applied to other electronic devices (such as a document reader, an electronic paper device, etc.) than the electronic book reader. In brief, the scanning electrode drive device according to the invention is applicable to any electronic device as long as the electronic device has a display device including a memory liquid crystal layer.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-313943 | Oct 2005 | JP | national |
| 2006-224216 | Aug 2006 | JP | national |
