Patent Grant
12100358
This application claims the benefit of priority to Japanese Patent Application Number 2022-197773 filed on Dec. 12, 2022. The entire contents of the above-identified application are hereby incorporated by reference.
The following disclosure relates to a display device and particularly relates to a scanning signal line drive circuit provided with a shift register that drives scanning signal lines disposed on a display portion of the display device.
A liquid crystal display device that includes a display portion including a plurality of source bus lines (image signal lines) and a plurality of gate bus lines (scanning signal lines) has been known. In such a liquid crystal display device, a pixel forming section that forms a pixel is provided at each of intersections of the source bus lines and the gate bus lines. Each pixel forming section includes a thin film transistor (TFT) serving as a switching element, in which a gate terminal is connected to a gate bus line passing through a corresponding intersection and a source terminal is connected to a source bus line passing through the corresponding intersection, a pixel capacitance configured to hold a pixel voltage value, and the like. The liquid crystal display device also includes a gate driver (a scanning signal line drive circuit) for driving the gate bus lines and a source driver (an image signal line drive circuit) for driving the source bus lines.
An image signal indicating the pixel voltage value is transmitted through the source bus lines. However, each of the source bus lines cannot transmit image signals indicating the pixel voltage values for a plurality of rows at one time (at the same time). Thus, the image signals are sequentially written (charged) into the pixel capacitances in the plurality of pixel forming sections provided in the display portion on a row-by-row basis. In order to achieve this writing scheme, the gate driver is constituted by a shift register including a plurality of stages so as to sequentially select the plurality of gate bus lines for a predetermined period each time. Then, active scanning signals are sequentially output from the plurality of stages to cause the image signals to be sequentially written into the pixel capacitances on the row-by-row basis as described above.
Incidentally, the gate driver has been mounted as an integrated circuit (IC) chip on a peripheral portion of a substrate constituting a liquid crystal panel in many cases. However, in recent years, the gate driver is often formed directly on the substrate. Such a gate driver is referred to as a “monolithic gate driver”.
Note that, hereinafter, a circuit constituting each of the stages of the shift register in the gate driver is referred to as a “unit circuit”. With respect to an n-channel thin film transistor, of the drain and the source, whichever having a higher potential is called the drain, but among thin film transistors provided in unit circuits described below, there are some thin film transistors in which the drain and the source are switched between each other during operation. Thus, in the following description, one of two terminals that function as the drain and/or the source is referred to as a “first conduction terminal” and the other is referred to as a “second conduction terminal”. A terminal that functions as the gate of the thin film transistor is referred to as a “control terminal”.
A second conduction terminal of the thin film transistor T1, a first conduction terminal of the thin film transistor T2, a control terminal of the thin film transistor T6, a control terminal of the thin film transistor T7, a control terminal of the thin film transistor T8, a first conduction terminal of the thin film transistor T9, and one end of the capacitor C are connected to each other via a first node N1. A second conduction terminal of the thin film transistor T4, a first conduction terminal of the thin film transistor T7, a control terminal of the thin film transistor T9, and a control terminal of the thin film transistor T10 are connected to each other via a second node N2. A second conduction terminal of the thin film transistor T3, a control terminal of the thin film transistor T4, and a first conduction terminal of the thin film transistor T6 are connected to each other via a third node N3.
Operations of the unit circuit 9 will be described with reference to signal waveform diagrams illustrated in
In a period before time t91, the set signal S, the output signal Q(n), and the reset signal R are maintained at a low level. A potential of the first node N1 is maintained at the low level, a potential of the second node N2 alternately appears at a high level and the low level every predetermined period, and a potential of the third node N3 is maintained at the high level. Note that the potential of the third node N3 alternately appears at a relatively high level and a relatively low level every predetermined period.
At the time t9i, the set signal S changes from the low level to the high level. Since the thin film transistor T1 is diode-connected as illustrated in
At the time t92, the first clock signal CK1 changes from the low level to the high level. At this time, since the thin film transistor T8 is in the on state, the potential of the output terminal 29 rises along with rise of a potential of the input terminal 23. Here, since the capacitor C is provided between the first node N1 and the output terminal 29 as illustrated in
At the time t93, the first clock signal CK1 changes from the high level to the low level. As a result, the potential of the output terminal 29 falls along with fall of the potential of the input terminal 23. That is, the potential of the output signal Q(n) is set to be at the low level. In addition, the potential of the first node N1 falls via the capacitor C.
At time t94, the reset signal R changes from the low level to the high level. As a result, the thin film transistor T2 is set to be in the on state, and the potential of the first node N1 is set to be at the low level. In a period after the time t94, operations similar to the operations in the period before the time t91 are performed.
Such operations are performed in each unit circuit 9, thus the plurality of gate bus lines provided in the liquid crystal display device are sequentially set to be in the select state, and the image signals are sequentially written into the pixel capacitances on the row-by-row basis. Note that, in the following description, a period (in the example illustrated in
The unit circuit 9 having the configuration illustrated in
A configuration of the unit circuit in the shift register provided in the display device is disclosed in, for example, JP 2019-045673 A, JP 2014-063164 A, JP 2010-262296 A, JP 2013-142899 A, and JP 2010-218673 A.
Regarding the operation of the unit circuit 9, in the example illustrated in
As described above, according to the configuration of the known unit circuit 9, charging and discharging of the second node N2 are repeated throughout the non-select period. This causes an increase in power consumption of the gate driver. With respect to the thin film transistor T10 for controlling the potential of the output terminal 29, the change from the on state to the off state and the change from the off state to the on state are frequently repeated, and thus a pull-down function for pulling the potential of the output terminal 29 to the low level is not normally operated in some cases. Similarly, with respect to the thin film transistor T9 for controlling the potential of the first node N1, the change from the on state to the off state and the change from the off state to the on state are frequently repeated, and thus the pull-down function for pulling the potential of the first node N1 to the low level is not normally operated in some cases as well.
Thus, an object of the following disclosure is to achieve reduction of power consumption and stabilization of operations of the gate driver (particularly, a monolithic gate driver).
(1) A scanning signal line drive circuit according to some embodiments of the disclosure is a scanning signal line drive circuit configured to drive a plurality of scanning signal lines, the scanning signal line drive circuit including
(2) The scanning signal line drive circuit according to some embodiments of the disclosure includes the configuration of (1) described above, wherein
(3) The scanning signal line drive circuit according to some embodiments of the disclosure includes the configuration of (1) described above, wherein,
(4) The scanning signal line drive circuit according to some embodiments of the disclosure includes the configuration of (1) described above, wherein
(5) The scanning signal line drive circuit according to some embodiments of the disclosure includes the configuration of (1) described above, wherein
(6) The scanning signal line drive circuit according to some embodiments of the disclosure includes the configuration of (1) described above, wherein
(7) The scanning signal line drive circuit according to some embodiments of the disclosure includes the configuration of (1) described above, wherein
(8) The scanning signal line drive circuit according to some embodiments of the disclosure includes the configuration of (1) described above, wherein
(9) The scanning signal line drive circuit according to some embodiments of the disclosure includes the configuration of (1) described above, wherein
(10) The scanning signal line drive circuit according to some embodiments of the disclosure includes the configuration of (1) described above, wherein
(11) The scanning signal line drive circuit according to some embodiments of the disclosure includes the configuration of (1) described above, wherein
(12) The scanning signal line drive circuit according to some embodiments of the disclosure includes the configuration of (1) described above, wherein
(13) A scanning signal line drive circuit according to some embodiments of the disclosure is a scanning signal line drive circuit configured to drive a plurality of scanning signal lines, the scanning signal line drive circuit including
(14) The scanning signal line drive circuit according to some embodiments of the disclosure includes the configuration of (13) described above, wherein
(15) The scanning signal line drive circuit according to some embodiments of the disclosure includes the configuration of (13) described above, wherein
(16) A display device according to some embodiments of the disclosure includes
(17) The display device according to some embodiments of the disclosure includes the configuration of (16) described above, wherein
(18) The display device according to some embodiments of the disclosure includes the configuration of (17) described above, wherein
(19) The display device according to some embodiments of the disclosure includes the configuration of (16) described above, wherein
According to the scanning signal line drive circuit according to some embodiments of the disclosure, the unit circuit constituting each of the stages of the shift register is provided with the second third node pull-down transistor including the control terminal applied with one of the plurality of clock signals, the first conduction terminal connected to the third node, and the second conduction terminal applied with the off level potential. Different clock signals (for example, clock signals whose phases are shifted to each other by 180 degrees) are applied to the control terminal of the third node pull-up transistor configured to change a potential of the third node toward the on level and the control terminal of the second third node pull-down transistor. Thus, in each unit circuit, the potential of the third node repeats a change from the off level to the on level and a change from the on level to the off level during the non-select period. The clock signal applied to the control terminal of the second third node pull-down transistor changes from the off level to the on level at a timing when the clock signal applied to the control terminal of the third node pull-up transistor changes from the on level to the off level. Thus, in the period when the clock signal applied to the control terminal of the third node pull-up transistor is at the off level, the potential of the third node is at the off level and the second node pull-up transistor is maintained in the off state. As described above, the potential of the second node is maintained at the on level throughout the non-select period. That is, excessive charging and discharging of the second node is suppressed. As a result, power consumption is reduced. Since the stabilization transistor including the control terminal connected to the second node is prevented from repeating the change from the on state to the off state and the change from the off state to the on state during the non-select period, deterioration of the stabilization transistor is suppressed. As a result, the operation of pulling the potential of the first node or the first output node to the off level is stably performed. As described above, reduction of the power consumption and the stabilization of the operations of the scanning signal line drive circuit are achieved.
According to the scanning signal line drive circuit according to some other embodiments of the disclosure, the unit circuit constituting each of the stages of the shift register is provided with the second third node pull-down transistor including the control terminal connected to the third node, the first conduction terminal connected to the third node, and the second conduction terminal applied with one of the plurality of clock signals. The same clock signal is applied to the control terminal of the third node pull-up transistor configured to change the potential of the third node toward the on level and the second conduction terminal of the second third node pull-down transistor. With the configuration described above, in each unit circuit, the potential of the third node repeats the change from the off level to the on level and the change from the on level to the off level during the non-select period. In this regard, when the clock signal applied to the control terminal of the third node pull-up transistor changes from the on level to the off level, the potential of the third node changes from the on level to the off level via the second third node pull-down transistor. Thus, in the period when the clock signal applied to the control terminal of the third node pull-up transistor is at the off level, the potential of the third node is at the off level and the second node pull-up transistor is maintained in the off state. As described above, the potential of the second node is maintained at the on level throughout the non-select period. That is, excessive charging and discharging of the second node is suppressed. As a result, the power consumption is reduced. Since the stabilization transistor including the control terminal connected to the second node is prevented from repeating the change from the on state to the off state and the change from the off state to the on state during the non-select period, deterioration of the stabilization transistor is suppressed. As a result, the operation of pulling the potential of the first node or the first output node to the off level is stably performed. As described above, reduction of the power consumption and the stabilization of the operations of the scanning signal line drive circuit are achieved.
The disclosure will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
An embodiment will be described below with reference to the accompanying drawings. Note that it is assumed that all transistors according to the present embodiment are n-channel thin film transistors, but the disclosure is not limited to this.
The display portion 400 includes a plurality of (j) source bus lines (image signal lines) SL(1) to SL(j) and a plurality of (i) gate bus lines (scanning signal lines) GL(1) to GL(i) disposed therein. A pixel forming section 4 that forms a pixel is provided corresponding to each of intersections of the plurality of (j) source bus lines SL(1) to SL(j) and the plurality of (i) gate bus lines GL (1) to GL (i). In other words, the display portion 400 includes a plurality of (i×j) the pixel forming sections 4. Each pixel forming section 4 includes a thin film transistor (pixel TFT) 40 serving as a switching element with the control terminal connected to a gate bus line GL passing through a corresponding intersection and with the first conduction terminal connected to a source bus line SL passing through the corresponding intersection, a pixel electrode 41 connected to a second conduction terminal of the thin film transistor 40, a common electrode 44 and an auxiliary capacitance electrode 45 provided in common to the plurality of pixel forming sections 4, a liquid crystal capacitance 42 formed with the pixel electrode 41 and the common electrode 44, and an auxiliary capacity 43 formed with the pixel electrode 41 and the auxiliary capacitance electrode 45. A pixel capacitance 46 includes the liquid crystal capacitance 42 and the auxiliary capacity 43. Note that, in
The display control circuit 100 receives an image signal DAT and a group of timing signals TG such as a horizontal synchronization signal and a vertical synchronization signal transmitted from the outside, and outputs a digital video signal DV, a gate control signal GCTL for controlling an operation of the gate driver 200, and a source control signal SCTL for controlling an operation of the source driver 300. That is, the display control circuit 100 controls the operations of the gate driver 200 and the source driver 300. Note that the gate control signal GCTL includes a gate start pulse signal, a clear signal, and a gate clock signal, and the source control signal SCTL includes a source start pulse signal, a source clock signal, and a latch strobe signal.
The gate driver 200 repeats application of an active scanning signal to each of the gate bus lines GL in one vertical scanning period as a cycle, based on the gate control signal GCTL transmitted from the display control circuit 100. Note that a configuration may also be employed in which the gate driver 200 is provided on both one end side and the other end side of the gate bus lines GL (that is, a configuration in which the gate driver 200 is provided on both the left side and the right side of the display portion 400 in
The source driver 300 applies a driving image signal to each of the source bus lines SL(1) to SL(j), based on the digital video signal DV and the source control signal SCTL transmitted from the display control circuit 100. At this time, the source driver 300 sequentially holds the digital video signals DV each indicating a voltage to be applied to a respective one of the source bus lines SL, at a timing when pulses of the source clock signal are generated. Then the held digital video signals DV are converted into analog voltages at a timing when pulses of the latch strobe signal are generated. Such converted analog voltages, as the driving image signals, are applied simultaneously to all of the source bus lines SL(1) to SL(j).
As described above, the driving image signals are applied to the source bus lines SL(1) to SL(j), and the scanning signals are applied to the gate bus lines GL(1) to GL(i). As a result, an image based on the image signal DAT transmitted from the outside is displayed on the display portion 400.
As the gate control signals GCTL, gate start pulse signals (not illustrated in
Each unit circuit 2 includes an input terminal that receives any of the gate clock signals GCK1 to GCK8 as a first clock signal CK1, an input terminal that receives any of the gate clock signals GCK1 to GCK8 as a second clock signal CK2, an input terminal that receives any of the gate clock signals GCK1 to GCK8 as a third clock signal CK3, an input terminal that receives a set signal S, an input terminal that receives a reset signal R, an input terminal that receives the low level direct current power supply voltage VSS, and an output terminal for outputting an output signal Q.
When a gate clock signal input as the first clock signal CK1 to the unit circuit 2(n) at the n-th stage is represented by GCK(n), a gate clock signal whose phase is advanced by K degrees from the phase of the gate clock signal GCK(n) is represented by GCK(n−K/45), and a gate clock signal whose phase is delayed by K degrees from the phase of the gate clock signal GCK(n) is represented by GCK(n+K/45), the waveforms of the eight-phase gate clock signals are represented as illustrated in
Signals as described below are applied to input terminals of the respective stages (respective unit circuits 2) of the shift register 210. The unit circuit 2(n−3) at the (n−3)-th stage is applied with the gate clock signal GCK1 as the first clock signal CK1, and is applied with the gate clock signal GCK8 as the second clock signal CK2, and is applied with the gate clock signal GCK4 as the third clock signal CK3. The unit circuit 2(n−2) at the (n−2)-th stage is applied with the gate clock signal GCK2 as the first clock signal CK1, is applied with the gate clock signal GCK1 as the second clock signal CK2, and is applied with the gate clock signal GCK5 as the third clock signal CK3. The unit circuit 2 (n−1) at the (n−1)-th stage is applied with the gate clock signal GCK3 as the first clock signal CK1, is applied with the gate clock signal GCK2 as the second clock signal CK2, and is applied with the gate clock signal GCK6 as the third clock signal CK3. The unit circuit 2 (n) at the n-th stage is applied with the gate clock signal GCK4 as the first clock signal CK1, is applied with the gate clock signal GCK3 as the second clock signal CK2, and is applied with the gate clock signal GCK7 as the third clock signal CK3. The unit circuit 2 (n+1) at the (n+1)-th stage is applied with the gate clock signal GCK5 as the first clock signal CK1, is applied with the gate clock signal GCK4 as the second clock signal CK2, and is applied with the gate clock signal GCK8 as the third clock signal CK3. The unit circuit 2(n+2) at the (n+2)-th stage is applied with the gate clock signal GCK6 as the first clock signal CK1, is applied with the gate clock signal GCK5 as the second clock signal CK2, and is applied with the gate clock signal GCK1 as the third clock signal CK3. The unit circuit 2 (n+3) at the (n+3)-th stage is applied with the gate clock signal GCK7 as the first clock signal CK1, is applied with the gate clock signal GCK6 as the second clock signal CK2, and is applied with the gate clock signal GCK2 as the third clock signal CK3. The unit circuit 2 (n+4) at the (n+4)-th stage is applied with the gate clock signal GCK8 as the first clock signal CK1, is applied with the gate clock signal GCK7 as the second clock signal CK2, and is applied with the gate clock signal GCK3 as the third clock signal CK3. Such a configuration is repeated every eight stages through all the stages of the shift register 210. As illustrated in
The output signal Q is output from an output terminal (of each of the unit circuits 2) at each of the stages of the shift register 210 (see
In the above-described configuration, when a pulse of the gate start pulse signal as the set signal S is applied to the unit circuit 2 as a dummy stage provided at a stage prior to the first stage of the shift register 210, based on the clock operations of the gate clock signals GCK1 to GCK8, a shift pulse included in the output signal Q output from each unit circuit 2 is sequentially transferred from the unit circuit 2(1) at the first stage to the unit circuit 2(i) at the i-th stage. Then, in response to the transfer of the shift pulse, the output signals Q (scanning signals GOUT) output from the respective unit circuits 2 are sequentially set to be at the high level. As a result, as illustrated in
Note that, although the eight-phase clock signals each having a duty ratio of approximately 50% are used as the gate clock signals GCK in the present embodiment, the duty ratio and the number of phases of the gate clock signal GCK are not particularly limited thereto.
Next, a connection relationship between the components in the unit circuit 2 will be described. A second conduction terminal of the thin film transistor T1, a first conduction terminal of the thin film transistor T2, a control terminal of the thin film transistor T6, a control terminal of the thin film transistor T7, a control terminal of the thin film transistor T8, a first conduction terminal of the thin film transistor T9, and one end of the capacitor C are connected to each other via a first node N1. A second conduction terminal of the thin film transistor T4, a first conduction terminal of the thin film transistor T7, a control terminal of the thin film transistor T9, and a control terminal of the thin film transistor T10 are connected to each other via a second node N2. A second conduction terminal of the thin film transistor T3, a control terminal of the thin film transistor T4, a first conduction terminal of the thin film transistor T5 and a first conduction terminal of the thin film transistor T6 are connected to each other via a third node N3.
As for the thin film transistor T1, a control terminal and a first conduction terminal thereof are connected to the input terminal 21, and the second conduction terminal thereof is connected to the first node N1. As for the thin film transistor T2, a control terminal thereof is connected to the input terminal 22, the first conduction terminal thereof is connected to the first node N1, and a second conduction terminal thereof is connected to the input terminal 26. As for the thin film transistor T3, a control terminal and a first conduction terminal thereof are connected to the input terminal 24, and the second conduction terminal thereof is connected to the third node N3. As for the thin film transistor T4, the control terminal thereof is connected to the third node N3, a first conduction terminal thereof is connected to the input terminal 24, and the second conduction terminal thereof is connected to the second node N2. As for the thin film transistor T5, a control terminal thereof is connected to the input terminal 25, the first conduction terminal thereof is connected to the third node N3, and a second conduction terminal thereof is connected to the input terminal 26. As for the thin film transistor T6, the control terminal thereof is connected to the first node N1, the first conduction terminal thereof is connected to third node N3, and a second conduction terminal thereof is connected to the input terminal 26. As for the thin film transistor T7, the control terminal thereof is connected to the first node N1, the first conduction terminal thereof is connected to the second node N2, and a second conduction terminal thereof is connected to the input terminal 26. As for the thin film transistor T8, the control terminal thereof is connected to the first node N1, a first conduction terminal thereof is connected to the input terminal 23, and a second conduction terminal thereof is connected to the output terminal 29. Note that the thin film transistor T8 is referred to as a “buffer transistor”. As for the thin film transistor T9, the control terminal thereof is connected to the second node N2, the first conduction terminal thereof is connected to the first node N1, and a second conduction terminal thereof is connected to the input terminal 26. As for the thin film transistor T10, the control terminal thereof is connected to the second node N2, a first conduction terminal thereof is connected to the output terminal 29, and a second conduction terminal thereof is connected to the input terminal 26. As for the capacitor C, one end thereof is connected to the first node N1, and the other end thereof is connected to the output terminal 29.
The unit circuit 2 includes, as functions, a first node pull-up unit 201 configured to change the potential of the first node N1 toward the high level (on level) based on the output signal Q output from the output terminal 29 of a unit circuit 2 constituting a stage before the present stage, a first first node pull-down unit 202 configured to change the potential of the first node N1 toward the low level (off level) based on the output signal Q output from the output terminal 29 of a unit circuit 2 constituting a stage after the present stage, a stabilization circuit 203 configured to reliably maintain the potential of the output terminal 29 at the low level during the non-select period, an output control unit 204 configured to apply the potential of the first clock signal CK1 to the output terminal 29 based on the potential of the first node N1, a second first node pull-down unit 205 configured to change the potential of the first node N1 toward the low level based on the potential of the second node N2, and an output pull-down unit 206 configured to change the potential of the output terminal 29 toward the low level based on the potential of the second node N2. The first node pull-up unit 201 includes the thin film transistor T1. The first first node pull-down unit 202 includes the thin film transistor T2. The stabilization circuit 203 includes the thin film transistors T3 to T7. The output control unit 204 includes the thin film transistor T8. The second first node pull-down unit 205 includes the thin film transistor T9. The output pull-down unit 206 includes the thin film transistor T10.
Next, functions of the respective components (the thin film transistors T1 to T10 and the capacitor C) will be described. The thin film transistor T1 changes the potential of the first node N1 toward the high level when the set signal S is at the high level. The thin film transistor T2 changes the potential of the first node N1 toward the low level when the reset signal R is at the high level. The thin film transistor T3 changes the potential of the third node N3 toward the high level when the second clock signal CK2 is at the high level. The thin film transistor T4 controls the potential of the second node N2 according to the level of the second clock signal CK2 when the potential of the third node N3 is at the high level. The thin film transistor T5 changes the potential of the third node N3 toward the low level when the third clock signal CK3 is at the high level. The thin film transistor T6 changes the potential of the third node N3 toward the low level when the potential of the first node N1 is at the high level. The thin film transistor T7 changes the potential of the second node N2 toward the low level when the potential of the first node N1 is at the high level. The thin film transistor T8 applies the potential of the first clock signal CK1 to the output terminal 29 when the potential of the first node N1 is at the high level. The thin film transistor T9 changes the potential of the first node N1 toward the low level when the potential of the second node N2 is at the high level. The thin film transistor T10 changes the potential of the output terminal 29 toward the low level when the potential of the second node N2 is at the high level. The capacitor C functions as a boost capacitance for increasing the potential of the first node N1.
Note that, in the present embodiment, a first node pull-up transistor is achieved by the thin film transistor T1, a first first node pull-down transistor is achieved by the thin film transistor T2, a third node pull-up transistor is achieved by the thin film transistor T3, a second node pull-up transistor is achieved by the thin film transistor T4, a second third node pull-down transistor is achieved by the thin film transistor T5, a first third node pull-down transistor is achieved by the thin film transistor T6, a first second node pull-down transistor is achieved by the thin film transistor T7, a first output control transistor is achieved by the thin film transistor T8, a second first node pull-down transistor serving as a stabilization transistor is achieved by the thin film transistor T9, a first output node pull-down transistor serving as a stabilization transistor is achieved by the thin film transistor T10, and a first output node is achieved by the output terminal 29.
Next, operations of the unit circuit 2 will be described with reference to signal waveform diagrams illustrated in
At time immediately before time t1l, the set signal S is at the low level, the output signal Q(n) is at the low level, the reset signal R is at the low level, the potential of the first node N1 is at the low level, the potential of the second node N2 is at the high level, and the potential of the third node N3 is at the low level.
At the time t1l, the set signal S changes from the low level to the high level. Since the thin film transistor T1 is diode-connected as illustrated in
At the time t12, the first clock signal CK1 changes from the low level to the high level. At this time, since the thin film transistor T8 is in the on state, the potential of the output terminal 29 rises along with rise of a potential of the input terminal 23. Here, since the capacitor C is provided between the first node N1 and the output terminal 29 as illustrated in
At the time t13, the first clock signal CK1 changes from the high level to the low level. As a result, the potential of the output terminal 29 falls along with fall of the potential of the input terminal 23. That is, the potential of the output signal Q(n) is set to be at the low level. The potential of the first node N1 falls via the capacitor C.
At the time t14, the reset signal R changes from the low level to the high level. As a result, the thin film transistor T2 is set to be in the on state, and the potential of the first node N1 is set to be at the low level. By setting the potential of the first node N1 to be at the low level, the thin film transistors T6, T7, and T8 are set to be in the off state.
At time t15, the second clock signal CK2 changes from the low level to the high level. As a result, the thin film transistor T3 is set to be in the on state. At the time t15, the third clock signal CK3 changes from the high level to the low level. As a result, the thin film transistor T5 is set to be in the off state. At this time, the thin film transistor T6 is in the off state. As described above, at the time t15, the potential of the third node N3 changes from the low level to the high level. As a result, the thin film transistor T4 is set to be in the on state. At this time, the thin film transistor T7 is in the off state. Thus, at the time t15, the potential of the second node N2 changes from the low level to the high level.
At time t16, the second clock signal CK2 changes from the high level to the low level, and the third clock signal CK3 changes from the low level to the high level. As described above, at the timing when the second clock signal CK2 applied to the control terminal of the thin film transistor T3 changes from the high level (on level) to the low level (off level), the third clock signal CK3 applied to the control terminal of the thin film transistor T5 changes from the low level (off level) to the high level (on level). As a result, the thin film transistor T3 is set to be in the off state, and the thin film transistor T5 is set to be in the on state. As described above, at the time t16, the potential of the third node N3 changes from the high level to the low level. At this time, the thin film transistor T4 is set to be in the off state, and thus the potential of the second node N2 is maintained at the high level.
At time t17, the second clock signal CK2 changes from the low level to the high level. As a result, the thin film transistor T3 is set to be in the on state. At the time t17, the third clock signal CK3 changes from the high level to the low level. As a result, the thin film transistor T5 is set to be in the off state. At this time, the thin film transistor T6 is in the off state. As described above, at the time t17, the potential of the third node N3 changes from the low level to the high level. As a result, the thin film transistor T4 is set to be in the on state, and charges are supplied to the second node N2 from the input terminal 24. Thus, even when the leakage of the charges occurs in the thin film transistor T7 and/or T9, the potential of the second node N2 is maintained at the high level.
In the non-select period, as described above, the potential of the third node N3 repeats the change from the low level to the high level and the change from the high level to the low level, and the potential of the second node N2 is maintained at the high level. As a result, throughout the non-select period, the potential of the first node N1 and the potential of the output signal Q(n) (the potential of the output terminal 29) are maintained at the low level.
Such operations are performed in each unit circuit 2, thus the plurality of (i) gate bus lines GL(1) to GL(i) provided in the liquid crystal display device are sequentially set to be in the select state, and the image signals are sequentially written into the pixel capacitances 46. As a result, an image based on the image signal DAT transmitted from the outside is displayed on the display portion 400 (see
Note that, although the eight-phase clock signals are used as the gate clock signals GCK in the present embodiment, the number of phases of the gate clock signal GCK is not particularly limited thereto as described above. In this regard, for example, when P-phase clock signals are used, where P is a natural number, the control terminal of the thin film transistor T3 is applied with a clock signal whose phase is advanced by (360/P) degrees from a phase of a clock signal applied to the first conduction terminal of the thin film transistor T8.
Here, the sizes of the thin film transistors in the unit circuit 2 illustrated in
The thin film transistor T3 is an element for charging the third node N3. When the potential of the first node N1 is maintained at the high level in the select period, the potential of the third node N3 is desirably at the low level. The channel length of the thin film transistor T3 is made longer than the channel lengths of the other thin film transistors, so that the pull-down effect of the thin film transistor T6 is larger than the pull-up effect of the thin film transistor T3 when the thin film transistor T3 serving as the pull-up transistor of the third node N3 and the thin film transistor T6 serving as the pull-down transistor of the third node N3 are simultaneously in the on state. The channel width of the thin film transistor T3 is the same as the channel widths of the thin film transistors T4 and T5.
Since the potential of the second node N2 is maintained at the high level throughout the non-select period as described above (see
As schematically illustrated in
As described above, the phase of the second clock signal CK2 is advanced by 45 degrees from the phase of the first clock signal CK1. Thus, for example, a gate clock signal GCK applied as the second clock signal CK2 to the control terminal and the first conduction terminal of the thin film transistor T3 included in the unit circuit 2 (n) at the n-th stage and a gate clock signal GCK applied as the first clock signal CK1 to the first conduction terminal of the thin film transistor T8 included in the unit circuit 2(n−1) at the (n−1)-th stage are the same signal. In consideration of this, in the present embodiment, the wiring line (branch wiring line) for applying the gate clock signal GCK to the control terminal and the first conduction terminal of the thin film transistor T3 included in the unit circuit 2 (n) at the n-th stage and the wiring line (branch wiring line) for applying the gate clock signal GCK to the first conduction terminal of the thin film transistor T8 included in the unit circuit 2 (n−1) at the (n−1)-th stage are achieved by one wiring line (branch wiring line). Specifically, as schematically illustrated in
In the present embodiment, the increase of the circuit area is suppressed by adopting layouts illustrated in
According to the present embodiment, the unit circuit 2 constituting each of the stages of the shift register 210 in the gate driver 200 is provided with the thin film transistor T5 including the control terminal applied with one of the plurality of gate clock signals GCK, the first conduction terminal connected to the third node N3, and the second conduction terminal applied with the low level direct current power supply voltage VSS. The gate clock signal GCK (second clock signal CK2) applied to the control terminal and first conduction terminal of the thin film transistor T3 and the gate clock signal GCK (third clock signal CK3) applied to the control terminal of the thin film transistor T5 are shifted to each other by 180 degrees in phase. Thus, during the non-select period, the potential of the third node N3 repeats the change from the low level to the high level and the change from the high level to the low level. The third clock signal CK3 changes from the low level to the high level at a timing when the second clock signal CK2 changes from the high level to the low level, and thus the potential of the third node N3 is at the low level in the period when the second clock signal CK2 is at the low level, and the thin film transistor T4 is maintained in the off state. As described above, the potential of the second node N2 is maintained at the high level throughout the non-select period. That is, excessive charging and discharging of the second node N2 is suppressed. As a result, the power consumption is reduced. Since the thin film transistors T9 and T10 are prevented from repeating the change from the on state to the off state and the change from the off state to the on state during the non-select period, deterioration of the thin film transistors T9 and T10 is suppressed. As a result, a pull-down function for pulling the potential of the first node N1 to the low level and a pull-down function for pulling the potential of the output terminal 29 to the low level are stabilized. As described above, according to the present embodiment, the reduction of the power consumption and the stabilization of the operations of the gate driver 200 (monolithic gate driver) are achieved.
Modified examples of the configuration of the unit circuit 2 will be described below.
According to the present modified example, charges of the second node N2 is discharged via the thin film transistor T7 and the thin film transistor T1l. Thus, at the time t1l in
Operations of the unit circuit 2 according to the present modified example will be described with reference to
At the time t21, the set signal S changes from the low level to the high level. As a result, similarly to the time t1l in the above embodiment (see
At time t25, the first clock signal CK1 changes from the low level to the high level. As a result, the thin film transistor T3 is set to be in the on state. At the time t25, the third clock signal CK3 changes from the high level to the low level. As a result, the thin film transistor T5 is set to be in the off state. As described above, similarly to the time t15 in the above embodiment, the potential of the third node N3 and the potential of the second node N2 change from the low level to the high level.
At time t26, the first clock signal CK1 changes from the high level to the low level, and the third clock signal CK3 changes from the low level to the high level. As described above, at the timing when the first clock signal CK1 applied to the control terminal of the thin film transistor T3 changes from the high level (on level) to the low level (off level), the third clock signal CK3 applied to the control terminal of the thin film transistor T5 changes from the low level (off level) to the high level (on level). As a result, the thin film transistor T3 is set to be in the off state, and the thin film transistor T5 is set to be in the on state. As described above, at the time t26, the potential of the third node N3 changes from the high level to the low level. At this time, the thin film transistor T4 is set to be in the off state, and thus the potential of the second node N2 is maintained at the high level.
At time t27, the first clock signal CK1 changes from the low level to the high level. As a result, the thin film transistor T3 is set to be in the on state. At the time t27, the third clock signal CK3 changes from the high level to the low level. As a result, the thin film transistor T5 is set to be in the off state. As described above, similarly to the time t17 in the above embodiment, the potential of the third node N3 changes from the low level to the high level, and charges are supplied from the input terminal 24 to the second node N2 via the thin film transistor T4.
As described above, also in the present modified example, the potential of the second node N2 is maintained at the high level in the non-select period. Thus, throughout the non-select period, the potential of the first node N1 and the potential of the output signal Q(n) (the potential of the output terminal 29) are maintained at the low level.
According to the present modified example as described above, the wiring line (branch wiring line) for applying the gate clock signal GCK to the control terminal and the first conduction terminal of the thin film transistor T3 and the wiring line (branch wiring line) for applying the gate clock signal GCK to the first conduction terminal of the thin film transistor T8 can be achieved by one wiring line (branch wiring line). As a result, the effect of reducing the circuit area and an effect of reducing the number of intersections of the wiring lines can be obtained. Note that effects similar to those of the above embodiments can also be obtained.
Operations of the unit circuit 2 according to the present modified example will be described with reference to
At time t35, the second clock signal CK2 changes from the low level to the high level. As a result, the thin film transistor T3 is set to be in the on state. Since the potential of the second conduction terminal of the thin film transistor T5 rises, the thin film transistor T5 is maintained in the off state. As this time, since the potential of the first node N1 is at the low level, the thin film transistor T6 is in the off state. As described above, at the time t35, the potential of the third node N3 changes from the low level to the high level. As a result, the thin film transistor T4 is set to be in the on state. At this time, the thin film transistor T7 is in the off state. Thus, at the time t35, the potential of the second node N2 changes from the low level to the high level.
At time t36, the second clock signal CK2 changes from the high level to the low level. As a result, the thin film transistor T3 is set to be in the off state. When the potential of the second conduction terminal of the thin film transistor T5 falls, the thin film transistor T5 is set to be in the on state and the potential of the third node N3 falls. As a result, the thin film transistor T4 is set to be in the off state. Thus, the potential of the second node N2 is maintained at the high level.
At time t37, the second clock signal CK2 changes from the low level to the high level. As a result, similarly to the time t35, the potential of the third node N3 changes from the low level to the high level. As a result, the thin film transistor T4 is set to be in the on state. At this time, the thin film transistor T7 is in the off state. As described above, charges are supplied to the second node N2 from the input terminal 24 via the thin film transistor T4.
As described above, also in the present modified example, the potential of the second node N2 is maintained at the high level in the non-select period. Thus, throughout the non-select period, the potential of the first node N1 and the potential of the output signal Q(n) (the potential of the output terminal 29) are maintained at the low level.
According to the present modified example as described above, the wiring line (branch wiring line) for applying the gate clock signal GCK to the control terminal and the first conduction terminal of the thin film transistor T3 and the wiring line (branch wiring line) for applying the gate clock signal GCK to the second conduction terminal of the thin film transistor T5 can be achieved by one wiring line (branch wiring line). As a result, the effect of reducing the circuit area and the effect of reducing the number of intersections of the wiring lines can be obtained. Note that effects similar to those of the above embodiments can also be obtained.
In the above embodiment and the above first to fifth modified examples, the output signal from one output terminal 29 is applied as the scanning signal GOUT to the corresponding gate bus line GL, is applied as the reset signal R to the unit circuit 2 at the stage six stages before the present stage, and is applied as the set signal S to the unit circuit 2 at the stage four stages after the present stage. That is, the scanning signal GOUT and a signal for controlling the operations of another stage (hereinafter referred to as “an other-stage control signal” for convenience) are output from the same output terminal 29. However, the disclosure is not limited thereto, and the configuration (configuration of the present modified example) can be adopted in which the scanning signal GOUT and the other-stage control signal are output from different output terminals with respect to the unit circuit 2.
As illustrated in
The output signal Q(n) is output from the output terminal 29a and the output signal G(n) is output from the output terminal 29b. The output signal Q(n) is applied as the other-stage control signal to a unit circuit 2 constituting another stage. Specifically, the output signal Q(n) output from the output terminal 29a of the unit circuit 2(n) at the n-th stage is applied as the reset signal R to the unit circuit 2 (n−6) at the (n−6)-th stage, and is applied as the set signal S to the unit circuit 2(n+4) at the (n+4)-th stage. The output signal G(n) is applied as the scanning signal GOUT (n) to the corresponding gate bus line GL (n). As described above, in the present modified example, the input/output signals of each unit circuit 2 are as illustrated in
As for the thin film transistor T8a, a control terminal thereof is connected to the first node N1, a first conduction terminal thereof is connected to the input terminal 23, and a second conduction terminal thereof is connected to the output terminal 29a. As for the thin film transistor T8b, a control terminal thereof is connected to the first node N1, a first conduction terminal thereof is connected to the input terminal 23, and a second conduction terminal thereof is connected to the output terminal 29b. As described above, the first conduction terminal of the thin film transistor T8a and the first conduction terminal of the thin film transistor T8b are applied with the first clock signal CK1 which is the same clock signal. As for the thin film transistor T10a, a control terminal thereof is connected to the second node N2, a first conduction terminal thereof is connected to the output terminal 29a, and a second conduction terminal thereof is connected to the input terminal 26. As for the thin film transistor T10b, a control terminal thereof is connected to the second node N2, a first conduction terminal thereof is connected to the output terminal 29b, and a second conduction terminal thereof is connected to the input terminal 26.
Note that, in the present modified example, a first output node is achieved by the output terminal 29a, a second output node is achieved by the output terminal 29b, a first output control transistor is achieved by the thin film transistor T8b, and a second output control transistor is achieved by the thin film transistor T8a.
Operations of the unit circuit 2 according to the present modified example will be described with reference to
At time immediately before time t41, the set signal S is at the low level, the output signals Q(n) and G(n) are at the low level, the reset signal R is at the low level, the potential of the first node N1 is at the low level, the potential of the second node N2 is at the high level, and the potential of the third node N3 is at the low level.
At the time t41, the set signal S changes from the low level to the high level. As a result, similarly to the time t1l in the above embodiment, the potential of the first node N1 rises. As a result, the thin film transistors T6, T7, T8a, T8b, and T1l are set to be in the on state. By setting the thin film transistors T7 and T1l to be in the on state, the potential of the second node N2 is set to be at the low level. Note that, in the period from the time t41 to time t42, the first clock signal CK1 is at the low level, and thus, even when the thin film transistors T8a and T8b are in the on state, the output signals Q(n) and G(n) are maintained at the low level. Similarly to the period from time t1l to the time t14 in the above embodiment, the potential of the third node N3 and the potential of the second node N2 are maintained at the low level in the period from the time t41 to time t44.
At the time t42, the first clock signal CK1 changes from the low level to the high level. At this time, since the thin film transistors T8a and T8b are in the on state, the potentials of the output terminals 29a and 29b rise along with the rise of the potential of the input terminal 23. Here, since the capacitor C is provided between the first node N1 and the output terminal 29b as illustrated in
At the time t43, the first clock signal CK1 changes from the high level to the low level. As a result, the potentials of the output terminals 29a and 29b falls along with fall of the potential of the input terminal 23. That is, the potentials of the output signals Q(n) and G(n) are set to be at the low level. The potential of the first node N1 falls via the capacitor C.
At the time t44, the reset signal R changes from the low level to the high level. As a result, the thin film transistor T2 is set to be in the on state, and the potential of the first node N1 is set to be at the low level. By setting the potential of the first node N1 to be at the low level, the thin film transistors T6, T7, T8a, T8b, and T1l are set to be in the off state.
At time t45, similarly to the time t15 in the above embodiment, the potential of the third node N3 and the potential of the second node N2 change from the low level to the high level. In a period after the time t46, operations similar to those in the period after the time t16 in the above embodiment are performed.
Also in the present modified example, in the non-select period, the potential of the third node N3 repeats the change from the low level to the high level and the change from the high level to the low level, and the potential of the second node N2 is maintained at the high level. As a result, throughout the non-select period, the potential of the first node N1 and the potential of the output signals Q(n) and G(n) (the potentials of the output terminals 29a and 29b) are maintained at the low level.
According to the present modified example, the two thin film transistors T8a and T8b are included in the output control unit 204 in the unit circuit 2 (see
Although the disclosure has been described in detail above, the above description is exemplary in all respects and is not limited thereto. It is understood that numerous other modifications or variations can be made without departing from the scope of the disclosure.
While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.
| Number | Date | Country | Kind |
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| 2022-197773 | Dec 2022 | JP | national |
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| Number | Date | Country | |
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| 20240194151 A1 | Jun 2024 | US |
