1. Field
The present invention relates generally to data packet communications and more specifically to scheduling synchronous packet transmissions on a Time-Division Multiplexed (TDM) communications system.
2. Background
Recently there is a demand for a transmission system to handle both unicast and multicast/broadcast transmission. Unicast transmission is directed to one user, whereas multicast/broadcast is directed to multiple users. In a time-division multiplexed scheme, time slots may be scheduled for unicast or multicast/broadcast packet transmissions. Multicast and broadcast packets are typically synchronous. Thus multicast and broadcast packets are transmitted in specific time slots on a periodic basis. These synchronous packets may come from one or more sources, such as synchronous control channels, sub-synchronous control channels, or multicast/broadcast channels. Unicast packets are typically asynchronous and may be transmitted in any available slot. In other words, the synchronous packets typically have less flexible scheduling requirements than unicast packets.
Packets may take multiple time slots to complete transmission, so the unicast scheduler schedules a unicast packet to complete transmission before the next synchronous packet is sent. When scheduling an asynchronous/unicast packet, the scheduler must be aware of future synchronous packet transmissions. When scheduling a unicast packet, the scheduler looks ahead, for example, the scheduler may consider as many as 64 slots, for synchronous packets that would be due to transmit within that time. In many cases, synchronous packets are not available sufficiently in advance to allow the scheduler to plan; but the unicast scheduler must still leave the appropriate slots open for synchronous packets. There is a need, therefore, to provide a simple, generic mechanism for handling synchronous and asynchronous packet transmissions in one system.
The embodiments disclosed herein address the above stated needs by providing a synchronous packet manager that contains a data structure for scheduling future synchronous packet transmissions. Slots required for transmitting a synchronous packet can be reserved by marking the corresponding entries in a synchronous packet reservation table. Rather than writing packets to many different queues, the network device fills in a single reservation table per Base Station Transceiver Sub-system (BTS) sector.
Each entry in the reservation table may be assigned a priority, and the synchronous packet manager ensures that a lower priority packet will not preempt or overwrite a higher priority packet.
Finally, the synchronous packet manager provides a mechanism to automatically reserve slots in the reservation table on a periodic basis. This mechanism inserts placeholder reservations into the reservation tables. Each placeholder reservation has a priority to ensure the slots won't get filled by a lower priority packet.
The features, objects, and advantages of the presently disclosed method and apparatus will become more apparent from the detailed description set forth below when taken in conjunction with the drawings:
The following discussion provides one or more embodiments serving as examples, instances, and/or for illustration purposes and clarity of understanding. Any embodiment described herein is not necessarily to be construed as preferred or advantageous over other embodiments.
Increasing demand for wireless data transmission and the expansion of services available via wireless communication technology have led to the development of specific data services. One such service is referred to as High Data Rate (HDR). An example of a HDR type system is the one proposed in the “cdma2000 High Rate Packet Data Air Interface Specification” referred to as “the HAI specification” and as “TIA/EIA/IS-856.”
In one embodiment, a transmission system supports the standard protocols referred to as 1xEV-DO. As shown in
The data on a synchronous Control Channel (CC) is sent in at least one packet every 256 slots, as shown in
The basic problem in this system is to keep the synchronous and asynchronous data packets separate. In this particular system, packet transmissions are interlaced over four timeslots. A packet that takes multiple slots to transmit will occupy every fourth slot until it completes transmission, as shown in
Others have solved this problem by using a “smart scheduler” as shown in
In
The scheduling of timeslots is performed in BTS 25 of
The scheduler 27 dedicates memory for these queues and has knowledge of the timing requirements of the broadcast channel. The scheduler 27 will typically examine the head of each queue to determine if the channel has data to send. One problem with this method is complexity. This method requires extra memory to store channel information (e.g., queues). Further this method is not flexible because the scheduler is updated on introduction of each new synchronous channel.
Synchronous Packet Management
In order to solve the above-mentioned problems, the following reservation table is described. In this regard, the reservation table is a simple and flexible solution because the scheduler 27 may operate without information regarding specific types of channels. As shown in the synchronous packet reservation table 30 as in
The placeholder reservations ensure that a multi-slot unicast packet is not scheduled which overlaps the slots required by a future synchronous packet (one that may not have been written into the table yet). The synchronous packet manager 28 has no knowledge of specific synchronous channels, which makes it more flexible and capable of handling a wide range of channel types. Any number of logical channels (e.g., handled by application software) can write to the synchronous packet reservation table 30. The simplicity and flexibility of the synchronous packet manager 28 or scheduler 27 make each a good candidate for hardware implementation.
The synchronous packet manager 28 or scheduler 27 has the following advantages. First, the generic mechanism easily extends to new synchronous channel types without firmware/hardware modification. The synchronous packet manager 28 was originally designed to handle the synchronous control channel and broadcast/multicast channels, but it will easily handle the new sub-synchronous control channel as well. Second, it scales well to large numbers of logical synchronous channels. A logical channel is one instance of a particular type of channel. For example, a three sector BTS could have 48 logical broadcast channels, 3 synchronous control channels, and 3 sub-synchronous control channels. Finally, it is a simple design that could easily be implemented in hardware.
In one embodiment, the FL DSP supports a generic synchronous packet interface that can be used to transmit physical layer packets at specified start times. This interface is suitable for transmitting both synchronous control channel and broadcast channel packets, since in both cases, the host driver at the BTS knows ahead of time exactly when the packets are to be transmitted. In other words, this synchronous packet interface provides a means of bypassing the unicast scheduler and requesting a physical layer packet transmission beginning in a specific time slot.
Sync Packet Reservation Table
In one embodiment, the FL DSP maintains a sync packet reservation table for each sector, as shown in
An example of a sync packet reservation table is shown below in
Each entry in the sync packet reservation table may contain one of the following two types of reservations: a physical layer packet that should begin transmitting in the slot that it occupies; or a placeholder for a physical layer packet that should begin transmitting in the designated slot, provided that the actual packet is submitted to the sync packet manager before the scheduled start time.
Each sync packet reservation table entry contains the following parameters:
Note, a multi-slot sync packet will occupy one entry in the sync packet reservation table (i.e., the one that corresponds with its start time). The sync packet manager resolves collisions, or overlapping sync packets, at the time of scheduling, which is approximately one slot before a sync packet's start time.
Periodic Sync Packet Reservations
This section describes how and when the sync packet manager writes the “placeholder” reservations to the sync packet reservation tables.
Most synchronous packet transmissions occur on a periodic basis. The synchronous control channel, for example, has a period of 256 slots, or 64 interlace slots on an interlace. Sync packets often aren't available until only a few slots before their scheduled start time, and without any means of reserving the slots for a sync packet transmission, an overlapping multi-slot packet could get scheduled before the sync packet write even occurs. As shown in
The sync packet manager maintains a separate list of periodic reservations 60, which trigger the placeholder writes into the sync packet reservation tables. These periodic reservations are updated by the ReserveSyncSlotsCmd and the UnreserveSyncSlotsCmd. Each periodic reservation has the following properties:
The sync packet manager processes all periodic reservations every slot.
The sync packet manager maintains counters that track the period, burst length, and num slots for each periodic reservation. During the first “burst length” slots of the period, the sync packet manager writes the placeholders every “num slots.” Two examples are shown in
Two or more periodic reservations may overlap. If a reservation table entry already has a placeholder reservation, which is recorded in the scheduler, then the sync packet manager preserves the one with the highest priority.
Sync Packet Writes
This section describes how the sync packet manager processes the SendSyncPktsCmd. Each SendSyncPkts command contains one or more physical layer packets, which may be transmitted on one or more sectors (as specified by SectorMask).
When processing a SendSyncPktsCmd, the sync packet manager iterates over the packets in the command, and performs the following for each packet.
The sync packet manager must look at each reservation table of a sector to see if a sync packet is to be transmitted. As shown in
More specifically, the sync packet manager performs the following two tests when finding a sync packet reservation in the “next slot” reservation table entry:
If either test fails, then the sync packet manager issues a CSDTDEFS_SyncPktDroppedMsg for the “next slot” sync packet.
Interaction with the Unicast Scheduler
In one embodiment, the FL DSP gives priority to sync packets over unicast/asynchronous packets, so sync packet scheduling always occurs before unicast scheduling. However, if a “next slot” sync packet reservation table entry is free, then the slot is made available to the unicast scheduler. Furthermore, the sync packet manager looks ahead on the “next slot” interlace to see how many subsequent slots can be made available for unicast. This count is called SyncMaxNumSlots, which is provided to the unicast scheduler every slot for each sector. If SyncMaxNumSlots for a sector is zero then the next slot is not available for unicast data; otherwise, the unicast scheduler may schedule a packet that does not exceed SyncMaxNumSlots.
Physical layer packets do not exceed 16 slots, so the sync packet manager examines each reservation table entry on the interlace until encountering a sync packet reservation, as shown in
Note, if the “next slot” reservation table entry contains a placeholder reservation, then SyncMaxNumSlots will normally be zero (i.e., not available for unicast data). The lack of an actual sync packet for the “next slot” will result in an idle slot transmission during the next slot. In many cases, this is desirable; however, the sync packet manager also supports a mode that allows unused “next slot” placeholder reservations to be released for unicast data. This mode may be useful for bursty logical synchronous channels (e.g., some types of broadcast channels), in which unicast data could be sent if the synchronous channel does not have data available. The synchronous packet manager supports this mode via a particular placeholder reservation priority level, as described below.
For the purpose of updating SyncMaxNumSlots, placeholder packet reservations with a “next slot” 1 have a slightly different behavior. A “next slot” 1 placeholder reservation in table entry 1 will be considered available for unicast. A priority 1 placeholder reservation in table entries greater than 1 (e.g., slots 5, 9, 13, etc. in
Note: SYNC_PKT_WINDOW_SIZE will be at least 16*4=64 slots since SyncMaxNumSlots ranges from 1 to 16.
Those of skill in the art would understand that various steps or elements in the embodiments may be altered or their order rearranged without varying from the invention that has been disclosed.
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor may read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal such as the MS or reside at the BS. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The present Application for Patent claims priority to Provisional Application No. 60/503,550, entitled “SCHEDULING SYNCHRONOUS PACKET TRANSMISSIONS ON A 1xEV-DO FORWARD LINK” filed Sep. 16, 2003, and assigned to the assignee hereof and hereby expressly incorporated by reference herein.
Number | Date | Country | |
---|---|---|---|
60503550 | Sep 2003 | US |