Schmitt trigger circuit using MOS transistors and having constant threshold voltages

Abstract

An input CMOS inverter comprises a complementary pair of first and second MOS transistors having their gates connected together to receive an input signal, and a buffer circuit connected between drains of the first and second MOS transistors. The buffer circuit is preferably an analog switch circuit having a complementary pair of third and fourth MOS transistors responsive to the input signal and connected in parallel. In response to a potential variation caused at the drain of one of the first and second transistors, the buffer circuit causes a potential variation at the drain of the other transistor after a delay. There is provided a second MOS inverter having a complementary pair of fifth and sixth MOS transistors with their gates connected to the drains of the first and second transistors, respectively. A feedback circuit is connected to the output of the second inverter to suppress the potential variation at the drains of the first and second transistors. The feedback circuit preferably includes a third inverter and a complementary pair of seventh and eighth MOS transistors connected to the drains of the first and second transistors, respectively, and controlled by the third inverter.

Description

BACKGROUND OF THE INVENTION

This invention relates to a Schmitt trigger circuit (hysteresis circuit) using metal oxide semiconductor field effect transistors (MOSFETs).

Various types of Schmitt trigger circuits using MOSFETs are known. FIGS. 1 and 2 show typical examples of prior art Schmitt trigger circuits using complementary MOSFETs.

The prior art circuit shown in FIG. 1 is disclosed in an early published Japanese Patent Specification No. 54-121051, laid open on Sept. 19, 1979. This circuit comprises an input CMOS inverter 11 consisting of p-type transistors P.sub.1 and P.sub.2 and n-type transistors N.sub.1 and N.sub.2 ; a CMOS inverter 12 consisting of complementary transistors P.sub.4 and N.sub.4 connected to the output of the inverter 11; and additional transistors P.sub.3 and N.sub.3 which are connected respectively in parallel to the complementary transistors P.sub.1 and N.sub.1 and which are controlled by the inverter 12.

When an input voltage V.sub.in rises from zero volts and when it drops from V.sub.DD volts, the corresponding resistance ratios of the input CMOS inverter 11 are varied by the additional transistors P.sub.3 and N.sub.3 in response to an output voltage V.sub.out of the CMOS inverter 12, thereby realizing the hysteresis characteristic.

The operation of the circuit of FIG. 1 will now be described. It is assumed that threshold voltages of p-FETs and n-FETs are respectively V.sub.TP and V.sub.TN, ON resistances of p-FETs P.sub.1, P.sub.2 and P.sub.3 are respectively R.sub.P1, R.sub.P2 and R.sub.P3, and ON resistances of n-FETs N.sub.1, N.sub.2 and N.sub.3 are respectively R.sub.N1, R.sub.N2 and R.sub.N3.

When an input signal V.sub.in is at V.sub.DD volts (e.g. 5 volts), p-FETs P.sub.1 and P.sub.2 in the inverter 11 are nonconducting, while n-FETs N.sub.1 and N.sub.2 are conducting. Therefore, the output voltage V.sub.A of the inverter 11 is zero volts and the output voltage V.sub.out of the inverter 12 is V.sub.DD volts. Thus, FETs P.sub.3 and N.sub.3 are non-conducting and conducting, respectively.

When the input voltage V.sub.in drops from V.sub.DD -.vertline.V.sub.TP .vertline., p-FETs P.sub.1 and P.sub.2 are turned on, so that the output voltage V.sub.A of the inverter 11 will be ##EQU1## The output voltage V.sub.out is kept to V.sub.DD until V.sub.A reaches the threshold voltage V.sub.F of the inverter 12.

The ON resistance of each FET varies with the input voltage V.sub.in, and when V.sub.A exceeds V.sub.F, the output voltage V.sub.out of the inverter 12 is inverted from V.sub.DD to zero volts. The input voltage to invert the output voltage V.sub.out from V.sub.DD to zero volts is a lower threshold voltage V.sub.thL of the hysteresis circuit. When the input voltage V.sub.in is zero volts, p-FETs P.sub.1 and P.sub.2 are conducting, while n-FETs N.sub.1 and N.sub.2 are nonconducting. Thus, V.sub.A is V.sub.DD volts and V.sub.out is zero volts. At this time, p-FETs P.sub.3 and n-FET N.sub.3 are conducting and nonconducting, respectively.

In a case where the input voltage V.sub.in rises from zero volts, when V.sub.in exceeds the threshold voltage V.sub.TN of n-FETs N.sub.1 and N.sub.2, FETs N.sub.1 and N.sub.2 will turn on. At this time, V.sub.A is given by ##EQU2## V.sub.A drops with an increase in V.sub.in and when it falls below V.sub.F, the inverter 12 inverts the output voltage V.sub.out from zero volts to V.sub.DD volts. The input voltage to invert the output voltage V.sub.out from zero volts to V.sub.DD volts is a higher threshold voltage V.sub.thH of the hysteresis circuit. Suitable selection of the channel width and channel length of each of the MOS transistors which constitute the inverter 11, namely, the proper selection of the mutual conductance g.sub.m of each MOS transistor enables a modification of the hysteresis characteristic (threshold voltages and hysteresis width) of the hysteresis circuit.

With such a prior art hysteresis circuit, low-voltage and high-speed operation of the circuit are difficult since the CMOS inverter 11 at the input stage includes a series connection of four FETs P.sub.1, P.sub.2, N.sub.1 and N.sub.2 across the power supply. In addition, the threshold voltages of the circuit depend upon the ON resistances of FETs P.sub.1, P.sub.2, N.sub.1 and N.sub.2 when a current flows through the CMOS inverter 11 from the V.sub.DD terminal to the ground terminal. Therefore, the threshold voltages of the circuit are easily subject to change due to variations in the production processes.

FIG. 2 shows a Schmitt trigger circuit which is disclosed in an early published Japanese Patent Specification No. 57-67319, laid open Apr. 23, 1982.

For ease of explanation, in this circuit, the same elements as those shown in the circuit of FIG. 1 are designated by the same reference numerals. In this circuit, p-FET P.sub.3 is connected between a connection point 14 of p-FETs P.sub.1 and P.sub.2 and ground. On the other hand, n-FET N.sub.3 is connected between the V.sub.DD terminal and a connection point 15 of n-FETs N.sub.1 and N.sub.2. A CMOS inverter 13 is connected to the CMOS inverter 12, and complementary FETs P.sub.3 and N.sub.3 are controlled by the inverter 13.

In the operation of this circuit, when V.sub.in =0, p-FETs P.sub.1 and P.sub.2 are conducting and n-FETs N.sub.1 and N.sub.2 are nonconducting. Thus, V.sub.out is V.sub.DD and FETs P.sub.3 and N.sub.3 are nonconducting and conducting, respectively. Therefore, the circuit point 15 is raised to V.sub.DD -V.sub.TN. When V.sub.in rises from zero volts and exceeds V.sub.TN, n-FETs N.sub.1 and N.sub.2 conduct. At this time, the circuit point 15 is at V.sub.DD -V.sub.TN, so that the output voltage V.sub.A of the inverter 11 keeps V.sub.DD. Hence, the inverters 12 and 13 do not invert the output voltage V.sub.out.

When V.sub.in further increases and reaches, for example, 4 volts, the ON resistance of FET N.sub.1 becomes minimal and the voltage at the circuit point 15 is substantially at the ground level so that V.sub.A also approaches the ground level. Therefore, the inverters 12 and 13 invert V.sub.out from V.sub.DD to zero volts.

When V.sub.in =V.sub.DD, V.sub.out is zero volts, so that FET P.sub.3 is conducting. The voltage at the circuit point 14 is therefore lowered to .vertline.V.sub.TP .vertline.. Next, when V.sub.in drops from V.sub.DD and reaches V.sub.DD -.vertline.V.sub.TP .vertline., p-FETs P.sub.1 and P.sub.2 are turned on. However, since the circuit point 14 is at .vertline.V.sub.TP .vertline. due to conducting FET P.sub.3, V.sub.A is kept to zero volts. Therefore, the inverters 12 and 13 do not invert V.sub.out. When V.sub.in further drops and reaches, for example, 1 volt, the ON resistance of p-FET P.sub.1 becomes minimal, so that V.sub.A increases to V.sub.DD. Hence, the inverters 12 and 13 invert V.sub.out from zero volts to V.sub.DD volts.

With a Schmitt trigger circuit as shown in FIG. 2, low-voltage operation and high-speed operation are difficult like the circuit shown in FIG. 1 since a series connection of four FETs is used. However, one of the threshold voltages of the circuit depends upon the ratio of the ON resistances of p-FETs P.sub.1 and P.sub.3, and the other threshold voltage depends upon the ratio of the ON resistances of n-FETs N.sub.1 and N.sub.2, namely upon the ratio of the ON resistances of FETs of the same channel type; therefore, the change of threshold voltages of the circuit due to variations in the production processes is less than the circuit shown in FIG. 1.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a Schmitt trigger circuit which uses fewer transistors connected in series than the conventional circuits, thereby enabling both low-voltage operation and high-speed operation.

Another object of the invention is to provide a Schmitt trigger circuit in which the change of threshold voltages due to variations in the production processes is suppressed.

According to the present invention, a MOS inverter at the input stage includes a complementary pair of first and second MOS transistors having their gates connected together to receive an input signal; and a buffer circuit connected between the drains of the first and second MOS transistors which causes, in response to a potential variation at the drain of one of the first and second transistors, a potential variation at the drain of the other transistor after a delay. Furthermore, there are provided a second MOS inverter responsive to the input-stage MOS inverter, and a feedback circuit responsive to the second MOS inverter to suppress the potential variation at the drain of at least one of the first and second transistors.

Preferably, the buffer circuit includes a complementary pair of MOS transistors connected in parallel, and the second MOS inverter includes a complementary pair of MOS transistors having their gates connected to the drains of the first and second MOS transistors, respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 show prior art Schmitt trigger circuits using MOS transistors;

FIG. 3 shows a Schmitt trigger circuit using MOS transistors embodying the present invention;

FIG. 4 shows the hysteresis characteristic of the circuit of FIG. 3; and

FIGS. 5 to 14 show other embodiments of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 3, a Schmitt trigger circuit (hysteresis circuit) embodying the present invention comprises a CMOS inverter 21 having complementary FETs P.sub.11 and N.sub.11 with their gates connected together to receive an input signal V.sub.in. The sources of FETs P.sub.11 and N.sub.11 are connected to the V.sub.DD terminal and ground, respectively. In this embodiment, an analog switching circuit 22 having complementary FETs P.sub.12 and N.sub.12 connected in parallel is connected between drains D.sub.1 and D.sub.2 of FETs P.sub.11 and N.sub.11 which are to be connected together in the normal CMOS inverter. FETs P.sub.12 and N.sub.12 have also their gates connected together to receive the input signal voltage V.sub.in. This analog switching circuit 22 functions as a buffer circuit to transmit a potential variation at the drain of one of FETs P.sub.11 and N.sub.11 to the drain of other FET with a delay and vice versa. Complementary FETs P.sub.14 and N.sub.14 constitute a second CMOS inverter 23, wherein FET N.sub.14 is connected at its gate to the drain D.sub.1 of FET P.sub.11 and FET P.sub.14 is connected at its gate to the drain D.sub.2 of FET N.sub.11. The drains of FETs P.sub.14 and N.sub.14 are connected together and the sources thereof are connected to the V.sub.DD terminal and ground, respectively. p-FET P.sub.13 is connected between the drain D.sub.1 of p-FET P.sub.11 and ground, and n-FET N.sub.13 is connected between the drain D.sub.2 of n-FET N.sub.11 and the V.sub.DD terminal.

A third MOS inverter 24, which is preferably a CMOS inverter but it is not limited to this, is connected to the output of the CMOS inverter 23. FETs P.sub.13 and N.sub.13 are connected to receive the output voltage V.sub.out of the MOS inverter 24 at their gates, this output voltage V.sub.out being used as an output voltage of the Schmitt trigger circuit. Thus, FETs P.sub.13 and N.sub.13 act to prevent the potential variation at the drain of FET P.sub.11 or N.sub.11 when FET P.sub.11 or N.sub.11 changes from the OFF-state to the ON-state. The MOS inverter 24 and FETs P.sub.13 and N.sub.13 constitute a feedback circuit to control the output change of the CMOS inverter 21. In the circuit of FIG. 3, the substrates of the p-FETs are connected to V.sub.DD (e.g., 5 volts), and the substrate of the n-FETs are connected to ground (0 volts).

The operation of the circuit shown in FIG. 3 will now be described. It is now to be assumed that all FETs used are of the enhancement type, having a threshold voltage of one volt in absolute value, and that g.sub.m of each FET is designed such that the threshold voltages of the circuit become four volts (V.sub.thH) and one volt (V.sub.thL).

When V.sub.in =0, p-FETs P.sub.11 and P.sub.12 are conducting, while n-FETs N.sub.11 and N.sub.12 are nonconducting. Thus, the drains D.sub.1 and D.sub.2 of FETs P.sub.11 and N.sub.11 are at substantially V.sub.DD volts. Therefore, FETs N.sub.14 and P.sub.14 in the CMOS inverter 23 are conducting and nonconducting, respectively, so that the output node N.sub.1 is at 0 volts and the output node N.sub.2 is at V.sub.DD volts. Thus, FET N.sub.13 is conducting and FET P.sub.13 is cut off. Although FET N.sub.13 is on, since the drain D.sub.2 of FET N.sub.11 is at V.sub.DD volts, no current flows through FET N.sub.13. When V.sub.in increases and reaches, for example, 2.5 volts, n-FETs N.sub.11 and N.sub.12 conduct. Hence, the potential at the drain D.sub.2 of n-FET N.sub.11 is about to fall. However, since the drain D.sub.2 is pulled to V.sub.DD through FET N.sub.13 which is on, the fall of potential at the drain D.sub.2 is suppressed. On the other hand, the drain D.sub.1 of p-FET P.sub.11 is connected to the drain D.sub.2 of FET N.sub.11 through the ON resistance of n-FET N.sub.12, so that the potential fall at the drain D.sub.1 is further suppressed than at the drain D.sub.2. As a result of the suppression of the potential fall at the drains D.sub.1 and D.sub.2, the CMOS inverter 23 doesn't change its state. That is, V.sub.out remains at V.sub.DD volts.

When the input voltage V.sub.in further increases and exceeds 4 volts, the ON resistance of n-FET N.sub.11 becomes fairly small, causing the drain D.sub.2 to fall close to 0 volts. The drain D.sub.1 also falls close to 0 volts after a delay behind the drain D.sub.2. Consequently, the CMOS inverter 23 inverts its state to cause the output node N.sub.1 to go to V.sub.DD volts and the output node N.sub.2 to go to zero volts. Thus, FET P.sub.13 is turned on and FET N.sub.13 is turned off. Both the source and drain of FET P.sub.13 are at zero volts, so that no current flows between the source and drain thereof.

In a case where V.sub.in falls from V.sub.DD volts to 2.5 volts, p-FETs P.sub.11 and P.sub.12 conduct. At this time, since p-FET P.sub.13 is on, the potential rise at the drain D.sub.1 of p-FET P.sub.11 is suppressed, and the potential rise at the drain D.sub.2 of n-FET N.sub.11 is delayed behind the drain D.sub.1 due to the On resistance of p-FET P.sub.12. Therefore, when V.sub.in =2.5 volts, the CMOS inverter 23 doesn't change its state, so that the node N.sub.2 remains at zero volts. When V.sub.in falls to one volt, the ON resistance of FET P.sub.11 becomes fairly small and the potential at the drain D.sub.1 becomes close to V.sub.DD. The potential at the drain D.sub.2 also approaches V.sub.DD along with the drain D.sub.1, so that the CMOS inverter 23 changes its state to cause the node N.sub.2 to go to V.sub.DD.

FIG. 4 shows the input/output characteristic of the Schmitt trigger circuit of FIG. 3 which operates in a manner such as was described above. This circuit has a higher threshold voltage V.sub.thH and a lower threshold voltage V.sub.thL than a threshold voltage of an ordinary CMOS inverter.

The circuit of the present invention also has fewer FETs to be connected in series across the power supply than the conventional circuits. Therefore, the circuit of the invention can operate from a lower power supply voltage than the conventional circuits, with the result that high-speed operation can be attained. Furthermore, the gates of FETs N.sub.14 and P.sub.14 of CMOS inverter 23 are individually connected to the drains D.sub.1 and D.sub.2 of FETs P.sub.11 and N.sub.11 ; consequently, the load capacitance of the drains D.sub.1 and D.sub.2 are reduced to half of those in the prior art Schmitt trigger circuits of FIGS. 1 and 2, thereby providing a further advantage for high-speed operation.

According to the circuit of the present invention, the threshold voltages V.sub.thL and V.sub.thH depend upon the ratio of the ON resistances of p-FETs P.sub.11 and P.sub.13 and the ratio of the ON resistances of n-FETs N.sub.11 and N.sub.13 ; in other words, they depend upon the dimensional ratio of p-FETs and the dimensional ratio of n-FETs. Therefore, the threshold voltage V.sub.thL and V.sub.thH of the circuit hardly change even if the threshold voltage of each FET varies due to variations in the manufacturing process. In the case of prior art circuits of FIGS. 1 and 2, if the threshold voltage of an FET varies, for example, in the positive direction, V.sub.thL and V.sub.thH will also vary in the positive direction. On the other hand, in the circuit of the present invention, since the drain D.sub.1 of p-FET P.sub.11 is connected to the gate of n-FET N.sub.14, and the drain D.sub.2 of n-FET N.sub.11 is connected to the gate of p-FET P.sub.14, the variations of threshold voltages of FETs are cancelled out. Therefore, the influence of the variations of threshold voltages of FETs on the threshold voltages V.sub.thL and V.sub.thH of the circuit is reduced.

The Schmitt trigger circuit of the present invention is not limited to the embodiment shown in FIG. 3, but various modifications can be made. FIGS. 5 to 14 show examples of such modifications of the circuit of FIG. 3. In these examples, the same elements as those shown in FIG. 3 are designated by the same reference numerals.

With reference to the circuit of FIG. 5, in the buffer circuit 22, the substrate of n-FET N.sub.12 is connected to the drain D.sub.1 of p-FET P.sub.11, and the substrate of p-FET P.sub.12 is connected to the drain D.sub.2 of n-FET N.sub.11. The operation of the circuit of FIG. 5 is the same as the operation of the circuit of FIG. 3.

The buffer circuit 22 is provided to prevent a coincidence of the potential variations at the drains D.sub.1 and D.sub.2 of FETs P.sub.11 and N.sub.11 of the input CMOS inverter 21. Therefore, as shown in FIG. 6, a resistor R having a value of, for instance, 10 kiloohms may be used in place of analog switches P.sub.12 and N.sub.12 to accomplish a function similar to that of the circuit of FIG. 5. However, with such a resistor, the Schmitt trigger circuit will occupy a large area in an integrated circuit than would the circuit using analog switches as shown in FIG. 3. The resistor R may be divided into three resistors R.sub.1, R.sub.2 and R.sub.3 as shown in FIG. 7. As shown in FIG. 8, the resistor R may also be divided into two resistors R.sub.1 and R.sub.2 with the connection point thereof connected to the CMOS inverter 23. In this example, since FETs P.sub.14 and N.sub.14 which constitute the CMOS inverter 23 have their gates connected together to the connection point of resistors R.sub.1 and R.sub.2, an inverter using only p-FETs or n-FETs may be used in place of the CMOS inverter 23.

In the circuit of FIG. 9, the drains D.sub.1 and D.sub.2 of complementary FETs P.sub.11 and N.sub.11 of the CMOS inverter 21 are respectively connected to the gates of complementary FETs P.sub.14 and N.sub.14 of the CMOS inverter 23. Unlike the circuit of FIG. 3, in the circuit of FIG. 9 it is impossible to obtain the advantageous effect that the variations of the threshold voltages of complementary FETs are cancelled out. However, the low-voltage operation and high-speed operation can be achieved.

In the circuit of FIG. 10, the third inverter 24, which is used in the circuits described above, is omitted and complementary FETs P.sub.13 and N.sub.13 are mutually exchanged. According to this circuit, the threshold voltages will be influenced due to variations of the manufacturing process; however, the low-voltage operation and high-speed operation can be advantageously performed.

In the circuit of FIG. 11, two MOS inverters 24a and 24b are cascade-connected between the CMOS inverter 23 and complementary FETs P.sub.13 and N.sub.13 in the circuit shown in FIG. 10. The cascade connection of these two inverters 24a and 24b can provide a waveform-shaping effect, allowing the high-speed response of the Schmitt trigger circuit.

In the circuit of FIG. 12, a part of the feedback circuit (e.g., p-FET P.sub.13) is omitted. In this case, the threshold voltage V.sub.thH of the Schmitt trigger circuit is the threshold voltage of the input CMOS inverter 22. On the other hand, in the case where n-FET N.sub.13 is omitted, V.sub.thL corresponds to the threshold voltage of the CMOS inverter 21.

In the circuit shown in FIG. 13, the feedback voltages are separately applied to FETs P.sub.13 and N.sub.13. In other words, the feedback voltage is applied from the drains D.sub.1 of FET P.sub.11 through inverters 24.sub.11 and 24.sub.12 to p-FET P.sub.13. The other feedback voltage is applied from the drain D.sub.2 of FET N.sub.11 through inverters 24.sub.21 and 24.sub.22 to n-FET N.sub.13.

In the circuit of FIG. 14, the feedback voltage is applied from the drain D.sub.2 of FET N.sub.11 through inverters 24.sub.11 and 24.sub.12 to FET P.sub.13. The feedback voltage is applied from the drain D.sub.1 of FET P.sub.11 through inverters 24.sub.21 and 24.sub.22 to FET N.sub.13.

Claims

1. A Schmitt trigger circuit having lower and higher threshold voltages, comprising:

first and second power supply terminals between which an operating voltage is applied;

first MOS inverter means including a complementary channel conductivity pair of first and second MOS transistors each having a drain, a source and a gate, said first and second MOS transistors having their gates connected together to receive an input voltage signal, and their sources connected to said first and second power supply terminals, respectively, and circuit means connected between the drains of said first and second MOS transistors for transmitting a potential variation at the drain of one of said first and second MOS transistors, which potential variation is caused by a voltage variation of said input voltage signal, to the drain of the other transistor after a delay;

second MOS inverter means responsive to said first MOS inverter means; and

feedback circuit means responsive to said second MOS inverter for suppressing the potential variation at the drain of at least one of said first and second MOS transistors of said first MOS inverter means until said input voltage signal becomes lower than said lower threshold voltage or higher than said higher threshold voltage of said Schmitt trigger circuit; and

output means coupled to said feedback circuit means for providing an output voltage signal of said Schmitt trigger circuit.

2. A Schmitt trigger circuit according to claim 1, wherein said second MOS inverter means comprises a complementary channel conductivity pair of third and fourth MOS transistors each having a drain, a source and a gate, and connected with the source-drain paths thereof in series between said first and second power supply terminals, the gates of said third and fourth MOS transistors being connected to the drains of said first and second MOS transistors, respectively.

3. A Schmitt trigger circuit according to claim 2, wherein said third and fourth MOS transistors are complementary to said first and second MOS transistors, respectively, and the sources of said third and fourth MOS transistors are connected to said second and first power supply terminals, respectively.

4. A Schmitt trigger circuit according to claim 2, wherein said third and fourth MOS transistors are complementary to said second and first MOS transistors, respectively, and the sources of said third and fourth MOS transistors are connected to said first and second power supply terminals, respectively.

5. A Schmitt trigger circuit according to claim 1, wherein said circuit means comprises a complementary channel conductivity pair of parallel-connected MOS transistors having their gates connected together to receive the input signal.

6. A Schmitt trigger circuit according to claim 1, wherein said circuit means comprises resistor means.

7. A Schmitt trigger circuit according to claim 1, wherein said feedback circuit means comprises third MOS inverter means connected to said second MOS inverter means, and a complementary channel conductivity pair of third and fourth MOS transistors each having a drain-source path and a gate, said third and fourth MOS transistors being complementary to said second and first MOS transistors, respectively, and having their gates connected together to an output of said third MOS inverter means, and their drain-source paths connected between the drain of said first MOS transistor and said second power supply terminal and between the drain of said second MOS transistor and first power supply terminal, respectively.

8. A Schmitt trigger circuit according to claim 1, wherein said feedback circuit means comprises a complementary pair of third and fourth MOS transistors each having a source-drain path and gate, said third and fourth MOS transistors being complementary to said first and second MOS transistors, respectively, and having their gates connected together to an output of said second MOS inverter means, and their drain-source paths connected between the drain of said first MOS transistor and said second power supply terminal and between the drain of said second MOS transistor and said first power supply terminal, respectively.

9. A Schmitt trigger circuit according to claim 8, wherein said feedback circuit means further comprises a cascade connection of an even number of inverters between the output of said second MOS inverter means and the gates of said third and fourth MOS transistors.

10. A Schmitt trigger circuit according to claim 1, wherein said second MOS inverter means comprises cascade connected inverter pairs each connected to a respective one of the drains of said first and second MOS transistors, and wherein said feedback circuit means is arranged to suppress the potential variations at the drains of said first and second MOS transistors in response to said pair of inverters.

11. A Schmitt trigger circuit according to claim 1, wherein said feedback circuit means comprises a third MOS inverter connected to said second MOS inverter means and a third MOS transistor having a source-drain path and a gate, said third MOS transistor having its source-drain path connected in series with the source-drain path of one of said first and second MOS transistors of the same channel type as said third MOS transistor between said first and second power supply terminals, and its gate connected to an output of said third MOS inverter.

12. A Schmitt trigger circuit comprising:

first and second power supply terminals between which an operating voltage is applied;

first MOS inverter means including a complementary channel conductivity pair of first and second MOS transistors each having a drain, a source and a gate, said first and second MOS transistors having their gates connected together to receive an input voltage signal, and their sources connected to said first and second power supply terminals, respectively, and a complementary channel conductivity pair of third and fourth MOS transistors each having a gate, a source, and a drain, said third and fourth MOS transistors having their source-drain paths connected in parallel between said drains of said first and second MOS transistors and their gates connected together to receive the input voltage signal;

second MOS inverter means having a complementary channel conductivity pair of fifth and sixth MOS transistors each having a drain, a source and a gate, said fifth and sixth MOS transistor having their drains connected together, their sources connected to said second and first power supply terminals respectfully, and their gates connected to the drains of said first and second MOS transistors, respectively;

third MOS inverter means having an input connected to said drains of said fifth and sixth MOS transistors; and

a seventh MOS transistor have a source-drain path and a gate, said seventh MOS transistor having its source-drain path connected in series with one of said first and second MOS transistors of the same channel type between said first and second power supply terminals, and its gate connected to an output of said third MOS inverter means.

13. A Schmitt trigger circuit according to claim 12, further comprising an eighth MOS transistor having a source-drain path and gate, said eighth MOS transistor being complementary to said seventh MOS transistor, and having its source-drain path connected in series with the other of said first and second MOS transistors of the same channel type between said first and second power supply terminals, and its gate connected to the output of said third MOS inverter means.

14. A Schmitt trigger circuit according to claim 12, wherein said fifth and sixth MOS transistors are complementary to said first and second MOS transistors, respectively.

15. A Schmitt trigger circuit according to claim 12, wherein said fifth and sixth MOS transistors are complementary to said second and first MOS transistors, respectively.

16. A Schmitt trigger circuit comprising:

first and second power supply terminals between which an operating voltage is applied;

first MOS inverter means including a complementary channel conductivity pair of first and second MOS transistors each having a drain, a source and a gate, said first and second MOS transistors having their gates connected together to receive an input voltage signal, and their sources connected to said first and second power supply terminals, respectively, and a complementary channel conductivity pair of third and fourth MOS transistors having their source-drain paths connected in parallel between said drains of said first and second MOS transistors and their gates connected together to receive the input voltage signal;

second and third MOS inverter means having their inputs connected to the drains of said first and second MOS transistors, respectively;

fourth and fifth MOS inverter means having their inputs connected to outputs of said second and third MOS inverter means, respectively; and

a complementary channel conductivity pair of fifth and sixth MOS transistors each having a source-drain path and a gate, said fifth transistor having its source-drain path connected in series with one of said first and second MOS transistors of the same channel type between said first and second power supply terminals, and its gate connected to an output of one of said fifth and sixth MOS inverters, and said sixth transistor having its source-drain path connected in series with the other of said first and second MOS transistors of the same channel type between said first and second power supply terminals, and its gate connected to an output of the other of said fifth and sixth MOS inverters.

17. A Schmitt trigger circuit comprising:

first and second power supply terminals between which an operating voltage is applied;

first MOS inverter means including a complementary channel conductivity pair of first and second MOS transistor each having a drain, a source and a gate, said first and second MOS transistors having their gates connected together to receive an input voltage signal, and their sources connected to said first and second power supply terminals respectively, and a complementary channel conductivity pair of third and fourth MOS transistors having their source-drain paths connected in parallel between said drains of said first and second MOS transistors and their gates connected together to receive the input voltage signal;

second MOS inverter means having a complementary channel conductivity pair of fifth and sixth MOS transistors each having a drain, a source and a gate, said fifth and sixth MOS transistors being complementary to said first and second MOS transistors, respectively, and their drains being connected together, their sources connected to said second and first power supply terminals, respectively, and their gates connected to the drains of said first and second transistors, respectively; and

a complementary channel conductivity pair of seventh and eighth MOS transistors each having a source-drain path and a gate, said seventh and eighth MOS transistors having their gates connected to the drains of said fifth and sixth transistors, said seventh transistor having is source-drain path connected between said first and second power supply terminals in series with one of said first and second transistors which is complementary to said seventh transistor, and said eighth transistor having its source-drain path connected between said first and second power supply terminals in series with the other of said first and second transistors, which is complementary to said eighth transistor.