Patent Application
20230401033
The present invention relates to a technique for aligning the most significant bit (hereinafter, also referred to as Most Significant Bit (MSB)) with a predetermined bit position (hereinafter, also referred to as “MSB alignment”) in secure computation.
In plaintext, a multiply-accumulate operation is a repetition of addition, but in secure computation based on secret sharing, it is necessary to be able to perform parallel processing in order to improve computation efficiency (see NPL 1 and NPL 2). In addition, in consideration of the accuracy, it is necessary to construct a special computation for the sum and the product sum.
Although it is desired to reduce the MSB to be constant at the time of input because the product sum has a high bit output, if the product sum is simply shifted to the right, the small input are lost and the accuracy is lowered.
An object of the present invention is to provide a secure MSB normalization system, a distributed processing apparatus, a secure MSB normalization method, and a program capable of performing MSB alignment while maintaining accuracy by shifting the entire vector all at once by shifting the MSB (called vector MSB) of the data with the largest absolute value among the elements included in the vector to a predetermined bit position (called vector MSB normalization).
In order to solve the above problem, according to one aspect of the present invention, a secure MSB normalization system includes n distributed processing apparatuses. Each of the n distributed processing apparatuses includes a bit decomposition unit, a logical sum acquisition unit, a shift amount acquisition unit, and a shift unit. The n bit decomposition units decompose a vector [[{right arrow over ( )}a]]P of a (k, n)-secret shared share into bits and obtain a bit representation [[{right arrow over ( )}a]]2{circumflex over ( )}L of the vector [[{right arrow over ( )}a]]P, the n logical sum acquisition units obtain a logical sum [[Ai]]2 of all elements for a vector [[{right arrow over ( )}a]] at each bit position of the bit representation [[{right arrow over ( )}a]]2{circumflex over ( )}L, the n shift amount acquisition units obtain a share <<ρ>>p obtained by distributing a shift amount ρ for shifting the most significant bit of a logical sum [[A0]]2, . . . , [[AL−1]]2 to a fixed position by (k, n)-replica secret sharing by a modulus p, and the n shift units obtain a vector [[2ρ{circumflex over ( )}a]]p in which each element of the vector [[{right arrow over ( )}a]]P is shifted left by ρ bits.
In order to solve the above problem, according to another aspect of the present invention, the distributed processing apparatus is included in a secure MSB normalization system. The distributed processing apparatus includes a bit decomposition unit configured to obtain a bit representation [[{right arrow over ( )}a]]2{circumflex over ( )}L of a vector [[{right arrow over ( )}a]]P by bit-decomposing the vector [[{right arrow over ( )}a]]P of a (k, n)-secret shared share together with (n−1) distributed processing apparatuses, a logical sum acquisition unit configured to obtain a logical sum [[Ai]]2 of all elements for a vector [[{right arrow over ( )}ai]] at each bit position of the bit representation [[{right arrow over ( )}a]]2{circumflex over ( )}L together with the (n−1) distributed processing apparatuses, a shift amount acquisition unit configured to obtain a share <<ρ>>p obtained by distributing a shift amount ρ for shifting the most significant bit of a logical sum [[A0]]2, . . . , [[AL−1]]2 to a fixed position by (k, n)-replica secret sharing by a modulus p together with the (n−1) distributed processing apparatuses, and a shift unit configured to obtain a vector [[2ρ{circumflex over ( )}a]]p in which each element of the vector [[{right arrow over ( )}a]]p is shifted left by ρ bits together with the (n−1) distributed processing apparatuses.
According to the present invention, there is an effect that MSB alignment can be performed while maintaining accuracy.
Hereinafter, embodiments of the present invention will be described. In the diagrams used for the following description, the same reference numerals are given to components having the same functions or steps of performing the same processing, and repeated description thereof will be omitted. In the following descriptions, symbols “{circumflex over ( )}” or the like that will be used in the text that should naturally be placed above the characters that follow them are instead placed before the characters due to the limitation of the text notation. In formulas, these symbols are written at the original positions. Further, processing performed in units of respective elements such as vectors and matrices will be applied to all the elements of the vector or the matrices unless otherwise specifically noted.
First, the notation in the present embodiment will be described.
⊚ k: A threshold value of secret sharing. For example, 2.
⊚ n: The number of secret sharing distributions, in other words, the number of secure computation parties. For example, 3.
⊚ P: Prime number. In the present embodiment, the Marsenne prime number 261−1 is assumed, and the processing efficiency is improved.
⊚ p: The number of bits of P. When P is the Marsenne prime, it is also a prime number, which is 61.
⊚ Q: The order of the quotient ring. It means a general order including P, p and the order used for the floating point exponent part. Especially when used for the share of the exponent part of the floating point, 213−1 is assumed.
⊚ L: The maximum bit length of the data to be stored. P is assumed to be smaller than p.
⊚ λ: The maximum bit length of the exponent part to be stored. It is assumed 10 or less.
⊚ [[x]]y: A share obtained by distributing a mod y element x by (k, n)-secret sharing.
⊚<x>y: A share obtained by distributing a mod y element x by (k, k)-additive secret sharing.
⊚<<x>>y: A share obtained by distributing a mod y element x by (k, n)-replica secret sharing. Since it is (k, n)-secret sharing, the protocol applicable to the share in the form of [[x]]y can also be applied to this share. In this case, it means that the nature of the replica secret sharing is utilized in particular.
⊚ [[x]]2{circumflex over ( )}m: A share in which m shares in [[x]]2 format are lined up. It may be regarded as a bit representation of a numerical value. In addition, A{circumflex over ( )}B in the subscript means AB, and A_B means AB.
⊚ ρ o{right arrow over ( )} a: A vector obtained by applying rotation ρ to a vector {right arrow over ( )} a. Since the rotation is both a number and a permutation, it is distinguished from the multiplication ρ{right arrow over ( )} a for each element.
⊚ xy: x and y are equal as real numbers on the computer. That is, the difference is within a fixed error range.
⊚ a/d: Integer division rounded down to the nearest whole number. In particular, the integer division with a power of 2 is equal to a right shift.
⊚ {proposition}: 1 if the proposition holds, 0 if it does not hold.
Next, two secret sharing, (k, n)-secret sharing and (k, k)-additive secret sharing, used in the present embodiment will be described.
<(k, n)-Secret Sharing>
(k, n)-Secret sharing is a security technology that divides the input plaintext into n fragments (called shares), distributes them to n different subjects (called parties), restores if any k shares are available, and no information about plaintext can be obtained with less than k−1. For example, examples thereof include Shamir's secret sharing and replica secret sharing. In the present embodiment, a set that is distributed by (k, n)-secret sharing and collects all shares whose plaintext is a certain value x (also referred as a (k, n)-secret sharing value) is expressed as [[x]]. For each share, the share of a party r is expressed as [[x]]yr. Here, r=0, . . . , n−1. Since the secret sharing value is usually distributed to each party, no one owns it and it is virtual. Also, a column of (k, n)-secret sharing values whose plaintext column is {right arrow over ( )} x is expressed as [[{right arrow over ( )} x]].
<(k, k)-Additive Secret Sharing>
(k, k)-secret sharing is (k, n)-secret sharing when n=k. It cannot be restored unless the shares of all parties are collected. (k, k)-secret sharing by replica secret sharing, in particular, is called additive secret sharing and is the simplest way to restore plaintext by simply adding k shares. In the present embodiment, under a modulus y, it is distributed by (k, k)-additive secret sharing, a set (also referred to as (k, k)-additive secret sharing value) that collects all the shares whose plaintext is a certain value x is expressed as <x>y, and the share of the party r is expressed as <x>yr. In addition, a column of (k, k)-additive secret sharing values whose plaintext column is {right arrow over ( )} x is expressed as <{right arrow over ( )} x>P.
First, some protocols used in the secure MSB normalization system according to the first embodiment will be described.
Input: A (k, n)-secret shared numerical share [[a]P, and a share <<ρ>>P obtained by distributing a rotation amount ρ by replica secret sharing
Output: A (k, n)-secret shared share [[2ρa]]P.
Processing: Obtain a share [[2ρa]]P obtained by distributing a value 2ρa obtained by ρ bit rotation of a numerical value a by (k, n)-secret sharing using the numerical share [[a]]P and the share <<ρ>>P. In this example, k=2 and n=3. Details of the processing will be described below.
2: Convert a numerical share [[a]]P to (k, k)-additive secret shared share <a>P. In this example, parties 0 and 1 have a share <a>p. The conversion from (k, n)-secret sharing to (k, k)-additive secret sharing can be performed by known techniques. For example, Reference 1 is used.
b
0:=2<<ρ>>
5: Party 1 calculates a below representation and sends the result to Party 0.
b
1:=2<<ρ>>
7: Party 0 calculates a below representation.
<c<0P:=2<<ρ>>
8: Party 2 calculates a below representation.
<c<2P:=2<<ρ>>
10: A (k, k)-additive secret shared share <c>P is converted into a (k, n)-secret shared share [c]P and output. Here, c=2ρa is established. The conversion from (k, k)-additive secret sharing to (k, n)-secret sharing can be performed by known techniques. For example, Reference 1 is used.
Input: A bit share vector [[{right arrow over ( )}f]]2 of a length p. However, there is only one 1 in {right arrow over ( )}f.
Output: mod p share [[b]]p at position 1 in {right arrow over ( )}f
Processing: Obtain a share [[2ρa]]P obtained by distributing a position b of 1 existing in {right arrow over ( )}f by (k, n)-secret sharing using the bit share vector [[{right arrow over ( )}f]]2. Details of the processing will be described below.
1: A share <<ρ>>P obtained by distributing a uniform random number ρ by (k, n)-replica secret sharing by mod p is generated.
2: A public value ρo{right arrow over ( )}f is calculated by a public value output rotation protocol. Since ρ is a uniform random number and {right arrow over ( )}f is determined to be 1 only at one position, ρo{right arrow over ( )}f is a uniform random number on rotation expressing a numerical value as a bit position, and it is safe even if it is opened to the public. The public value output rotation protocol is a protocol that obtains a ρo{right arrow over ( )}f (public value) obtained by rotating the vector {right arrow over ( )} a by ρ by inputting the vector [[{right arrow over ( )}a]] of the (k, n)-secret shared share and the (k, n)-replica secret shared rotation amount ρ and can be realized by the well-known technology. For example, the space of random permutation in the public value output random permutation protocol of Reference 2 can be limited to random rotation.
Even in a case where the length of the input bit share vector [[{right arrow over ( )}f]]2 is shorter than p, this protocol can be applied by padding [[0]]2 to the high-order bits.
Hereinafter, the vector MSB normalization realized in the present embodiment will be described.
Input: A vector [[{right arrow over ( )}a]]P of a share
Parameter: The maximum number of bits of input L and a vector length m.
The output: [[2ρ{right arrow over ( )}a]]P, <<ρ>>P, where the vector MSB of 2ρ{right arrow over ( )}a is the L−1-th bit.
Processing: The entire vector [[{right arrow over ( )}a]]P is shifted so that the MSB (vector MSB) of the data having the largest absolute value among the elements included in the vector [[{right arrow over ( )}a]]P is aligned with the fixed position (here, L−1-th bit)), and the vector [[2ρ{right arrow over ( )}a]]p after the shift and the shift amount <<ρ>>P are obtained. Details of the processing will be described below.
1: The bit representation [[{right arrow over ( )}a]]2{circumflex over ( )}L of [[{right arrow over ( )}a]]P is obtained by bit decomposition. The bit decomposition can be performed by a known technique. For example, Reference 1 is used.
2: the OR of all elements are taken for each bit position 0≤i<L vector [[{right arrow over ( )}ai]]2 of [[{right arrow over ( )}a]]2{circumflex over ( )}L. When as is the s-th element of {right arrow over ( )}a, s=0, 1, . . . , m−1, the bit representation of [[as]] is [[as]]2{circumflex over ( )}L, and the share of the i-th bit position of [[as]]2{circumflex over ( )}L is [[(ai)s]]2, the vector [[{right arrow over ( )}ai]] is [[{right arrow over ( )}ai]]=([[(ai)0]]2, . . . , [[(ai)m−1]]2), and the logical sum to be obtained is [[Ai]]2:=[[(ai)0]]2OR . . . OR[[(ai)m−1]]2.
3-1: Inductively, 0≤i<L−1, let [[fi]]2:=[[fi+1VAi]]2. Here, [fL−1]2:=[[AL−1]]2 is established. Up to this point, the bit representation f=(fL−1, fL−2, . . . , f0) has a form in which 01s are lined up with the MSB as the boundary, such as 0, 0, 0, 1, 1, . . . , 1.
3-2: Maximum p-L pieces of [[1]]2 are inserted into the low-order bits, and ([[f′0]]2, . . . [[f′L′−1]]2):=([[1]]2, . . . , [[1]]2, . . . , [[1]]2, [f0]2, . . . [[fL−1]]2 is established. L′ is a number obtained by adding the number of [[1]]2 inserted to L. By this processing, the MSB position is defined even when all the elements of {right arrow over ( )}a are 0.
3-3: In 0≤i<L′−1, [[xi]]2:=[[f′ixor f′i+1]]2 is established. Here, [xL′−1] 2:=[[AL−1]]2 is established. Up to this point, the bit representation x=(xL′−1, xL′−2, . . . , x0) is a flag such as 0, 0, 1, 0, . . . , 0 where only the MSB position is 1.
4: By the above-mentioned <Flag Column {right arrow over ( )}Numerical Share Conversion Protocol>, [[XL′−1]]2, [[XL′−2]]2, . . . , and [[X0]]2 are converted into <<ρ>>P. However, note that it is in descending order.
5: By the above-mentioned <Multiplicative Rotation>, the (k, n)-secret shared share [[2ρ{right arrow over ( )}a]]P is obtained from the vector [[{right arrow over ( )}a]]P of the share and the share <<ρ>>P which is obtained by distributing the rotation amount by replica secret sharing and output. However, the multiplicative rotation may be performed by other known techniques.
Hereinafter, the vector MSB normalization system that realizes the above-mentioned vector MSB normalization will be described.
The vector MSB normalization system 1 includes n distributed processing apparatuses 100-r. Here, n is any integer of 3 or more, and r=0, 1, . . . , n−1. The n distributed processing apparatuses 100-r can communicate with each other via a communication line 2.
The vector MSB normalization system 1 inputs a vector [[{right arrow over ( )}a]]p of a share [[as]]P which is obtained by distributing each element as of a vector {right arrow over ( )}a by (k, n)-secret sharing by a modulus p, performs the vector MSB normalization, and obtains and outputs the vector [[2ρ{right arrow over ( )}a]]p and the shift amount <<ρ>>P after the vector MSB normalization. The parameters are the maximum bit length L of the share [[as]]p and the vector length m of the vector [[{right arrow over ( )}a]]P.
The distributed processing apparatus is a special computer configured by loading a special program into a publicly known or dedicated computer having, for example, a central processing unit (CPU), a main storage device (RAM: Random Access Memory), and the like. The distributed processing apparatus executes each processing under the control of the central processing unit, for example. The data input to the distributed processing apparatus and the data obtained by each processing are stored in the main storage device, for example, and the data stored in the main storage device is read out to the central processing unit as needed and is used for processing. At least a part of each processing unit of the distributed processing apparatus may be configured by hardware such as an integrated circuit. Each storage unit included in the distributed processing apparatus can be configured by, for example, a main storage device such as random access memory (RAM) or middleware such as a relational database or a key-value store. However, each storage unit does not necessarily have to be provided inside the distributed processing apparatus, and is configured by an auxiliary storage device composed of semiconductor memory elements such as a hard disk, an optical disc, or a flash memory, and is a distributed processing apparatus. It may be configured to be provided outside the distributed processing apparatus.
[Distributed Processing Apparatus 100-r]
The distributed processing apparatus 100-r includes a bit decomposition unit 101, a logical sum acquisition unit 103, a shift amount acquisition unit 105, and a shift unit 107.
Hereinafter, the processing of each part will be described with reference to
The n bit decomposition units 101 receive a vector [[{right arrow over ( )}a]]P of a (k, n)-secret shared share, and obtain a bit representation [[{right arrow over ( )}a]]2{circumflex over ( )}L of the vector [[{right arrow over ( )}a]]p by the bit distribution (S101).
The n logical sum acquisition units 103 receive the bit representation [[{right arrow over ( )}a]]2{circumflex over ( )}L and obtain a logical sum [[Ai]]2 of all elements for the vector [[{right arrow over ( )}ai]] of each bit position 0≤i<L (S103). Here, assuming that the s-th element of the vector {right arrow over ( )} a be as, s=0, 1, . . . , m−1, a bit representation of [[as]] be [[as]]2{circumflex over ( )}L, and the share of the i-th bit position of [[as]]2{circumflex over ( )}L be [[(ai)s]]2 the vector [[{right arrow over ( )} ai]] is [[{right arrow over ( )}ai]]=([[(ai)0]]2, . . . , [[(ai)m−1]]2) and the logical sum to be obtained is [[Ai]]2:=[[(ai)0]]2OR . . . OR[[(ai)m−1]]2.
The n shift amount acquisition units 105 receive the logical sum [[Ai]]2 and obtain a shift amount <<ρ>>P for shifting the MSB of the vector [[{right arrow over ( )} A]]2=([[A0]]2, . . . , [[AL−1]]2) to the fixed position using the maximum number of bits L≤p−1 as a parameter (s105).
For example, the shift amount <<ρ>>P is obtained as follows.
First, the n shift amount acquisition units 105 assume [[fL−1]]2:=[[AL−1]]2, and in an inductive manner in 0≤i<L−1, assume [[fi]]2:=[[fi+1VAi]]2. By this processing, a bit representation f=(fL−1, fL−2, . . . , f0) has a form in which 01s are lined up with the MSB as the boundary, such as 0, 0, 0, 1, 1, . . . , 1.
Next, the n shift amount acquisition units 105 assume [[xL−1]]2:=[[AL−1]]2, and in 0≤i<L−1, assume [[xi]]2:=[[fixor fi+1]]2. By this processing, the bit representation x=(xL−1, xL−2, . . . , x0) becomes a flag such as 0, 0, 0, 1, 0, . . . , 0 where only the MSB position becomes 1.
Finally, the n shift amount acquisition units 105 convert the columns [[xL−1]]2, [[xL−2]]2, . . . , [[x0]]2, [[1]]2, . . . , [[1]]2 of the length p into <<ρ>>P by the above-mentioned <Flag Column→Numerical Share Conversion Protocol>.
The n shift units 107 receive [[{right arrow over ( )}a]]P and <<ρ>>P, obtain each the vector [[2ρ{right arrow over ( )}a]]P which is obtained by left-shifting each element of [[{right arrow over ( )}a]]P by bits (S107) and output the vector. For example, by the above-mentioned <Multiplicative Rotation>, the (k, n)-secret shared share [[2ρa]]P is obtained from the share vector [[{right arrow over ( )}a]]P and the replica secret shared share <<ρ>>P of the rotation amount.
With such a configuration, MSB matching can be performed while maintaining accuracy.
The part different from the first embodiment will be mainly described.
In the second embodiment, the fixed-point vector product sum using the vector MSB normalization of the first embodiment will be described. First, some protocols used in the fixed-point vector product sum according to the second embodiment will be described.
Input: A numerical share [[a]]P, a share of a positive and negative left shift amount <<ρ>>Q,
Parameters: An upper limit Mmax which can be taken by the MSB position of the input. and the maximum MSB position Mlim which is allowed by the share, and
Output: A ρ bit shifted value [[s]]P.
1. First, when u:=Mlim−Mmax+1, the following representation is used.
u indicates the size of the range of the right shift amount that can be covered by one shift amount secure right shift (covers 0 to (Mlim−Mmax)) and d indicates the number of secure right shift amounts required to make a right shift in the range of 1 to (Mmax−1) bits. When the right shift amount is zero or less, the left shift is sufficient, and when the right shift amount is Mmax or more, the output is always zero.
2: <<ρ>>P is calculated by modulus transformation using quotient transition. The modulus conversion using the quotient transition can be performed by known techniques. For example, Reference 1 is used.
3: By comparison of magnitude, the followings are calculated:
[[f0]]2:=[[{ρ≥−Mmax+1}]]2,
[[f1]]2:=[[{ρ≥−Mmax+1+u}]]2, . . . ,
[[fd−1]]2:=[[{ρ≥−Mmax+1+(d−1)u}]]2, and
[[fL]]2:=[[{ρ≥0}]]2
Note that fL, fd−1, fd−2, . . . are transitive flags.
4. By mod 2→mod p conversion, from [[f1]]2, [[f2]]2, . . . , [[fd−1]]2, [[fL]] to <<f1>>p, <<f>>p, . . . , <<fd−1>>p, <<fL>>p are calculated. Here, <<f0>>p is unnecessary. Note that the mod 2→mod P conversion can be performed by a known technique. For example, Reference 1 is used.
5: <<ρ′>>P:=<<ρ>>P+Mmax−1−uΣ1≤i<d<<fi>>P+((d−1)u−Mmax+1)<<fL>>p is calculated.
6: [[b]]P:=[[2ρ′a]]P is calculated by <Multiplicative Rotation Protocol> using [[a]]P and <<ρ′>>P. However, known techniques may be used as the multiplicative rotation protocol.
7: By a collective shift amount public right shift, the followings are calculated:
[[c0]]P:=[[2ρ′a/2M_(max)−1]]P,
[[c1]]P:=[[2ρ′a/(2M_(max)−1−u)]]P, . . . , and
[[cd−1]]P:=[[2ρ′a/(2M_(max)−1−(d−1)u)]]P.
8: By the mod 2→mod P conversion, [[f0]]P, [[f1]]P, . . . , [[fd−1]]P, and [[fL]]P are calculated. Here, [[f0]]P is required.
9: By sum of products, [[s]]:=[[c0]]P[[f0]]P+([[c1]]−[[c0]])P[[f1]]P+ . . . +([[cd−1]]−[[cd−2]])P[[fd−1]]P+[[b]]P−[[cd−1]]P)[[fL]]P is calculated and output. It is noted that this representation is a selection gate for a transitional flag.
The fixed-point vector product sum realized in the present embodiment will be described below.
Input: Fixed-point number vectors [[{right arrow over ( )}a]]P and [[{right arrow over ( )}b]]P
Parameter: Vector length m
Output: [[c]]P, where Σ0≤I<maibi≈C
1: By the vector MSB normalization protocol of the first embodiment, the fixed-point number vectors [[{right arrow over ( )}a]]P and [[{right arrow over ( )}b]]P are vector MSB normalized, respectively, and the vectors whose MSB position are adjusted and the shift amounts ([[{right arrow over ( )} 2ρ_a{right arrow over ( )} a]]P, <<ρa>>P), ([[2ρ_b{right arrow over ( )}b]]P, <<ρb>>P) are obtained.
2: [[ρa]]Q and [[ρb]]Q are obtained by mod p→mod Q conversion from <<ρa>>P, <<ρb>>P. The mod p→mod Q conversion can be performed by a known technique. For example, Reference 1 is used. Further, a modulus conversion other than Reference 1 may be used. For example, the technique of Reference 1 needs to satisfy that there are a predetermined number of free bits (hereinafter, also referred to as conditions for quotient transition). However, the modulus conversion that does not satisfy the conditions for quotient transition may be used. Hereinafter, a modulus conversion that does not satisfy the conditions for quotient transition will be described.
Input: A (k, n)-secret shared share [[a]]P
Parameter: The number of bits |p| of the p
Output: A (k, n)-secret shared share [[a]]Q by different modulus Q
2-1: The share [a]p is converted into (k, k)-additive secret shared share <a>p. With k=2, parties p0 and p1 have a share <a>p. The conversion from (k, n)-secret sharing to (k, k)-additive secret sharing can be performed by known techniques. For example, Reference 1 is used.
2-2: The party p0 calculates a′0:<a>P0+(2|p|−p) by addition on Z without performing mod p, and the each bit of a′0 is subjected to (k, n)-secret sharing to obtain a share [[a′0]2|p| of bit expression. The bit decomposition can be performed by a known technique. For example, Reference 1 is used.
2-3: The party p1 performs (k, n)-secret sharing of each bit of <a>P1 to obtain a share [[a1]]2{circumflex over ( )}|p| of a bit representation.
2-4: A share [[a′0+a1]]2{circumflex over ( )}(|p|+1)) of the bit representation of a′0+a1 is obtained by an addition circuit. After the addition circuit computation, the bit length increases by 1 from |p| to |p|+1.
2-5: [[q]]2 is made the most significant bit of [[a′0+a1]]2{circumflex over ( )}(|p|+1). q is the quotient of the share <a>p, that is, q when expressed as <a>0+<a>1=a+qp.
2-6: [[q]]Q are obtained from [[q]]2 by mod 2→mod Q conversion. For example, the mod 2→mod Q conversion can be performed by a known technique. For example, Reference 1 is used.
2-7: The parties P0 and P1 obtain <a>P0 mod Q and <a>P1 mod Q from <a>P0 and <a′>Q, respectively, and satisfy <a′>Q. Here, a′=a+QP mod Q is established.
2-8: The (k, k)-secret shared share <a′>Q is converted to (k, n)-secret-sharing to obtain the (k, n)-secret shared share [[a′]]Q. The conversion from (k, k)-additive secret sharing to (k, n)-secret sharing can be performed by known techniques. For example, Reference 1 is used.
2-9: [[a]]Q=[[a′]]Q−p[[q]]Q is calculated and output.
For example, in the case of p=61, since only the value is taken up to 31 in order to leave free bits, in this case, mod p→mod Q conversion, it is assumed that the conditions for using the quotient transition are often not satisfied. Therefore, it is preferable to use the non-quotient transition modulus conversion protocol.
3: [[c]]P=[[Σ0≤i<m2ρ*aai2ρ_bbi]]P is calculated.
4: [[−ρa−ρb]]Q is calculated and <<−ρa−ρb>>Q is obtained by conversion.
5: By the above-mentioned <Shift Amount Secure Left and right Shift Protocol>, a value obtained by shifting [[c]]P by <<−ρa−ρb>>Q and shifting [[c]]P by (−ρa−ρb) bits is output.
A vector MSB normalization system for realizing the above-mentioned <Fixed-Point Vector Product-Sum Protocol> will be described below.
The vector MSB normalization system 1 takes two fixed-point vectors [[{right arrow over ( )}a]]P and, [[{right arrow over ( )}b]]P as inputs, obtains the sum of products [[c]]P of the elements, and outputs the sum of products. Here, Σ0≤i<maibi≈c is established. The vector length m of the vectors [[{right arrow over ( )}a]]P and[[{right arrow over ( )}b]]P is used as a parameter.
<Distributed Processing Apparatus 100-r>
The distributed processing apparatus 100-r includes a modulus conversion unit 109, a product sum computation unit 111, a secret sharing conversion unit 113, and a shift amount secure left and right shift unit 115 in addition to the bit decomposition unit 101, the logical sum acquisition unit 103, the shift amount acquisition unit 105, and the shift unit 107,
Hereinafter, the processing of each part will be described with reference to
S101 to S107 are as described in the first embodiment. The vector MSB normalization system 1 takes fixed-point vectors [[{right arrow over ( )}a]]P and [[{right arrow over ( )}b]]P as an input, performs vector MSB normalization, and obtains the vectors after vector MSB normalization and shift amounts ([[{right arrow over ( )}2ρ_a{right arrow over ( )}a]]P, <<ρa>>P) and ([[2ρ_b{right arrow over ( )}b]]P, <<ρb>>P). The processing after S109 will be described.
The n modulus conversion units 109 receive ([[{right arrow over ( )}2ρ_a{right arrow over ( )}a]]P, <<ρa>>P) and ([[2μ_b{right arrow over ( )}b]]P, <<ρb>>p) and obtain [[ρa]]Q, [[ρb]]Q by mod p→mod Q conversion from <<ρa>>p, <<ρb>>p (S109).
The n product sum computation units 111 receive shares [[{right arrow over ( )}2ρ_a{right arrow over ( )}a]]P and [[2ρ_b{right arrow over ( )}b]]P and calculate sum of products [[c]]P:=[[Σ0≤i<m2ρ_aai2ρ_bbi]]P (S111).
The n secret sharing conversion units 113 receive [[ρa]]Q and [[ρb]]Q, calculate [[−ρa−ρb]]Q, and obtain <<−ρa−ρb>>Q by secret sharing transformation (S113).
The shift amount secure left and right shift unit 115 receives the share [[c]]P of the sum of products and the share <<−ρa−ρb>>Q of the shift amount and by the above-mentioned <Shift Amount Secure Left And Right Shift Protocol>, [[c]]P is shifted by <<−ρa−ρb>>Q bit (S115), and the shifted value is output. It should be noted that, instead of using the above-mentioned <Shift Amount Secure Left And Right Shift Protocol>, a value obtained by shifting [[c]]P by <<−ρa−ρb>>Q bit may be obtained by a known technique using the share of the sum of products [[c]]P and the share <<−ρa−ρb>>Q of the shift amount.
A description will be given mainly of differences from the first embodiment.
In the third embodiment, the floating point vector product sum utilizing the vector MSB normalization of the first embodiment will be described. First, several protocols used in the floating point vector product sum according to the third embodiment will be described.
Input: Floating point vector ([[{right arrow over ( )}a]]P, [[{right arrow over ( )}ρa]]Q). However, in this embodiment, the mantissa part is a, the exponent part is ρa, and the real number x is x=2ρ_aa. [[{right arrow over ( )}a]]P=([[a0]]P, . . . , [[{right arrow over ( )}am−1]]P), and [[{right arrow over ( )}ρa]]Q=([[ρa_0]]Q, . . . , [[ρa_m−1]]Q) are established and the floating point vector ([[{right arrow over ( )}a]]P, [[{right arrow over ( )}ρa]]Q) expresses the i(0≤i≤m−1)-th real number as 2ρ_(a_i)ai.
Output: ([[{right arrow over ( )}b]]P, [[ρmax]]Q). However, for each i-th element 2ρ_(a_i)ai≈2ρ_maxbi
Processing: The exponent part [[{right arrow over ( )}ρa]]Q of the floating point vector ([[{right arrow over ( )}a]]P, [[{right arrow over ( )}ρa]]Q) is unified to the largest value [[ρmax]]Q, and the mantissa part [[{right arrow over ( )}a]]]P is shift right by the difference [[{right arrow over ( )}ρdif]]Q: =[[{right arrow over ( )}ρa]]Q−[[ρmax]]Q to find a floating point vector with a unified exponent part.
1: The largest value among all elements included in [[{right arrow over ( )}ρa]]Q is obtained as [[ρmax]]Q by maximum value computation.
2: [[{right arrow over ( )}ρdif]]Q:=[[{right arrow over ( )}ρa]]Q−[[ρmax]]Q is calculated. [[ρmax]]Q is subtracted from each element of [[{right arrow over ( )}ρa]]Q.
3: By <Shift Amount Secure Left And Right Shift Protocol>, each element of [[{right arrow over ( )}a]]P is shifted by each element of [[−{right arrow over ( )}ρdif]]Q to make [[{right arrow over ( )}b]]P. However, since the each element of −{right arrow over ( )}dif is non-negative, the right shift is achieved, and therefore the branch of the left shift may be omitted.
4: Output ([[{right arrow over ( )}b]]P, [[ρmax]]Q)
The floating point vector product sum realized in this embodiment will be described below.
Input: Floating point vectors ([[{right arrow over ( )}a]]P, [[{right arrow over ( )}ρa]]Q) and ([[{right arrow over ( )}b]]P, [[{right arrow over ( )}ρb]]Q)
Parameter: Vector length m.
Output: ([[c]]P, <<ρb>>Q), where, the representation Σ0≤i<m2(ρ_a)_i)ρ_b)_iaibi≈2ρ_bb is established.
1: By above-mentioned <Vector MSB Normalization Protocol>, vectors and shift amounts ([[{right arrow over ( )}a′]], <<p′a>>P) and ([[{right arrow over ( )}b′]], <<ρ′b>>P) which are obtained by adjusting the MSB position of [[{right arrow over ( )}a]]P and[[{right arrow over ( )}b]]P are obtained.
2: [[ρa′]]Q and [[ρb′]]Q are obtained by mod p→mod Q conversion.
3: By the above-mentioned <Floating Point Vector Exponent Part Unifying Protocol>, a vector in which exponent parts of ([[{right arrow over ( )}a′]]P, [[{right arrow over ( )}ρa−ρa′]]Q) and ([[{right arrow over ( )}b′]]P, [[{right arrow over ( )}ρb−ρb′]]Q) are unified and exponent parts ([[{right arrow over ( )}a″]], [[ρa″]]Q), ([[{right arrow over ( )}b″]], [[ρb″]]Q are obtained.
4: [[c]]P:=[[Σ0≤i<ma″ib″i]]P is calculated to obtain ([[c]]P, [[ρa″+ρb″]]Q).
Further, when the number of input bits is known to some extent, or when it is known that the number of bits of a and b is relatively high for the reason that the MSB is adjusted, the right shift is performed by a predetermined number of bits σ by a known shift amount disclosure right shift.
On the other hand, if the number of bits is unknown, the MSB is aligned to the fixed position by the same method as in the first embodiment, and then the MSB is shifted to the appropriate bit position by a known shift amount disclosure right shift. The right shift amount is defined as [[σ]]Q.
Hereinafter, the vector MSB normalization system that realizes the above-mentioned <Floating Point Vector Product Sum Protocol> will be described.
The vector MSB normalization system 1 inputs two floating point vectors ([[{right arrow over ( )}a]]P, [[{right arrow over ( )}ρa]]Q) and ([[{right arrow over ( )}b]]P, [[{right arrow over ( )}ρb]]Q), obtains the product sum ([[c]]P, <<ρc>>Q) of the elements, and outputs the product sum. Where the representation is established: Σ0≤i<m2(ρ_a)_i)ρ_b)_iaibi≈2ρ_cc. The vector length m of the vectors [[{right arrow over ( )}a]]P and [[{right arrow over ( )}b]]P is used as a parameter.
[Distributed Processing Apparatus 100-r]
The distributed processing apparatus 100-r includes a modulus conversion unit 117, an index unifying unit 119, and a product sum unit 121 in addition to the bit decomposition unit 101, the logical sum acquisition unit 103, the shift amount acquisition unit 105, and the shift unit 107.
Hereinafter, the processing of each part will be described with reference to
S101 to S107 are as described in the first embodiment. The vector MSB normalization system 1 inputs two floating point vectors ([[{right arrow over ( )}a]]P, [[{right arrow over ( )}ρa]]Q) and ([[{right arrow over ( )}b]]P, [[{right arrow over ( )} ρb]]Q) normalizes ([[{right arrow over ( )}a]]P and [[{right arrow over ( )}b]]P to vector MSB, and obtains the vectors and the shift amounts ([[{right arrow over ( )}a′]]P, <<ρ′a>>P) and ([[{right arrow over ( )}b′]]P, <<p′b>>P) after the vector MSB normalization. The processing after S117 will be described.
The n modulus conversion units 117 receive <<ρ′a>>p and <<ρ′b>>p and obtain <<ρ′b>>p by mod p→mod Q conversion (S117.)
The n index unifying units 119 receive exponential parts [[{right arrow over ( )} ρa]]Q and [[{right arrow over ( )} ρb]]Q of two floating point vectors ([[{right arrow over ( )} a]]P, [[{right arrow over ( )} ρa]]Q) and ([[{right arrow over ( )}b]]p), the vectors [[{right arrow over ( )}a′]]P and [[{right arrow over ( )}b′]]P after the vector MSB normalization, and the shift amounts [[ρa′]]Q and [[ρb′]]Q after mod p→mod Q conversion, and obtain vectors and exponent parts obtained by unifying exponent parts of ([[{right arrow over ( )}a′]]P, [[{right arrow over ( )}ρa−ρa′]]Q) and ([[{right arrow over ( )}b′]]P, [[{right arrow over ( )}ρb−ρb′]]Q) using the above-mentioned <Floating Point Vector Exponent Part Unifying Protocol> (S119).
The n product sum units 121 calculate [[c]]P:=[[Σ0≤i<ma″ib″i]]P and obtain ([[c]]P, [[ρa′+ρb′]]Q) (S121).
Regarding the processing efficiency of the algorithm, a multiplication rotation, such as elemental operations, a flag column→numerical conversion, a shift amount secure Left and right shift protocol and a floating point addition and multiplication for comparison are evaluated.
For comparison, Reference 2 has two methods for addition, and if the cost of communication volume less than the logarithm is rounded, 22|P|+5|Q|+O(log|P|+log|Q|) can be expressed.
The results of the actual machine experiment are reported. The multi-party computation of the following three machines is performed.
⊚ CPU: Xeon Gold 6144 3.5 GHz, 6 cores×2 sockets
⊚ NW: 10 Gbps ring topology
The upper limit of the MSB position is important as a parameter, and it is set to 28 bits (the number of 29 bits for the purpose of 0 start notation). The condition is that the maximum MSB position where the quotient transition can be used with mod P with a sign is 57 and is within half of the maximum MSB position. 28 bits exceed single accuracy and are considered sufficient for many applications.
In fact, matrix multiplication is selected as the product sum operation. This is because the matrix multiplication is composed of a product sum and is extremely important for machine learning or the like. Specifically, the left matrix is set to 100 rows, the number of rows x the number of columns=the “number of cases,” and the right matrix is a vector whose length is the number of columns on the left. The processing amount is equal to a processing amount in which a product sum having a size as the number of columns is repeated by the number of rows.
There are three scales, 1000, 1 million, and 10 million, and the actual number of rounds is measured by maximizing the delay to 100 ms. In addition to the passive model, the performance of the active model is also shown (the protocol is an extension of the passive version). The security parameter of the active model is 8 bits, and the attack detection rate is about 99%. This probability is sufficient to deter an attack, as offline attacks are not possible, unlike computational security.
The present invention is not limited to the foregoing embodiments and modified examples. For example, the above-described various kinds of processing may be performed chronologically, as described above, and may also be performed in parallel or individually in accordance with a processing capability of a device performing the processing or as necessary. In addition, changes can be made appropriately within the scope of the present invention without departing from the gist of the present invention.
The aforementioned various types of processing can be carried out by causing a storage unit 2020 of the computer shown in
The program describing the processing contents can be recorded on a computer-readable recording medium. As the computer-readable recording medium, for example, any of a magnetic recording device, an optical disc, a magneto-optical recording medium, and a semiconductor memory may be used.
In addition, the distribution of this program is carried out by, for example, selling, transferring, or lending a portable recording medium such as a DVD or a CD-ROM on which the program is recorded. Further, the program may be distributed by storing the program in a storage device of a server computer and transmitting the program from the server computer to other computers via a network.
A computer that executes such a program first temporarily stores, for example, a program recorded on a portable recording medium or a program transferred from a server computer in its own storage device. Then, when the processing is executed, the computer reads the program stored in its own recording medium and executes the processing according to the read program. Further, as another execution form of this program, a computer may read the program directly from a portable recording medium and execute processing according to the program. Further, each time the program is transferred from the server computer to this computer, the processing according to the received program may be executed sequentially. Also, the program may not be transferred from the server computer to this computer. The above-mentioned processing may be executed by a so-called application service provider (ASP) type service that realizes the processing function only by the execution instruction and the result acquisition. The program in the present embodiment includes information to be used for processing by a computer and equivalent to the program (data that is not a direct command to the computer but has a property that regulates the processing of the computer, or the like).
In this aspect, the device is configured by executing a predetermined program on a computer, but at least a part of the processing content may be implemented by hardware.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2020/039078 | 10/16/2020 | WO |
