BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing a system outline of an embodiment of the present invention;
FIG. 2 is a functional block diagram of a secure node;
FIG. 3 is a diagram showing an example of a security policy used at the time of a normal state;
FIG. 4 is a diagram showing a first portion of a processing flow in the embodiment of the present invention;
FIG. 5 is a diagram showing a processing flow of a security determining processing;
FIG. 6 is a diagram showing a processing flow of a confirmation processing;
FIG. 7 is a diagram showing a processing flow of a first routing processing;
FIG. 8 is a diagram showing an outline of the secure routing;
FIG. 9 is a diagram showing a processing flow of a second routing processing;
FIG. 10 is a diagram showing a network outline to explain the second routing processing;
FIG. 11 is a diagram showing a second portion of the processing flow in the embodiment of the present invention;
FIG. 12 is a diagram showing a processing flow of an admission control processing;
FIG. 13 is a diagram showing a third portion of the processing flow in the embodiment of the present invention;
FIG. 14 is a diagram to explain a first example of a header setting processing at the time of the normal state;
FIG. 15 is a diagram to explain a first example of a header setting processing at the time of an abnormal state;
FIG. 16 is a diagram showing an example of the security policy at the time of the abnormal state;
FIG. 17 is a diagram showing a second example of the header setting processing at the time of the normal state;
FIG. 18 is a diagram showing a second example of the header setting processing at the time of the abnormal state;
FIG. 19A is a schematic diagram when the secure node has a single function;
FIG. 19B is a schematic diagram when the secure node has plural functions;
FIGS. 20A and 20B are diagrams to explain consideration on an arrangement of the secure nodes;
FIG. 21 is a diagram to explain consideration on the arrangement of the secure nodes; and
FIG. 22 is a functional block diagram of a computer.