Patent Application
20230359438
The present invention relates to a secure computation technique, and more particularly, to a technique for performing a plurality of exponent part uniforming operations of floating points in secure computation.
The secure computation is a method for obtaining a result of a designated operation without restoring an encrypted numerical value, (for example, refer to a reference non-patent document 1). In the method of the reference non-patent document 1, encryption is performed in which a plurality of pieces of information capable of restoring a numerical value are shared to three secure computation apparatuses, and addition/subtraction, constant sum, multiplication, constant multiplication, boolean operation (negation, logical product, logical sum, exclusive or), data form conversion (integer, binary number) can be held in a state of being shared in the three secure computation apparatuses, that is, in an encrypted state. In general, the number of sharing is not limited to 3, and can be set to W (W can be a predetermined constant of 3 or more), and a protocol for realizing secure computation by cooperative calculation by W secure computation apparatuses is called a multi-party protocol.
(Reference non-patent document 1: Koji Chida, Koki Hamada, Dai Igarashi, and Katsumi Takahashi, “Reconsideration of Lightweight Verifiable Three-Party Secure Function Evaluation”, In CSS, 2010.)
Conventionally, there are NPL 1 and NPL 2 as references related to protocols and implementation of secure computation for performing floating point calculation. In order to calculate the sum of the floating points, it is necessary to uniform the exponent parts of the floating points to be added.
[NPL 1] Takuma Amada, Masahiro Nara, Takashi Nishide, Hiroshi Yoshiura, “Multiparty Computation for Floating Point Arithmetic with Less Communication over Small Fields,” IPSJ Journal, vol. 60, No. 9, pp. 1433-1447, 2019.
[NPL 2] Randmets, J., “Programming Language for Secure Multi-party Computation Application Development,” PhD thesis. University of Tartu, 2017.
However, there is a problem that the method of uniforming the exponent parts of the floating points while keeping the secrecy is poor in efficiency.
Hence, an object of the present invention is to provide a secure computation technique for effectively uniforming the exponent parts of the floating points.
One aspect of the present invention is a secret exponent uniforming system where P is a prime number and Q is an order of a residue ring, the secret exponent part uniforming system which is comprised of three or more pieces of secret exponent part uniforming apparatuses and calculates, from a share ( [ [→a] ]P, [ [→ρ] ]Q) of a floating point vector (-a, →ρ) (provided that →a= (a0, a1, ..., am-1), →ρ= (ρ0, ρ1, ..., ρm-1) ), a share ( [ [→b] ] P, [ [→ρmax] ]Q) of a floating point vector (→b, →ρmax) obtained by uniforming exponent parts of the floating point vector (→a, →ρ) (provided that →b= (b0, b1, ..., bm-1), →ρmax= (ρmax, ρmax, ..., ρmax) (provided that ρmax=max {ρ0, ρ1, ..., ρm-1}, | →ρmax | =m), 2ρ-iai≒3p_maxbi(0≦i<m) is satisfied), the secret exponent part uniforming system comprising:
According to the present invention, the exponent part of the floating point can be efficiently uniformed while keeping confidentiality.
Hereinafter, embodiments of the present invention will be described in detail. Further, constituent units having the same function are denoted with the same number, and overlapping descriptions thereof are omitted.
Prior to the description of each embodiment, the notation in the present specification will be explained.
^(caret) indicates a superscript. For example, xy^z means that yz is a superscript to x, and xy^z means that yz is a subscript to x. Further, _ (under score) indicates a subscript. For example, xy_z indicates that yz is a superscript to x, and xy_z indicates that yz is a subscript to x.
Superscripts of a letter x, such as “^” and “~” in ^x and ~x, are to be written directly above “x”, but these are written as ^x and ~x due to constraints of notation in the specification.
The secure computation in each embodiment of the present invention is constructed using an existing secure computation protocol. Hereinafter, a notation will be described.
P is a prime number. For example, it is preferable to set the Mersenne prime number P = 261-1. p is a number of bits of the prime number P. It should be noted that p-|P| may be expressed. When P is a Mersenne prime number, p is a prime number. For example, if P-261-1, p=61 is obtained. Also, Q is an order of a residue ring. The order Q is used as the prime number P and its bit number p. The order Q can be used for a exponent part of a floating point. When the order Q is used for an exponent part of a floating point, Q = 213-1, for example.
It is assumed that k is a threshold of a secret sharing. For example, it is preferable to set k=2. And n is s sharing number of secret sharing (that is, a number of parties of secure computation). For example, it is preferable to set n=3.
[ [X] ]y represents a share in which a mod y element x is (k, n)-secret shared. As a method of secret sharing, for example, Shamir secret sharing or replicated secret sharing can be used. In the following, The share of (k, n)- replicated secret sharing for the mod y element x is expressed by <<x>>y. Since (k, n)-replicated secret sharing is (k, n)-secret sharing, a protocol applicable to (k, n)-secret sharing can be applied to (k, n)- replicated secret sharing. When a share is expressed as <<x>>y, it means that the property of the replicated secret sharing is utilized. In particular, (k, k)-replicated secret sharing is called (k, k)-additive secret sharing. The mod y element x is expressed as a share <x>y in which (k, k)-additive secret sharing is performed.
[ [x] ]2^m represents a share in which m shares in the form of [ [x] ]2 are arranged. In some cases, [ [x] ]2^m is regarded as a bit representation of a number.
x≒y indicates that x and y are equal as real numbers on the computer. That is, the difference between x and y is within a certain error range.
For two numbers a, d, a/d represents the value of integer division for truncating the decimal part. Therefore, the integer division by the number of powers of 2 is equivalent to the right shift, and (a/d)Re represents the value of real number division for the two numbers a, d.
For the number a, ceiling(a) represents the minimum integer of a or more.
(prop) represents 1 when proposition prop is established, and 0 when proposition prop is not established. For example, (1>0) is 1.
A floating point 2ba, (provided that a and b represent a mantissa part and an exponent part respectively), are represented as a floating point (a, b). Further, m floating points 2b_0a0, 2b_1a1, ..., 2b_m-1am-1 (provided that ai, bi (0≦i<m) represent a mantissa part and an exponent part respectively), are represented as a floating point vector (→a, →b) (provided that →a= (a0, a1, ..., am-1), →b- (bo, b1, ..., bm-1)). In some cases, the length m of the vector →a= (a0, a1, ..., am-1) may be expressed as |→a|.
First, existing secure computation protocols used in the present invention will be described. For addition and subtraction, constant sum, multiplication, constant multiplication, a boolean operation (negation, logical product, logical sum, exclusive or), data form conversion (integer, binary number), calculation of the exponential function, existing secure computation protocols are used. The following protocols are used as existing protocols used in the present invention.
Input: a share [ [x] ]y of value x (a share <<x>>y of value x).
Output: a share <x>y of value x.
Specifically, there is a method described in reference non-patent document 2.
(Reference non-patent document 2: Kikuchi, R., Ikarashi, D., Matsuda, T., Hamada, K. and Chida, K., “Efficient Bit-Decomposition and Modulus-Conversion Protocols with an Honest Majority,” 23rd Australasian Conference on Information Security and Privacy (ACISP 2018), Lecture Notes in Computer Science, Vol. 10946, Springer, pp. 64-82, 2018.)
Input: a share <x>y of value x.
Output: a share [ [x] ]y of value x (a share <<x>>y of value x).
Specifically, there is a method described in reference non-patent document 2.
Input: a share [ [x] ]2 of value x (a share <<x>>2 of value x).
Output: a share [ [x] ]q of value x (a share <<x>>q of value x).
Specifically, there is a method described in reference non-patent document 2.
Input: a share [ [x] ]q of value x, a shift amount p
Output: a share [ [x/2ρ] ]q of a value obtained by shifting value x to the right by p bits
Specifically, there is a method described in reference non-patent document 3.
(Reference non-patent document 3: Ibuki Mishina, Dai Igarashi, Koki Hamada, Ryo Kikuchi, “Designs and Implementations of Efficient and Accurate Secret Logistic Regression,” CSS2018, 2018.
Input: a share [ [x] ]q of value x, shift amounts ρ0, ..., ρm-1
Output: shares [ [x/2ρ_0] ]q, ..., [ [x/2ρ_m-1] ]q of values which are obtained by right-shifting of value x by ρ0 bit, ..., ρm-1 bit.
Specifically, there is a method described in reference non-patent document 4.
(Reference non-patent document 4: Dai Igarashi, “Elementary functions more than M op/s in the secure computation,” SCIS2020, 2020.)
As a self-evident method, bulk shift amount public right shift can be formed by repeating shift amount public right shift.
Input: a share <<x>>q of value x.
Output: a share <<x>>r of value x.
Specifically, there is a method described in reference non-patent document 2.
Input: a share [ [x] ]q of value x.
Parameter: a maximum number M of bits of input values.
Output: a share [ [x] ]2^M of value x.
Specifically, there is a method described in reference non-patent document 2.
Next, the secure computation protocols of the present invention will be described.
Input: a share [ [a] ]p of value a, a share <<ρ>>p of a rotation amount (shift amount) ρ(≧0).
Output: a share [ [2ρa] ]P of a value obtained by left-shifting value a by p bits.
Although the share to be output can be calculated by using a protocol of multiplication or exponential function calculation, the share can be calculated by using a method using the idea of the random conversion (refer to reference non-patent document 5). As a specific example, a case where n=3 will be described.
(Reference non-patent document 5: Dai Igarashi, Koki Hamada, Ryo Kikuchi, Koji Chida, “The improvement of the secure computation basic sort directed to statistical processing of 1 second of response to the Internet environment,” SCIS2014, 2014.
step1: A share [ [a] ]P is converted into (k, k)-additive secret share <a>P which party 0 and party 1 have.
step2: The party 0 and the party 1 share a random number r01. The parties 1 and 2 share a random number r12.
step3: The party 0 calculates b0-2(<<ρ>>^p)_01<a>P0-r01 and sends by to the party 2.
Here, <<ρ>>p01 represents a share held by the party 0 and the party 1 with respect to the share <<ρ>>p In addition, <a>p0 represents a share held by the party 0 with respect to the share <a>P.
step4: The party 1 calculates b1=2(<<ρ>>^p)_12(2(<<p>>^p)_01<a>p1+r01)-r12, and sends b1 to the party 0.
Here, <<ρ>>p12 represents a share held by the party 1 and the party 2 with respect to the share <<ρ>>p. In addition, <a>P1 represents a share held by the party 1 with respect to the share <a>P.
step5: The party 0 calculates <c>P0=2(<<ρ>>^p)_20b1.
Here, <<ρ>>p20 represents a share held by the party 2 and the party 0 with respect to the share <<ρ>>p.
Step6: The party 2 calculates <c>P2=2(<<ρ>>^p)_20 (2(<<ρ>>^p)_12b0+r12).
Step7: A share <c>P is converted into (k, k)-secret share [ [c] ]P.
Here, c=2ρa is established.
Input: a share [ [a] ]p of value a, a share <<ρ>>p of a shift amount p.
Parameter: an upper limit value M of shift amount.
Provided that, 0≦ρ≦M, a value 2Ma obtained by left-shifting value a by M bits does not overflow.
Output: a share [ [a/2ρ] ]P of a value obtained by right-shifting value a by p bits.
Step1: calculate <<M-ρ>>p,
Step2: By using multiplicative rotation, calculate a share [ [2m-ρa] ]P of a value obtained by left-shifting value a by M-p bits.
Step3: By using shift amount public right shift, a share [ [a/2ρ] ]P=[ [2M-ρa/2M] ]P of a value obtained by right-shifting a value 2M-ρa to by M bits is calculated.
Input: a share [ [a] ]p of value a, a share <<ρ>>Q of a shift amount p (provided that when ρ≧0 left-shifting is represented, when ρ<0 right-shifting is represented). Parameter: an upper limit value M which can be taken by the position of the MSB (Most Significant Bit) of input values. Output: a share [ [s] ]P of value s obtained by shifting value a by p bits.
Here, s=2ρa is established.
Step1: A share <<ρ>>p is calculated by using modulus conversion. For example, a modulus conversion using the above-mentioned quotient transfer can be used for the modulus conversion.
Step2: [ [fL] ]2= [ [(ρ≧0)] ]2 is calculated by size comparison.
Step3: By using mod 2 → mod p conversion, <<fL>>p is calculated.
Step4: <<ρ′>>p=<<ρ>>p+M-M<<fL>>p is calculated.
Step5: [ [b] ]P=[ [2ρ′a] ]P is calculated by using multiplicative rotation.
Step6: [ [c] ]P=[ [2ρ′a/2M] ]P is calculated by using shift amount public right shift.
Step7: [ [fL] ]P is calculated by using mod 2 → mod P conversion.
Step8: [ [s] ]P-[ [c] ]P+([ [b] ]P-[ [c] ]P) [ [fL] ]P is calculated.
This expression is a selection gate, so that s=c when ρ<0, and s=b when ρ≧0.
Input: a share [ [a] ]p of value a, a share <<ρ>>Q of a shift amount p (provided that when ρ≧0 left-shifting is represented, when ρ<0 right-shifting is represented).
Parameter: an upper limit value M which can be taken by the MSB position of input values, an upper limit value M′ of the MSB position allowed by shares.
Output: a share [ [s] ]P of value s obtained by shifting value a by p bits.
Here, s=2ρa is established.
Step1: u=M′-M+1, d=ceiling(((M-1)/u)Re) are calculated.
Here, u is the right shift amount which can be covered by one shift amount concealment right shift (specifically, the amount in the range of M′-M bits from 1), and d is the number of execution times of the shift amount concealment right shift necessary for performing the right-shifting in the range of 1 to M-1 bits.
Step2: A share <<ρ>>p is calculated by using modulus conversion. For example, a modulus conversion using the above-mentioned quotient transfer can be used for the modulus conversion.
Step3: By size comparison, [ [f0] ]2=[ [(ρ≧-M+1)] ]2, [ [f1] ]2=[ [ (ρ≧-M+1+u) ] ]2, ..., [ [fd-1] ]2=[ [ (ρ≧-M+1+(d-1)u) ] ]2, [[fL]2- [ [ (ρ≧0)] ] are calculated.
In this case, if is fL; fd-1, if is fd-1; fd-2, ... are established. The above-mentioned characteristics of f0, f1, ..., fd-1, fL are referred to as transitive flags.
step4: BY using mod 2 → mod p conversion, <<f1>>p, <<f2>>p, ..., <<fd-1>>p, <<fL>>p are calculated.
In this step, the calculation of <<f0>>p is not required.
step5: <<ρ′>>p=<<ρ>>p+M-1-u (Σ1≦i<d<<fi>>p) + ( (d-1) u-M+1) <<fL>>p is calculated.
Step6: By using multiplicative rotation, [ [b] ]P= [ [2ρ′a] ]P is calculated.
step7: By using bulk shift amount public right shift, [ [c0] ]P=[[2ρ′a/2M-1] ]P [[c1] ]P=[ [2ρ′a/(2M-1-u)] ]P ..., [[cd- 1] ]P=[ [2ρ′a/ (2M-1(-d-1)-u)] ]P are calculated.
step 8: By using mod 2 → mod P conversion, [ [f0] ]P [ [f1] ]P, ..., [ [fd-1]P, [ [fL] ]P are calculated.
In this step, the calculation of [ [f0] ]P is necessary.
step9: [ [s] ]P=[ [c0] ] p [ [f0] ]P+ ( [ [c1] ]P-[ [c0] ]P) [ [f1] ]P+...+ ( [ [cd-1] ]P-[ [cd-2] ]P) [ [fd-1] ]P+ ([ [b] ]P-[ [cd-1] ]P) [ [fL] ]P is calculated.
This expression is a selection gate for transitive flags f0, f1, ..., fd-1, fL, and s= 0 when f0, f1, ..., fd-1, fL are all 0, s=c0 when f0, s=c1 when f1, ..., s=b when fL.
Input: a share [ [a] ]P of value a, a share <<ρ>>Q of a shift amount ρ (provided that when ρ≧0 left-shifting is represented, when ρ<0 right-shifting is represented).
Parameter: an upper limit value M which can be taken by the MSB position of input values, an upper limit value M′ of the MSB position allowed by shares.
Output: a share [ [s] ]P of value s obtained by shifting value a by p bits.
Here, s=2ρa is established.
Step1: It is assumed that u is an integer satisfying u≦M′-M+1. Further, [R, R′] is the range of the right shift amount covered by the divided right shift, and d is an integer satisfying d≧ceiling(((R′-R+1)/u)Re).
Hereinafter, { }L indicates that when the shift amount larger than -R need not be taken into consideration (for example, when it is known that the shift is right shift), the calculation of the portion surrounded by the parentheses can be omitted. In addition, { }0 indicates that, when the shift amount smaller than -R′ is not required to be considered (for example, when it is found that the right shift amount is larger than the value to which the shift amount concealment shift (part 1) can be applied but is not an extremely large value), the calculation of the part surrounded by the parentheses can be omitted.
Step2: A share <<ρ>>p is calculated by using modulus conversion. For example, a modulus conversion using the above-mentioned quotient transfer can be used for the modulus conversion.
Step3: By size comparison, { [ [f0] ]2=[ [ (ρ≧-R′) ] ]2, }0 [ [f1] ]2=[ [ (ρ≧-R′+u) ] ]2, ..., [ [fd-1] ]2=[ [ (ρ≧-R′+(d-1)u)] ]2{, [ [fL] ]2=[ [ (ρ≧-R+1) ] ]2}L are calculated.
In this case, if is fL; fd-1, if is fd-1; fd-2, ... are established. The above-mentioned characteristics of f0, f1, ..., fd-1, fL are referred to as transitive flags.
step4: By using mod 2 → mod p conversion, <<f1>>p, <<f2>>p, ..., <<fd-1>>p{, <<fL>>p)L are calculated.
step5: <<p′ >>p=<<ρ>>p+R′-u (∑1≦1<d<<fi>>p) {+ ( (d-1) u-R′ ) <<fL>>p}L is calculated.
step6: By using multiplicative rotation, [ [b] ]P=[ [2ρ′a] ]P is calculated.
step7: By using bulk shift amount public right shift, { [ [c0] ]P=[ [2ρ′a/2R′ ] ]P, }0 [ [c1] ] P= [ [2ρ′ a/ (2R′-u) ] ]P, ..., [ [cd-1] ]P=[ [2ρ′a/(2R′- (d-1)u) ] ]P are calculated.
step8: By using mod 2 - mod P conversion, { [ [f0] ] P, }0 [ [f1] ]P, ..., [ [fd-1] ]P {, [ [fL] ]P}L are calculated.
step9: [[s] ]P={ [ [ c0] ]P[ [f0] ]P+( } 0 [ [c1] ]P {-[ [c0] ]P) } 0 [ [ f1] ]P+...+ ( [ [ cd-1] ]P-[ cd-2] ]P) [ [ fd-1] ]P{+ ( [ [b] ]P-[ [cd-1] ]P) [ [fL ]P}L is calculated.
This expression is a selection gate for transitive flags f0, f1, ..., fd-1, fL, and s= 0 when f0, f1, ..., fd-1, fL are all 0, s=c0 when f0, s=c1 when f1, ..., s=b when fL.
When R= 1, R′= M-1, u= M′-M+1, d=ceiling(((R′-R+1)/u)Re), the shift amount concealment shift (part 3) becomes the shift amount concealment shift (part 2). Therefore, the shift amount concealment shift (part 3) is a protocol generalized the shift amount concealment shift (part 2).
Input: a share [[→a]]Q of vector →a, (provided that →a= (a0, a1, ..., am-1), a1(0≦i<m) are bit representation integers. Parameter: a maximum number M of bits of input values. Output: a share [ [amax] ]Q of the maximum value amax (provided that amax=max{a0, a1, ..., am-1}).
Step1: A share [ [amax,M-1] ] Q of amax,M-1 which is an OR of the most left bit ai,m-1(0≦i<m) of ai (0≦i<m) (provided that amax,M-1=a0,M-1 OR a1,M-1 OR... OR am-1,M-1) is calculated.
step2: [ [ei,M-1] ]Q=[ [ai,M-1 XOR amax,M-1] ]Q is calculated for 0≦i<m.
step3: for j=M-2 to 0 do
Step3-1: For 0≦i<m, [ [bi,j] ]Q=[ [ai,jΛei,j+1] ]Q is calculated.
Step3-2: A share [ [amax,j] ]Q of amax,j which is OR of bi,j (0≦i<m) (provided that amax,j=b0,j OR b1,j OR... OR bm-1,j) is calculated.
Step3-3: For 0≦i<m, [ [e′i,j] ] Q= [ [ei,j+1Λ ¬amax,j] ]Q is calculated.
step3-4: For 0≦i<m, [ [ei,j ] ] Q= [ [bi,j XOR e′ i,j ] ] Q is calculated.
Step4: amax=amax,M-1amax,M...amax,0 (amax,M-1amax,m...amax,0 is a bit representation to assume amax,j as the j-th digit from right side) is generated.
In the case of executing this protocol after executing the bit decomposition described above, Q = 2 may be used.
Input: a share ([ [→a] ]P, [ [→ρ] ]Q) of a floating point vector (→a, →ρ) (provided that →a= (a0, a1, ..., am-1), →ρ= (ρ0, ρ1, ..., ρm-1) ) Output: a share ([ →b] ]p, [ [→ρmax] ] Q) of a floating point vector →b, →ρmax) obtained by uniforming exponent parts of the floating point vector (→a, →ρ) (provided that →b=(b0, b1, ..., bm- 1), →ρmax= (ρmax, ρmax, ..., ρmax) (provided that ρmax=max{ρ0, ρ1, ..., ρm-1}, | →ρmax | =m) ) Here,
is satisfied.
Step1: By using maximum value calculation, [[ρmax]]Q is obtained from [[→ρ]]Q.
Step2: [[→pdif]] Q= [[→p]]Q- [[→pmax]]Q is calculated.
step3: A share [[-b]]P=([[b0]]P, [[bm-1]]P, ..., [[bm-1]]P) is calculated, with shift amount concealment shift (part 2) or shift amount concealment shift (part 3), by calculating a share [[bi]]P (provided that bi-2-p_dif,iai) of the number bi which is obtained by -pdif,i bit shift of the number ai, from the i-th element [[ai]]P of the share [[→a]]P and the i-th element <<pdif,i>>Q of a share <<→pdif>>Q converted by replicated secret sharing from the share [[→pdif]] Q.
step4: A share ([[→b]]P, [[→pmax]]Q) is generated.
Input: a share ([[→a]]P, [[→p]]Q) of a floating point vector (→a, →p) (provided that →a= (a0, a1, ..., am-1), →p= (P0, p1, ..., pm- 1)) .
Parameter: vector length m.
Output: a share ([ [b] ]P, [[σ]]Q) of a floating point (b, σ) which is a sum of floating points which are elements of the floating point vector (→a, →p).
Here, Σ0≦i<m2p_iai≒2σb is satisfied.
step1: By using uniforming exponent part of floating point vector, a share ([[→a′]]P, [[→pmax]]Q) obtained by uniforming exponent parts of elements of the share ([[→a]]P, [[→p]]Q) (provided that →a′=(a′0, a′1, ..., 8′m_1), →ρmax=(pmax, pmax, ..., pmax) (provided that pmax=max{p0, p1, ..., pm-1}, |→pmax|=m), 2p_iai≒2p_max a′i(0≦i<m) is satisfied) is calculated.
Step2: A share ([[b]]P, [[σ]]Q) (provided that b=Σ0≦i<ma′i, σ=ρmax) is calculated.
Input: a share ([[-a]]P, [[-p]]Q) of a floating point vector (→a, →p) (provided that →a= (a0, a1, ..., am-1), →p= (P0, p1, ..., pm- 1)), a share ([[→b]]P, [[→σ]]Q) of a floating point vector (-b, →σ) (provided that →b=(b0, b1, ..., bm-1), →σ(σ0, σ1, ..., σm-1 )). Parameter: vector length m Output: a share ([[c]]P, [[t]]Q) of a floating point (c, t) which is a product sum of floating points which are elements of the floating point vector (→a, →p) and floating points which are elements of the floating point vector (→b, →σ)
Here, Σ0≦i<m2p_i+σ_iaibi≒2τc is satisfied.
Step1: By using uniforming exponent part of floating point vector, a share ([[→a′]]P, [[→pmax]]Q) obtained by uniforming exponent parts of elements of the share ([[→a]]P, [[→p]]Q) (provided that →a′=(a′0, a′1, ..., a’m-1), →Pmax=(Pmax, Pmax, ..., Pmax) (provided that pmax=max{ρ0, p1, ..., pm-1}, |→pmax|=m), 2p_iai≒2p_max a′i(0≦i<m) is satisfied), and a share ([[→b′]]P, [[→σmax]]Q) obtained by uniforming exponent parts of elements of the share ([[→b]]P, [[→σ]]Q) (provided that →b′=(b′0, b′1, ..., b’m-1), →σmax= (σmax, σmax, ..., σmax) (provided that σmax=max{σ0, σ1, ..., σm-1}, |→σmax| =m), 2σ_ibi≒2σ_maxb′i(0≦i<m) is satisfied) are calculated.
Step2: A share ([[c]]P, [[t]]Q) (provided that c=Σ0≦i<ma′ib′i, t=pmax+σmax) is calculated.
In the following, the secret exponent part uniforming system 10 will be described below with reference to
As shown in
By cooperative calculation by W secret exponent part uniforming apparatuses 100i, the secret exponent part uniforming system 10 realizes secure computation of exponent part uniforming of a floating point vector being a multi-party protocol. Therefore, a maximum value calculation means 110 (not shown) of the secret exponent part uniforming system 10 is constituted of the maximum value calculation units 1101, ..., 110w, a difference calculation means 120 (not shown) is constituted of the difference calculation units 1201, ..., 120w, a mantissa part calculating means 130 (not shown) is constituted of the mantissa part calculating units 1301, ..., 130w, and an output means 140 (not shown) is constituted of the output units 1401, ..., 140w.
It is assumed that P is a prime number and Q is an order of a residue ring, the secret exponent part uniforming system 10, from a share ([[→a]]P, [[→p]]Q) of a floating point vector (-a, →p) (provided that →a= (a0, a1, ..., am-1), →p= (P0, p1, ..., Pm-1)), calculates a share ([[→b]]P, [[→pmax] ]Q) of a floating point vector (→b, →pmax) obtained by uniforming exponent parts of elements of the floating point vector (→a, →p), (provided that →b= (b0, b1, ..., bm-1), →pmax=(pmax, pmax, ..., pmax) (provided that pmax=max{ρ0, p1, ..., pm-1}, |→pmax|=m), 2p_iai≒2p_maxbi(0≦i<m) is satisfied). In the following the operation of the secret exponent part uniforming system 10 will be described with reference to
In S110, the maximum value calculation means 110 calculates a share [[ρmax]]Q from the share [[→p]]Q. The maximum value calculation means 110 may be configured to execute, for example, maximum value calculation.
In S120, the difference calculation means 120 calculates a share [[→pdif]] Q= [[→ρ] ] Q_[[→pmax] ] Q from the share [[→p]] Q and the share [[pmax]]Q calculated in S110.
In S130, the mantissa part calculation means 130 calculates a share [[→b]]P= ([[b0] ]P, [[b1]]P, ..., [[bm-1]]P) from the share [[→a]]P and the share [[→pdif]]Q, for i which is satisfied 0≦i<m, by calculating a share [[bi]]P (provided that bi=2-p_dif,iai) of the number b1 which is obtained by -pdif,i bit shift of the number ai, from the i-th element [[ai]]P of the share [[→a]]P and the i-th element <<pdif,i>>Q of a share <<→pdif>>Q converted by replicated secret sharing from the share [[→pdif]]Q. The mantissa part calculating means 130 may be configured to execute, for example, shift amount concealment shift (part 2) or shift amount concealment shift (part 3).
In S140, the output unit 140 generates the share ([[→b]]P, [[→pmax]]Q) from the share [[→b]]P calculated in S130 and the share [[pmax]]Q calculated in S110.
According to an embodiment of the present invention, it is possible to efficiently uniform the exponent part of the floating point while keeping confidentiality.
In the following, the secret sum calculation system 20 will be described with reference to
As shown in
By cooperative calculation by W secret sum calculation apparatuses 200i, the secret sum calculation system 20 realizes secure computation of sum of a floating point vector being a multi-party protocol. Therefore, a exponent part uniforming means 210 (not shown) of the secret sum calculation system 20 is constituted of the exponent part uniforming units 2101, ..., 210w, and a sum calculation means 220 (not shown) is constituted of the sum calculation units 2201, ..., 220w.
It is assumed that P is a prime number and Q is an order of a residue ring, and the secret sum calculation system 20, from a share ([[→a]]P, [[→p]]Q) of a floating point vector (→a, →p) (provided that →a= (a0, a1, ..., am-1), →p= (P0, p1, ..., pm-1)), calculates a share ([[b]]P, [[σ]]Q) of a floating point vector (b, σ) which is the sum of floating points which are elements of the floating point vector (→a, →p) (provided that Σ0≦i<m2p_iai≒2σb is satisfied). In the following, the operation of the secret sum calculation system 20 will be described with reference to
In S210, the exponent part uniforming means 210, from a share ([ [→a] ]P, [[→p]]Q), calculates a share ([[→a′]]P, [[→pmax]]Q) of a floating point vector (→a′, →ρmax) obtained by uniforming exponent parts of the floating point vector (→a, →p) (provided that →a′=(a′0, a′1, ..., a’m-1), →ρmax=(pmax, pmax, ..., pmax) (provided that pmax=max{p0, p1, ..., pm-1}, |→pmax|=m), 2p_iai≒2p_max a′i(0≦i<m) is satisfied). It is sufficient that the exponent part uniforming means 210, for example, is constituted of each means included in the secret exponent part uniforming system 10 (that is, a maximum value calculation means 110, a difference calculation means 120, a mantissa part calculation means 130, and an output means 140). In this case, the exponent part uniforming unit 210i of the secret sum calculation apparatus 200i is configured to include a maximum value calculation unit 110i, a difference calculation unit 120i, a mantissa part calculation unit 130i, and an output unit 140i.
In S220, the sum calculation means 220 calculates the shares ([[b]]P, [[σ]]Q) from the shares ([[→a′]]P, [[→pmax]]Q) calculated in S210 (provided that b=Σ0≦i<ma′i, σ=ρmax) .
According to an embodiment of the present invention, the sum of floating points can be calculated efficiently by using secure computation for uniforming the exponent parts of floating points efficiently.
In the following, the secret product sum calculation system 30 will be described below with reference to
As shown in
By cooperative calculation by W secret product sum calculation apparatuses 3001, the secret product sum calculation system 30 realizes secure computation of product sum of floating point vectors being a multi-party protocol. Therefore, an exponent part uniforming means 310 (not shown) of the secret product sum calculation system 30 is constituted of the exponent part uniforming units 3101, ..., 310w, and a product sum calculation means 320 (not shown) is constituted of the product sum calculation units 3201, ..., 320W.
It is assumed that P is a prime number and Q is an order of a residue ring, the secret product sum calculation system 30, from a share ([[→a]]P, [[→p]]Q) of a floating point vector (→a, →p) (provided that →a= (a0, a1, ..., am-1), →p(p0, P1, ..., pm-1)) and a share ([[→b]]P, [[→σ]]Q) (provided that →b=(b0, b1, ..., bm-1), →σ= (σ0, σ1, ..., σm-1)), calculates a share ([[c]]P, [[t]]Q) of a floating point vector (c, t) which is the product sum of floating points which are elements of the floating point vector (→a, →p) and floating points which are elements of the floating point vector (→b, →σ) (provided that Σ0≦i<m2p_i+σ_iaibi≒2tc is satisfied). In the following, the operation of the secret product sum calculation system 30 will be described with reference to
In S310, the exponent part uniforming means 310, from the share ([[→a]]P, [[→p]]Q) and the share ([[→b]]P, [[→σ]]Q), calculates a share ([[→a′]]P, [[→pmax]]Q) of a floating point vector (→a′, →ρmax) obtained by uniforming exponent parts of the floating point vector (→a, →p) (provided that →a′=(a′ 0, a′1, ..., a’m-1), →ρmax=(pmax, pmax, ..., pmax) (provided that pmax=max{ρ0, p1, ..., pm-1}, |→pmax|=m), 2p_iai≒2p_max a′i(0≦i<m) is satisfied), and a share ([[→b′]]P, [ [→σmax]]Q) of a floating point vector (→b′, →σmax) obtained by uniforming exponent parts of the floating point vector (→b, →σ) (provided that →b′=(b′0, b′1, ..., b’m-1), →σmax= (σmax, σmax, ..., σmax) (provided that σmax=max{σ0, σ1, ..., σm-1}, | →σmax | =m), 2σ_ibi≒2σ_maxb′i (0≦i<m) is satisfied). It is sufficient that the exponent part uniforming means 310, for example, is constituted of each means included in the secret exponent part uniforming system 10 (that is, a maximum value calculation means 110, a difference calculation means 120, a mantissa part calculation means 130, and an output means 140). In this case, the exponent part uniforming unit 310i of the secret product sum calculation apparatus 300i is configured to include a maximum value calculation unit 110i, a difference calculation unit 120i, a mantissa part calculation unit 130i, and an output unit 140i.
In S320, the product sum calculation unit 320, from the share [[→a′]]P, [[→pmax]]Q) calculated in S310 and the share ([[→b′]]P, [[→σmax]]Q) calculated in S310, calculates the share ([ [c] ]P, [[t]]Q) (provided that c=Σ0≦i<ma′ib′i, t=ρmax+σmax) .
According to an embodiment of the present invention, the product sum of the floating points can be calculated efficiently by using secure computation for uniforming the exponent parts of the floating points efficiently.
The apparatuses of the present invention includes, for example, as a single hardware entity, an input unit to which a keyboard or the like can be connected, an output unit to which a liquid crystal display or the like can be connected, a communication unit to which a communication apparatus (e.g., a communication cable) capable of communicating with the exterior of the hardware entity can be connected, a CPU (Central Processing Unit; may also include a cache memory, registers, etc.), a RAM or ROM serving as a memory, an external storage device, which is a hard disk, and a bus that connects the input unit, the output unit, the communication unit, the CPU, the RAM, the ROM, and the external storage device such that data can be exchanged there between. As needed, for hardware entity, an device (drive) which can read and write from or to a recording medium such as CD-ROM may be provided. A general-purpose computer or the like is an example of a physical entity including such hardware resources.
A program that is necessary to realize the above-described functions and data and the like that are necessary for processing of the program are stored in the external storage device of the hardware entity (the program does not necessarily have to be stored in the external storage device, and may be stored in, for example, the ROM, which is a read-only storage device). Data and the like that are obtained in the processing of the program are stored in the RAM, the external storage device or the like as appropriate.
In the hardware entity, each program stored in the external storage device (or ROM, etc.) and the data needed for processing of each program are loaded to the memory as needed, and the CPU interprets, executes, and processes them as appropriate. As a result, a CPU realizes a predetermined function (each constitution department that above, ... unit, ... means referred to).
The present invention is not limited to the embodiments described above, and can be modified appropriately within a scope not departing from the gist of the present invention. The processing steps described in the foregoing embodiments do not necessarily have to be executed chronologically in the described order, and may be executed in parallel or individually as necessary or according to the processing capacity of the apparatus that executes the processing.
As described above, in a case where processing functions of the hardware entity (the apparatus according to the present invention) described in the foregoing embodiments are realized by a computer, the processing contents of the functions that are to be included in the hardware entity are described by a program. The processing functions of the hardware entity described above are realized in the computer as a result of the program being executed by the computer.
The program that described this processing contents can be stored in the recording medium which is readable with a computer. For example, anything such as a magnetic recording device, an optical disk, a magneto-optical recording medium, semiconductor memory is enough for a readable recording medium with a computer. Specifically, for example, a hard disk device, a flexible disk, a magnetic tape, or the like can be used as a magnetic recording device, and a DVD (Digital Versatile Disc), a DVD-RAM (Random Access Memory), a CD-ROM (Compact Disc Read Only Memory), CD-R (Recordable)/RW (Rewritable), or the like can be used as an optical disk, an MO (Magneto-Optical disc) or the like can be used as magneto-optical recording medium, and an EEP-ROM (Electronically Erasable and Programmable-Read Only Memory) or the like can be used as a semiconductor memory.
In addition, the distribution of this program is carried out by, for example, selling, transferring, or lending a portable recording medium such as a DVD or a CD-ROM on which the program is recorded. Further, the program may be distributed by storing the program in a storage device of a server computer and transmitting the program from the server computer to other computers via a network.
A computer executing such a program is configured to, for example, first, temporarily store a program recorded on a portable recording medium or a program transferred from a server computer in its own storage device. When executing the processing, the computer reads the program stored in its own storage device, and executes the processing according to the read program. As another execution form of the program, the computer may directly read the program from the portable recording medium and execute processing according to the program, or each time a program is transferred from the server computer to the computer, processing according to the received program may be executed sequentially. In addition, by a so-called ASP (Application Service Provider) type service which does not transfer a program from the server computer to the computer and realizes a processing function only by the execution instruction and the result acquisition, the above-mentioned processing may be executed. It is assumed that the program in this embodiment includes data which is information to be provided for processing by the electronic computer and which is not a direct command to the computer conforming to the program but has a property to specify the processing of the computer.
According to this aspect, the computer is caused to execute a predetermined program to constitute the hardware entity, but at least part of the processing contents may be realized using hardware.
The above descriptions of the embodiments of the present invention are presented for the purpose of illustration and description. The descriptions are neither intended to be comprehensive nor to limit the present invention to the strict form disclosed. Modifications and variations can be made from the teachings described above. The embodiments were selected and described to provide the best illustration of the principle of the present invention such that those skilled in the art can use the present invention in various embodiments suitable for thoroughly considered practical use, and by adding various alterations. All of such modifications and variations are within the scope of the present invention defined by the appended claims that are interpreted according to a fairly, legally, and equitably given range.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2020/039081 | 10/16/2020 | WO |
