Patent Application
20180375768
The present disclosure relates generally to sending of packets through a packet network, such as, but not limited to, according to segment routing of packets through a packet network.
The communications industry is rapidly changing to adjust to emerging technologies and ever increasing customer demand. This customer demand for new applications and increased performance of existing applications is driving communications network and system providers to employ networks and systems having greater speed and capacity (e.g., greater bandwidth). In trying to achieve these goals, a common approach taken by many communications providers is to use packet switching technology. Packets are typically forwarded in a network forwarded based one or more values representing network nodes or paths.
The appended claims set forth the features of one or more embodiments with particularity. The embodiment(s), together with its advantages, may be understood from the following detailed description taken in conjunction with the accompanying drawings of which:
Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with segment routing network processing of packets including packets having a multiple segment routing header packet structure that provides processing and/or memory efficiencies.
In one embodiment, a particular packet is received by a particular router in a network. In response to the particular router data plane ascertaining based on the particular packet a particular segment routing (SR) policy identifying one or more ordered SR identifiers, the particular router adding one or more SR headers to the particular packet resulting in the particular packet including multiple ordered SR headers instead of the particular packet having a packet structure with a single SR header, with each of the one or more SR headers including at least one segment identifier of said one or more ordered SR identifiers. The packet with the multiple ordered SR headers is sent from the particular router.
In one embodiment, the one or more ordered SR identifiers of the particular SR policy includes two or more ordered segment identifiers in a particular order; and adding one or more SR headers includes adding two or more ordered SR headers with two or more ordered segment identifiers distributed among the two or more ordered SR headers such that each of the two or more ordered SR headers includes at least one of the two or more ordered segment identifiers while maintaining the particular order for processing of the two or more ordered segment identifiers among and within the two or more ordered SR headers. In one embodiment, the particular packet is received by the particular router without any SR header, including without any of the ordered SR headers.
In one embodiment, the particular SR policy defines a SR path through the network that is associated with preferentially using multiple smaller SR headers representing an ordered list of SR identifiers rather than a larger SR header representing the ordered list of SR identifiers; and wherein each said one or more SR headers is limited to a maximum of a predetermined quantity of SR identifiers. One embodiment includes the particular router exchanging routing information via a routing protocol with another router in the network, which includes receiving a value representing the predetermined quantity of SR identifiers supported by the specific router, that is SR-capable, along a path through the network according to the particular SR policy, and limiting a SR header to be processed by the specific router to having a maximum of the predetermined quantity of SR identifiers.
Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with segment routing network processing of packets including packets having a multiple segment routing header packet structure that provides processing and/or memory efficiencies. As used herein segment routing (SR) includes, but is not limited to using Internet Protocol Version 4 or 6 (IPv4 or IPv6) addresses as segment routing identifiers (SIDs). Further, SR includes, but is not limited IPv6 SR (SRv6) and/or IPv4 (SRv4).
Embodiments described herein include various elements and limitations, with no one element or limitation contemplated as being a critical element or limitation. Each of the claims individually recites an aspect of the embodiment in its entirety. Moreover, some embodiments described may include, but are not limited to, inter alia, systems, networks, integrated circuit chips, embedded processors, ASICs, methods, and computer-readable media containing instructions. One or multiple systems, devices, components, etc., may comprise one or more embodiments, which may include some elements or limitations of a claim being performed by the same or different systems, devices, components, etc. A processing element may be a general processor, task-specific processor, a core of one or more processors, or other co-located, resource-sharing implementation for performing the corresponding processing. The embodiments described hereinafter embody various aspects and configurations, with the figures illustrating exemplary and non-limiting configurations. Computer-readable media and means for performing methods and processing block operations (e.g., a processor and memory or other apparatus configured to perform such operations) are disclosed and are in keeping with the extensible scope of the embodiments. The term “apparatus” is used consistently herein with its common definition of an appliance or device.
The term “route” is used to refer to a fully or partially expanded prefix (e.g., 10.0.0.1 or 10.0.*.*), which is different than a “path” through the network which refers to a nexthop (e.g., next router) or complete path (e.g., traverse router A then router B, and so on). Also, the use of the term “prefix” without a qualifier herein refers to a fully or partially expanded prefix.
The steps, connections, and processing of signals and information illustrated in the figures, including, but not limited to, any block and flow diagrams and message sequence charts, may typically be performed in the same or in a different serial or parallel ordering and/or by different components and/or processes, threads, etc., and/or over different connections and be combined with other functions in other embodiments, unless this disables the embodiment or a sequence is explicitly or implicitly required (e.g., for a sequence of read the value, process said read value—the value must be obtained prior to processing it, although some of the associated processing may be performed prior to, concurrently with, and/or after the read operation). Also, nothing described or referenced in this document is admitted as prior art to this application unless explicitly so stated.
The term “one embodiment” is used herein to reference a particular embodiment, wherein each reference to “one embodiment” may refer to a different embodiment, and the use of the term repeatedly herein in describing associated features, elements and/or limitations does not establish a cumulative set of associated features, elements and/or limitations that each and every embodiment must include, although an embodiment typically may include all these features, elements and/or limitations. In addition, the terms “first,” “second,” etc., as well as “particular” and “specific” are typically used herein to denote different units (e.g., a first widget or operation, a second widget or operation, a particular widget or operation, a specific widget or operation). The use of these terms herein does not necessarily connote an ordering such as one unit, operation or event occurring or coming before another or another characterization, but rather provides a mechanism to distinguish between elements units. Moreover, the phrases “based on x” and “in response to x” are used to indicate a minimum set of items “x” from which something is derived or caused, wherein “x” is extensible and does not necessarily describe a complete list of items on which the operation is performed, etc. Additionally, the phrase “coupled to” is used to indicate some level of direct or indirect connection between two elements or devices, with the coupling device or devices modifying or not modifying the coupled signal or communicated information. Moreover, the term “or” is used herein to identify a selection of one or more, including all, of the conjunctive items. Additionally, the transitional term “comprising,” which is synonymous with “including,” “containing,” or “characterized by,” is inclusive or open-ended and does not exclude additional, unrecited elements or method steps. Finally, the term “particular machine,” when recited in a method claim for performing steps, refers to a particular machine within the 35 USC § 101 machine statutory class.
Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with segment routing network processing of packets including packets having a multiple segment routing header packet structure that provides processing and/or memory efficiencies. A packet structure is a particular way of organizing information (e.g., header and packet data) of a packet for storing, processing, and communicating in and among network nodes (e.g., routers, hosts).
Different packet structures have varying storage and processing requirements. A segment routing implementation may specify that a single segment routing header is to be used. Further, a segment routing implementation may specify that the ordered list of segments within a segment routing header is to be processed in order from the segment identifier furthest from the beginning of the packet to the one closest to beginning of the packet.
One embodiment improves the storage and processing efficiencies of a SR packet by including multiple ordered segment routing headers with each containing a small number (e.g., one, two, three, etc.) of segment identifiers. Thus, one embodiment might use one or more segment routing headers rather than a single segment routing header. The packet structure of one embodiment allows for fewer read operations (e.g., possibly a single read operation) to access the current segment routing identifier based on which the packet is processed. The packet structure of one embodiment allows for a smaller memory and fewer processing operations to locate and determine the current segment routing identifier based on which the packet is processed as the depth of the segment list can be limited, including to the processing capabilities of network nodes through which the packet will traverse. The packet structure of one embodiment allows for more efficient processing of a packet by having multiple segment routing headers which are added and processed by different administrative domains. The packet structure of one embodiment allows for more efficient processing of a packet by adding a segment routing header rather than manipulating an existing segment routing header, such as for, but not limited to re-routing of the segment routing path of a packet through the network.
In response to receiving a packet, a SR edge node 111, 113 and/or a SR node within network 112 determines a SR policy (e.g., list of segments) through and/or to which to forward a SR packet encapsulating the native packet. These policies can change in response to network conditions, network programming, etc. In one embodiment, the SR policy specifies to add one or more SR headers, each with one or more SR identifiers, resulting in a SR packet having multiple SR headers. In one embodiment, a native packet is received without a SR header, and the SR node encapsulates the native packet in a SR packet including multiple added SR headers, each including one or more SR identifiers. In one embodiment, a SR packet is received with a SR header, and with SR node adding one or more SR headers resulting in a SR packet including multiple added SR headers, each including one or more SR identifiers. In contrast, and for each of these scenarios a single SR header could have been used that includes all of the SR identifiers. However, such a packet structure does not provide the processing and/or memory efficiencies provided by using multiple SR headers.
In one embodiment, apparatus 220 includes one or more processor(s) 221 (typically with on-chip memory), memory 222 (possibly shared memory), storage device(s) 223, specialized component(s) 225 (e.g. optimized hardware such as for performing lookup and/or packet processing operations and/or service function, associative memory, binary and/or ternary content-addressable memory, etc.), and interface(s) 227 for communicating information (e.g., sending and receiving packets, user-interfaces, displaying information, etc.), which are typically communicatively coupled via one or more communications mechanisms 229 (e.g., bus, links, switching fabric, matrix), with the communications paths typically tailored to meet the needs of a particular application.
Various embodiments of apparatus 220 may include more or fewer elements. The operation of apparatus 220 is typically controlled by processor(s) 221 using memory 222 and storage device(s) 223 to perform one or more tasks or processes. Memory 222 is one type of computer-readable/computer-storage medium, and typically comprises random access memory (RAM), read only memory (ROM), flash memory, integrated circuits, and/or other memory components. Memory 222 typically stores computer-executable instructions to be executed by processor(s) 221 and/or data which is manipulated by processor(s) 221 for implementing functionality in accordance with an embodiment. Storage device(s) 223 are another type of computer-readable medium, and typically comprise solid state storage media, disk drives, diskettes, networked services, tape drives, and other storage devices. Storage device(s) 223 typically store computer-executable instructions to be executed by processor(s) 221 and/or data which is manipulated by processor(s) 221 for implementing functionality in accordance with an embodiment.
As shown, multiple ordered SR headers 310 includes one to n SR headers 311-319, with n being a positive integer. Each of these ordered SR headers 311-319 includes an ordered list of one or more segment identifiers (e.g., IPv6 or IPv4 address), each representing a segment (e.g., locator, function, argument) in the network used to process (e.g., forward, manipulate, modify) a SR packet in and through a SR network.
The network processing (e.g., forwarding, manipulating, modifying) of the encapsulated native packet 421 in SR packet 430 (
As determined in process block 505, if the packet was received with a SR header, then processing proceeds to process block 506; otherwise, processing proceeds to process block 511. Continuing with process block 506, the SR header of the received packet is updated to a next current SR identifier (possibly removing a completely processed SR header) and/or decapsulating an encapsulated packet, with processing proceeding to process block 511. In one embodiment, the processing of process block 506 is performed later in the processing of the flow diagram of
Continuing with, and as determined in process block 511, if the SR policy identifies to add a SR header to the received packet, then processing proceeds to process block 514; otherwise, processing proceeds to process block 512 wherein the packet is processed normally and processing proceeds to process block 519.
Continuing with process block 514 and according to the SR policy, a SR packet is created or an additional SR header is added to the received packet resulting in a SR packet including multiple ordered SR headers (e.g., one, two, three SR headers), each with one or more SR identifiers. In one embodiment, two SR headers are added instead of a single SR header. In one embodiment, an additional SR header is added to the received SR packet instead of adding corresponding SR identifiers to the existing SR header. Next, in process block 516, the packet is forwarded (e.g., sent according to routing information) from the SR node, and processing continues with process block 519.
Continuing with process block 519, processing of the flow diagram of
In view of the many possible embodiments to which the principles of the disclosure may be applied, it will be appreciated that the embodiments and aspects thereof described herein with respect to the drawings/figures are only illustrative and should not be taken as limiting the scope of the disclosure. For example, and as would be apparent to one skilled in the art, many of the process block operations can be re-ordered to be performed before, after, or substantially concurrent with other operations. Also, many different forms of data structures could be used in various embodiments. The disclosure as described herein contemplates all such embodiments as may come within the scope of the following claims and equivalents thereof.
This application claims the benefit of U.S. Provisional Application No. 62/525,439, filed Jun. 27, 2017, which is hereby incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 62525439 | Jun 2017 | US |
