Selective differential low-noise amplifier

Abstract

A selective differential low-noise amplifier includes a pair of transistors, each transistor of the pair being connected by its source to a current source and by its gate and/or its source to a differential voltage source, a coupling circuit between the gate of each transistor and the source of the other transistor of the pair, and, for each transistor of the pair, at least one series resonance and parallel resonance resonator connected in series between the source and/or the gate of the transistor and the differential voltage source.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a differential low-noise amplifier that differs from prior art differential low-noise amplifiers in that it includes series resonance and parallel resonance resonators to render it frequency selective.

2. Description of the Prior Art

One prior art differential low-noise amplifier is described in published European patent application EP 1 548 932, for example.

For a differential low-noise amplifier of that kind to be used in a radio signal receiver circuit, it is generally necessary to place it between two filters, an anti-blocking filter being disposed between a receiver antenna and the amplifier itself and an image rejection filter being disposed at the output of the amplifier.

The anti-blocking filter is necessary to prevent the receiver circuit from becoming saturated in the presence of strong out of band interference signals known as blocking signals. The image rejection filter is necessary to reject signals in the image band in the case of a “heterodyne” receiver.

It is also necessary to verify the matching of impedances between the antenna, the filters and the amplifier. The input impedance of the amplifier must correspond to the output impedance of the anti-blocking filter. Similarly, the input impedance of the anti-blocking filter must correspond to the impedance of the antenna and the output impedance of the amplifier must correspond to the input impedance of the image rejection filter.

Thus a radio signal receiver circuit includes a plurality of elements (amplifier, filters) whose input and output impedances must be matched.

The invention aims to solve the problems linked to the complexity of existing receiver circuits by providing a selective differential low-noise amplifier that does not necessitate the addition of antiblocking or image rejection filters on the upstream or downstream side or of impedance matching circuits.

SUMMARY OF THE INVENTION

The invention therefore consists in a selective differential low-noise amplifier including a pair of transistors, each transistor of the pair being connected by its source to a current source and by its gate and/or its source to a differential voltage source, a coupling circuit between the gate of each transistor and the source of the other transistor of the pair, and, for each transistor of the pair, at least one series resonance and parallel resonance resonator connected in series between the source and/or the gate of the transistor and the differential voltage source.

Associating this type of resonator with the pair of transistors of the differential low-noise amplifier provides a high Q filtering function and at the same time adjusts the input impedance of the differential amplifier by modifying the dimensions of the resonators.

Each coupling circuit is preferably a capacitive circuit.

The series resonance and parallel resonance resonator is preferably a resonator whose equivalent circuit includes a series RLC circuit connected in parallel with a capacitive circuit. Piezo-electric resonators, and in particular bulk acoustic wave (BAW) resonators, have this property.

In a preferred embodiment of the invention the differential low-noise amplifier includes, for each transistor of the pair, a first series resonance and parallel resonance resonator connected in series between the gate of the transistor and the differential voltage source and a second series resonance and parallel resonance resonator connected in series between the source of the transistor and the differential voltage source.

In particular, to provide the required impedance matching and filtering, the first resonator and the second resonator are detuned.

Furthermore, for the differential amplifier to be able to fulfill its voltage amplification function completely, the two transistors of the pair are connected by their drain to respective load circuits.

The two transistors of the pair are advantageously connected to their respective load circuits via two other transistors in a cascode configuration.

To improve the frequency selectivity of the differential low-noise amplifier, the aforementioned circuit is connected to the differential voltage source via a prefilter circuit including a symmetrical lattice circuit with four branches equipped with series resonance and parallel resonance resonators.

Each branch of the lattice circuit of the prefilter circuit preferably includes a resonator, two of the resonators of the lattice circuit, disposed face-to-face, being designed to have the same admittance as the resonators connected in series to the gate of the two transistors of the pair, the other two resonators of this lattice circuit, also disposed face-to-face, being designed to have the same admittance as the resonators connected in series to the source of the two transistors of the pair.

The invention will be better understood in the light of the following description given by way of example only and with reference to the appended drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a preferred embodiment of a differential low-noise amplifier of the invention.

FIG. 2 is an equivalent circuit of a resonator used in the FIG. 1 amplifier.

FIG. 3 is a small-signal equivalent half-circuit for modeling a transconductance circuit of the FIG. 1 differential amplifier.

FIGS. 4 and 5 are diagrams indicating the input impedance values of the FIG. 1 amplifier that correspond to the numerical example set out in table 2.

FIG. 6 is a diagram of the modulus of the input reflection coefficient of the transconductance circuit modeled in FIG. 3 as a function of normalized frequency.

FIG. 7 is a diagram representing the modulus of the effective transconductance of the transconductance circuit modeled in FIG. 3 as a function of normalized frequency.

FIG. 8 is a diagram representing the effective voltage gain of the FIG. 1 differential amplifier as a function of frequency.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The differential low-noise amplifier 10 represented in FIG. 1 includes a transconductance circuit 12 connected to a set 14 of load circuits via a cascode circuit 16. This differential low-noise amplifier 10 also includes a prefilter circuit 18.

More precisely, two transistors 20 and 22 in the transconductance circuit 12 are connected by their source to two identical sources 24 of a bias current I₀ and by their gate and their source to a differential voltage source including a negative source 26 and a positive source 28. The negative voltage source 26 produces a voltage of value v_in⁻=v₀−δv, for example, and the positive voltage source 28 produces a voltage of value v_in⁺=v₀+δv, for example.

There is a first coupling circuit 30 between the gate of the transistor 20 and the source of the transistor 22. Similarly, there is a second coupling circuit 32 between the gate of the transistor 22 and the source of the transistor 20. These two coupling circuits 30 and 32 are preferably capacitive circuits, of equal capacitance C_c, as indicated in FIG. 1.

The transconductance circuit 12 further includes a first resonator 34 using series resonance and parallel resonance, for example a BAW type resonator, of admittance Y₁, connected in series between the gate of the transistor 20 and the differential voltage source. It also includes a second resonator 36, for example of the same type, of admittance Y₂, connected in series between the source of the transistor 20 and the differential voltage source. The first and second resonators 34 and 36 are preferably detuned.

Similarly, a third BAW resonator 38 is connected in series between the gate of the transistor 22 and the differential voltage source and a fourth BAW resonator 40 is connected in series between the source of the transistor 22 and the differential voltage source. Through considerations of symmetry, the admittance of the third resonator 38 has the value Y₁ and the admittance of the fourth resonator 40 has the value Y₂. The point common to the resonators 34 and 36 constitutes a first input node 120 of the transconductance circuit 12 and the point common to the resonators 38 and 40 constitutes a second input node 130 of that same transconductance circuit.

It will be noted that the resonators 34, 36, 38 and 40 connected in series to the gates and the sources of the transistors 20 and 22 are therefore coupled by the two capacitive coupling circuits 30 and 32 as well as by the transistors 20 and 22 themselves.

The functional characteristics of the resonators 34, 36, 38 and 40 are described in detail with reference to FIG. 2. The operation of the transconductance circuit 12, which is symmetrical about the axis A-A indicated in FIG. 1, is described with the aid of the small-signal equivalent half-circuit represented in FIG. 3.

The drain of the transistor 20 is connected to a first load circuit 46. Similarly, the drain of the transistor 22 is connected to a second load circuit 48. These two load circuits 46 and 48 are conventionally connected to each other and to a source of a voltage V_dd.

It will be noted that the load circuits 46 or 48 are parallel LC resonators the capacitive portion of which consists of stray capacitances and a capacitive load. The inductance L_load of each of these circuits causes the capacitive portion to resonate at a frequency tuned to the useful band of the signal. The Q factor of the passive components used fixes the impedance obtained at resonance.

To increase the output impedance of the transconductance circuit 12, the transistors 20 and 22 are connected to the load circuits 46 and 48, respectively, via the cascode circuit 16, which includes two other transistors 42 and 44 connected in a cascode arrangement, their gates being connected to a common source of a voltage V_B. Each transistor 42 or 44 is connected to the drain of one of the transistors 20 or 22 and connected to the corresponding load circuit 46 or 48.

The cascode circuit 16 also limits the effect of the Miller capacitance on the overall stability of the differential low-noise amplifier 10.

The prefilter circuit 18 is connected between the input nodes 120 and 130 of the transconductance circuit 12 and the differential voltage source 26, 28.

It includes a symmetrical lattice arrangement with four branches equipped with resonators 50, 52, 54 and 56, for example BAW type resonators. The resonators 50 and 52, which are disposed face-to-face in the lattice arrangement, are carefully selected to have the same admittance Y₁ as the resonators 34 and 38. The resonators 54 and 56, which are also disposed face-to-face in the lattice arrangement, are selected to have the same admittance Y₂ as the resonators 36 and 40.

Adding this prefilter circuit 18 improves the frequency selectivity of the differential low-noise amplifier 10.

FIG. 2 shows a first order equivalent circuit of the resonators 34, 36, 38, 40, 50, 52, 54 and 56 used in the differential low-noise amplifier 10.

It includes an RLC circuit comprising a resistor R_s, an inductor L_s and a capacitor C_s, connected in parallel with a capacitive circuit comprising a resistor R₀ and a capacitor C₀.

Accordingly, the admittance y normalized at Y₀ of a resonator whose series resonant frequency has the value ω_s=k ω₀ is expressed by the following equation:

$\begin{array}{cc}y=\frac{Y}{Y_0}=k·\frac{\rho Q}{1+j{\mathrm{Qx}}_k}+\frac{\mathrm{j\Omega }}{1+\mathrm{j\Omega tan}\left(\delta \right)/k},& \left(1\right)\end{array}$ in which x_k is the detuning defined by the following equation:

$\begin{array}{cc}{x}_k=\frac{\Omega }{k}-\frac{k}{\Omega }.& \left(2\right)\end{array}$

In equation (1), ρ is a technological factor that represents the piezo-electric coupling and Q is the Q factor of series resonance of the resonator whose equivalent circuit is represented in FIG. 2. The factor tan(δ) is the loss factor of the dielectric capacitance, such that R₀Y₀=tan(δ)/k.

Finally, the normalization magnitudes used in equation (1) are given by the following table:

TABLE 1
Normalization magnitudes
	Magnitude	Normalization
	Frequency	Ω = ω/ω0	Ωs= ωs/ω0 = k
	Admittance	y = Y/Y0	Y0= ω0 · C0
	Impedance	z = Z · Y0
	Capacitance	c = C/C0

Equation (1) can be simplified as follows:

$\begin{array}{cc}y\approx k·\frac{\rho Q}{1+j{\mathrm{Qx}}_k}+j\Omega ,\mathrm{if}\Omega <<\frac{k}{\tan \left(\delta \right)}.& \left(3\right)\end{array}$

It will be noted that the operating principle of the resonator described here is independent of the technique used to produce it. It must therefore be possible to use it with any type of resonator whose equivalent circuit corresponds to that of FIG. 2.

In the FIG. 1 circuit, the resonators 34, 38, 50 and 52 of admittance Y₁ have a series resonant frequency equal to ω_1s=k_1s ω₀ and the resonators 36, 40, 54 and 56 of admittance Y₂ have a different series resonant frequency equal to ω_2s=k_2s /ω₀. The ratio k_2s/k_1s expresses the detuning of the resonators of admittance Y₂ relative to the resonators of admittance Y₁.

The transconductance circuit 12 operates in differential mode and is exactly symmetrical. FIG. 3 shows its small-signal equivalent half-circuit.

This equivalent half-circuit is used to calculate the performance of the low-noise amplifier. The magnitudes C₁, C₂ and Y_c used in FIG. 3 are defined by the following equations:C₁=C_c+C_gs,  (4)C₂=C_c+C_gs,  (5)Y_c=jω·(C_c−C_gs),  (6)in which C_gs represents the stray capacitance of the transistor 20 or 22 between its source and its gate.

Furthermore, y_m and y_ms represent transconductance parameters of voltage-controlled current sources.

For the transfer of power to be optimized it is necessary for the input impedance Z_in of the differential low-noise amplifier to be matched to the impedance Z₀ of the antenna of the radio signal receiver circuit. This condition is expressed in mathematical terms by the following equation:Z₀=Z_in*.  (7)

It is easy to calculate the impedance of the differential low-noise amplifier from the small-signal equivalent half-circuit:

$\begin{array}{cc}{Y}_{in}=\frac{1}{Z_{in}}=H_1·Y_1+H_2·Y_2,& \left(8\right)\end{array}$ in which H₁ is defined by:

$\begin{array}{cc}{H}_1=1-\frac{v_g}{v_{in}},& \left(9\right)\end{array}$ and H₂ is defined by:

$\begin{array}{cc}{H}_2=1-\frac{v_s}{v_{in}}.& \left(10\right)\end{array}$

The auxiliary functions H₁ and H₂ are calculated as a function of the magnitudes of the small-signal equivalent half-circuit and given by the following equations, in which s=jω:

$\begin{array}{cc}{H}_1=1-\left(Y_2-\frac{Y_1}{Y_c}·\left({\mathrm{sC}}_2+Y_2+y_{ms}\right)\right)·\frac{1}{D},& \left(11\right)\\ H_2=1-\left(\left(Y_c-y_m\right)·\frac{Y_1}{Y_c}-\frac{{\mathrm{sC}}_1+Y_1}{Y_c}·Y_2\right)·\frac{1}{D},\mathrm{where}& \left(12\right)\\ D=Y_c-y_m-\left({\mathrm{sC}}_2+Y_2+y_{ms}\right)·\frac{{\mathrm{sC}}_1+Y_1}{Y_c}.& \left(13\right)\end{array}$

From the above equations, which ignore the Miller capacitance (which is partly justified by the presence of the cascode circuit 16 connected to the transconductance circuit 12 which limits the effect of the Miller capacitance), the complex locus of the input impedance Z_in of the differential low-noise amplifier 10 in the vicinity of the series resonance and parallel resonance frequencies of the resonators 34, 36, 38 and 40 has the general form shown in the FIG. 4 diagram. The curve 58 represents this complex locus.

Note that on this curve there are two frequencies ω_a and ω_b between the series resonance of the resonators 34 and 38 and the parallel resonance of the resonators 36 and 40, for which the input impedance is the same. Note also that, empirically, it is possible to cancel out the imaginary part of this input impedance completely by a careful choice of the capacitance C_c of the coupling circuits 30 and 32.

Accordingly, by appropriately adjusting the dimensions of the resonators, it is possible to match the differential amplifier 10 perfectly to a real impedance Z₀ (that of the antenna) at the two different frequencies ω_a and ω_b. Between these two frequencies, the value of the input impedance of the differential amplifier 10 varies little in the vicinity 60 of the point (Z₀, 0) in the complex plane, as shown by the loop formed by the curve 58 in that vicinity 60.

A numerical example is given below. The normalized values from table 1 are repeated in table 2 below:

TABLE 2
Normalized values for the numerical example
Quality factor	Q	600
Coupling factor	ρ	0.054
Dielectric loss factor	tan(δ)	0.07
Transconductance	yms/Y0	0.7
Gate-source capacitance	Cgs/C0	60 · 10−3
Y1 and Y2 detuning factor	k2s/k1s	1.025
Coupling capacitance	Cc/C0	8.8925
Matching frequencies	Ωa = ωa/ω0	1.0249
	Ωb = ωb/ω0	1.0358
Input impedance	Zin(ωa, ωb) · Y0= z0 · Y0	0.6258 + 0 j

A different representation of the curve 58 in FIG. 5 using the Smith chart for values of Ω from 0.8 to 1.2 and for the numerical values set out in table 2 shows clearly that the input impedance Z_in of the differential amplifier 10 is virtually constant between ω_a and ω_b and, more generally, the stability of the complex locus of Z_in, since the curve 58 remains within the unit circle of the Smith chart around the point (Z₀, 0).

It is also possible to represent the impedance matching as a function of Ω by the parameter Γ_in defined by the following equation:

$\begin{array}{cc}{\Gamma }_{in}=\frac{Z_{in}-Z_0}{Z_{in}+Z_0}.& \left(14\right)\end{array}$

Γ_in is the input reflection coefficient defined relative to the impedance Z₀ of the antenna. The FIG. 6 diagram represents the evolution of this coefficient for the numerical values from table 2. It will be noted that the two offset matching frequency values ω_a and ω_b provide for reasonable matching over a frequency band of around 2%.

Moreover, to measure the gain of the differential low-noise amplifier 10 independently of the load circuits, it is beneficial to represent the effective transconductance g_eff by the following equation:

$\begin{array}{cc}{g}_{\mathrm{eff}}=\frac{i_{\mathrm{out}}}{v_0}=\frac{i_{\mathrm{out}}}{v_{in}}·\frac{1}{1+y_{in}{z}_0},\mathrm{where}& \left(15\right)\\ \frac{i_{\mathrm{out}}}{v_{in}}=y_m·\frac{v_g}{v_{in}}-y_{ms}·\frac{v_s}{v_{in}}=\frac{y_{ms}}{n}·\left(1-H_1\right)-y_{ms}·\left(1-H_2\right).& \left(16\right)\end{array}$

The FIG. 7 diagram is obtained by inserting the numerical values from table 2.

Comparing FIGS. 6 and 7, note in particular that the bandwidth of the effective transconductance g_eff corresponds to the frequency band [ω_a, ω_b] in which impedance matching is effected.

Finally, FIG. 8 shows the improvement resulting from the presence of the prefilter circuit 18 in the differential amplifier 10. The signals are more strongly attenuated outside the bandwidth [ω_a, ω_b]. Selectivity is thus significantly better.

It is clearly apparent that a differential low-noise amplifier as described above provides an amplification function combined with highly selective filtering of radio-frequency signals received by the antenna of the receiver circuit.

This kind of amplifier does not necessitate the addition of passive components over and above those already used to perform filtering. In particular, no antiblocking or image rejection filter is necessary.

Claims

1. A selective differential low-noise amplifier including a pair of transistors, each transistor of said pair being connected by its source to a current source and by its gate and/or its source to a differential voltage source, a coupling circuit between the gate of each transistor and the source of the other transistor of said pair, and, for each transistor of said pair, at least one series resonance and parallel resonance resonator connected in series between the source and/or the gate of said transistor and said differential voltage source.

2. The selective differential low-noise amplifier according to claim 1, wherein each coupling circuit is a capacitive circuit.

3. The selective differential low-noise amplifier according to claim 1, wherein said series resonance and parallel resonance resonator is a resonator whose equivalent circuit includes a series RLC circuit connected in parallel with a capacitive circuit.

4. The selective differential low-noise amplifier according to claim 1, wherein said series resonance and parallel resonance resonator is a piezo-electric resonator, in particular a bulk acoustic wave resonator.

5. The selective differential low-noise amplifier according to claim 1, including, for each transistor of said pair, a first series resonance and parallel resonance resonator connected in series between the gate of said transistor and said differential voltage source and a second series resonance and parallel resonance resonator connected in series between the source of said transistor and said differential voltage source.

6. The selective differential low-noise amplifier according to claim 5, wherein said first resonator and said second resonator are detuned.

7. The selective differential low-noise amplifier according to claim 1, wherein the two transistors of said pair are connected by their drain to respective load circuits.

8. The selective differential low-noise amplifier according to claim 7, wherein the two transistors of said pair are connected to their respective load circuits via two other transistors in a cascode configuration.

9. The selective differential low-noise amplifier according to claim 1, wherein the two transistors of said pair are connected by their gate and their source to said differential voltage source via a prefilter circuit including a symmetrical lattice circuit with four branches equipped with series resonance and parallel resonance resonators.

10. The selective differential low-noise amplifier according to claim 9, wherein each branch of said lattice circuit of said prefilter circuit includes a resonator, two of said resonators of said lattice circuit, disposed face-to-face, being designed to have the same admittance as the resonators connected in series to the gate of the two transistors of said pair, the other two resonators of this lattice circuit, also disposed face-to-face, being designed to have the same admittance as the resonators connected in series to the source of the two transistors of said pair.