Patent Grant
6985023
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-023324, filed Jan. 31, 2003, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device having a P-channel transistor to which a well voltage is applied.
2. Description of the Related Art
In semiconductor memory devices, a control circuit controlling memory cells is formed around the memory cells. The control circuit comprises elements such as a transistor or diode. For example, the control circuit is composed of a P-channel transistor 40 shown in FIG. 5. The P-channel transistor 40 is formed in a substrate or well formed in the substrate, and supplied with well voltage (back gate voltage) VB in addition to gate voltage VG, source voltage VS and drain voltage VD. The Source voltage VS is supplied from a first power supply and it is a power supply potential Vcc. The Well voltage VB is supplied from a second power supply formed of a charge-pump circuit in the semiconductor memory device, and it is usually a boosted potential Vpp. That is, VB=Vpp≧VS=Vcc.
As illustrated in
JPN. PAT. APPLN. KOKAI Publication No. 7-131332 is given as the document relevant to a CMOS circuit having the following structure. According to the structure, P-channel and N-channel MOS transistors are connected in series, and the node between both MOS transistors is used as an output terminal. In
FIG. 5 and
According to an aspect of the present invention, there is provided a semiconductor device comprising:
a first transistor having a first conduction type first semiconductor region and a second conduction type second semiconductor region formed in the first semi-conductor region, the first semiconductor region being supplied with a first prescribed potential, the second semiconductor region being supplied with a second prescribed potential; and
a potential generator circuit generating the first prescribed potential, wherein
the potential generator circuit has a first power supply terminal supplied with a first power supply potential, a second power supply terminal supplied with a second power supply potential set to a higher potential than the first power supply potential, and an output terminal outputting the first prescribed potential, and
the potential generator circuit outputs the second power supply potential as the first prescribed potential when the second power supply potential is higher than a predetermined potential, and outputs the first power supply potential as the first prescribed potential when the second power supply potential is lower than the predetermined potential.
According to another aspect of the present invention, there is provided a semiconductor device comprising:
a first transistor having a first conduction type first semiconductor region and a second conduction type second semiconductor region formed in the first semiconductor region, the first semiconductor region being supplied with a first prescribed potential, the second semiconductor region being supplied with a second prescribed potential; and
a potential generator circuit generating the first prescribed potential, wherein
the potential generator circuit has a first power supply terminal supplied with a first power supply potential, a second power supply terminal supplied with a second power supply potential set to a higher potential than the first power supply potential, and an output terminal outputting the first prescribed potential, and
the potential generator circuit comprises:
a second transistor having a source connected to the second power supply terminal supplied with the second power supply potential, and a drain connected to the output terminal outputting the first prescribed potential;
a third transistor having source and gate connected to the first power supply terminal supplied with the first power supply potential, and a drain connected to the output terminal outputting the first prescribed potential; and
an inverter circuit having an input terminal connected to the second power supply terminal, and an output terminal connected to the gate of the second transistor.
According to a further aspect of the present invention, there is provided a semiconductor device comprising:
a first transistor having a first conduction type first semiconductor region and a second conduction type second semiconductor region formed in the first semiconductor region, the first semiconductor region being supplied with a first prescribed potential, the second semiconductor region being supplied with a second prescribed potential; and
a potential generator circuit generating the first prescribed potential, wherein
the potential generator circuit has a first power supply terminal supplied with a first power supply potential, a second power supply terminal supplied with a second power supply potential set to a higher potential than the first power supply potential, and an output terminal outputting the first prescribed potential, and
the potential generator circuit comprises:
a second transistor having a source connected to the second power supply terminal supplied with the second power supply potential, and a drain connected to the output terminal outputting the first prescribed potential;
a third transistor having source and gate connected to the first power supply terminal supplied with the first power supply potential, and a drain connected to the output terminal outputting the first prescribed potential; and
a comparator circuit including a differential amplifier circuit having a pair of input terminals and an output terminal;
wherein one of the pair of input terminals of the differential amplifier circuit of the comparator circuit is connected with the first power supply terminal, the other thereof is connected with a source of a fourth transistor having drain and gate both connected to the first power supply terminal, and the output terminal of the differential amplifier circuit of the comparator circuit is connected to the gate of the second transistor.
Embodiments of the present invention will be described below with reference to the accompanying drawings.
(First Embodiment)
A semiconductor device according to a first embodiment of the present invention will be explained below with reference to
In semiconductor memory devices, a control circuit controlling memory cells is formed around the memory cells. The control circuit comprises elements such as a transistor or diode. For example, the control circuit is composed of a P-channel transistor 10 shown in FIG. 1. The P-channel transistor 10 is formed in a substrate or well formed in the substrate, and supplied with well voltage (back gate voltage) VB in addition to gate voltage VG, source voltage VS and drain voltage VD. The voltage VB is not limited to the well voltage, and a substrate voltage may be supplied.
As illustrated in
Controlled boosted potential Vpp′ is supplied as the well voltage VB of the P-channel transistor 10. A well voltage generator circuit shown in
The terminal A is connected with the source of the P-channel transistor 21, and the gate of the P-channel transistor is connected to the output of an inverter circuit 23. The input of the inverter circuit 23 is connected to the terminal A. The back gate and drain of the P-channel transistor 21 are interconnected. The inverter circuit 23 comprises a CMOS circuit, and is connected to first power supply potential Vcc and reference potential Vss (e.g., ground potential).
The terminal B is connected with the source of the N-channel transistor 22. The source and gate of the N-channel transistor 22 are interconnected, that is, diode-connected. The well voltage (back gate voltage) of the N-channel transistor 22 is reference voltage Vss; for example, ground potential. The voltage of the common drain of interconnected P-channel and N-channel transistors 21 and 22 is applied as well voltage VB to the well of the P-channel transistor 10. The threshold Vthn of the N-channel transistor 22 is about 0.2 V to 0.3 V, for example. The threshold Vthp of the P-channel transistor 21 is about 0.6 V, for example. P-channel and N-channel transistors 21 and 22 constituting the well voltage generator circuit are provided for generating the well voltage. The current flow rate is relatively low; therefore, the P-channel and N-channel transistors 21 and 22 form a low-consumption type circuit.
The operation of the well voltage generator circuit shown in
For example, a great many cells are operated; for this reason, a large current flows through the power supply supplying the voltage Vpp to the terminal A, or noise is generated. In this case, the boosted potential Vpp becomes low. When the voltage Vpp becomes lower than (Vcc−Vthn), the N-channel transistor 22 comprising a transistor having a low threshold voltage turns on, and When the voltage Vpp becomes lower than the circuit threshold of the inverter circuit 23, the P-channel transistor 21 turns off. For this reason, the controlled boosted potential Vpp′ has the relationship of Vpp′=Vcc−Vthn; therefore, it is equal approximately to power supply potential Vcc. In other words, the well voltage VB has the relationship of VB=Vcc−Vthn; therefore, it is equal approximately to power supply potential Vcc. As a result, the PN junction between the source and well is prevented from being forward-biased; therefore, it is also prevented from turning on. Consequently, it is possible to prevent the influence on semiconductor elements.
In the well voltage generator circuit shown in
If the well voltage VB is lower than the source voltage VS, a slight charge may flow through the PN junction between source and well, even if the difference between well voltage VB and source voltage VS is less than the threshold voltage of the PN junction between source and well. However, a large number of carriers are not generated in the substrate. Thus, neither parasitic transistors latch up nor a large current flows therethrough. Therefore, no influence is given on elements.
The well voltage generator circuit shown in
(Second Embodiment)
In semiconductor memory devices, a control circuit controlling memory cells is formed around the memory cells. The control circuit comprises elements such as a transistor or diode. Similarly to the first embodiment, the control circuit is composed of a P-channel transistor 10 shown in
As illustrated in
Controlled boosted potential Vpp′ is supplied as the well voltage VB of the P-channel transistor 10. A well voltage generator circuit shown in
The terminal A is connected with the source of the P-channel transistor 21, and the gate of the P-channel transistor 21 is connected with the output of a comparator circuit 24. The comparator circuit 24 comprises a differential amplifier circuit 25 including a current mirror circuit as a load. The current mirror circuit is composed of two P-channel transistors 31 and 32. The input section of the differential amplifier circuit 25 includes two differential transistors 33 and 34 each comprising an N-channel transistor. The input (gate) of the differential transistor 33 of the differential amplifier circuit is connected to the terminal A, and inputted with boosted potential Vpp. The input (gate) of the differential transistor 34 of the differential amplifier circuit is connected to the drain of an N-channel transistor 26, and inputted with potential Vcc−Vthn via the N-channel transistor 26. Vthn is the threshold value of the N-channel transistor 26. The potential Vcc−Vthn is generated when power supply potential Vcc is connected to the source of the N-channel transistor 26 having connected source and gate.
The terminal B is connected with the source of the N-channel transistor 22. The source and gate of the N-channel transistor 22 are interconnected, that is, diode-connected. The well voltage (back gate voltage) of the N-channel transistor 22 is reference voltage Vss; for example, ground potential. The voltage of the common drain of interconnected P-channel and N-channel transistors 21 and 22 is applied as well voltage VB to the well of the P-channel transistor 10. The threshold voltage Vthn of the N-channel transistor 22 is lower than the threshold voltage Vthp of the P-channel transistor 21. The threshold Vthn of the N-channel transistor 22 is about 0.2 V to 0.3 V, for example. The threshold Vthp of the P-channel transistor 21 is about 0.6 V, for example. N-channel transistor 22 of the potential switching circuit 20 and N-channel transistor 26 of the input section of the differential amplifier circuit 25 have substantially the same size and substantially the same threshold. P-channel and N-channel transistors 21 and 22 constituting the well voltage generator circuit are provided for generating the well voltage. The current flow rate is relatively low; therefore, the P-channel and N-channel transistors 21 and 22 form a low-consumption type circuit.
The operation of the well voltage generator circuit shown in
For example, a great many cells are operated; for this reason, a large current flows through the power supply supplying the voltage Vpp to the terminal A, or noise is generated. In this case, the boosted potential Vpp becomes low. In the comparator circuit 24, when the boosted potential Vpp becomes low, and a difference occurs in the input voltage to differential transistors 33 and 34, the output current increases or decreases so that the current ratio of differential transistors 33 and 34 can be kept constant in the comparator circuit 24. The current from P-channel transistors 31 and 32 constituting the current mirror circuit is distributed to current flowing to differential transistors 33 and 34 and output current flowing to the out terminal. Therefore, the output current becomes constant regardless of the load connected to the output terminal. The difference of the input voltage to differential transistors 33 and 34 is the output voltage, and the amplification degree can be controlled from the external device.
The comparator circuit 24 outputs an “H” level when the boosted potential Vpp is lower than a predetermined level. More specifically, when Vpp is lower than Vcc−Vthn, the comparator circuit 24 outputs an “H” level. On the other hand, when boosted potential Vpp is higher than the predetermined level, the comparator circuit 24 outputs an “L” level. In other words, when Vpp is higher than Vcc−Vthn, the comparator circuit 24 outputs an “L” level. Thus, the boosted potential Vpp falls, and the N-channel transistor 22 comprising a transistor having a low threshold value turns on while the P-channel transistor 21 turns off. Therefore, the controlled boosted potential Vpp′ has the relationship of Vpp′=Vcc−Vthn, that is, equal approximately to power supply potential Vcc. In other words, the well voltage VB has the relationship of VB=Vcc−Vthn; therefore, it is equal approximately to power supply potential Vcc. Since the N-channel transistor is formed of a transistor having a low threshold, the PN junction between the source and well is prevented from being forward-biased; therefore, it is also prevented from turning on.
In the well voltage generator circuit shown in
If the well voltage VB is lower than the source voltage VS, a slight charge may flow through the PN junction between source and well, even if the difference between well voltage VB and source voltage VS is less than the threshold voltage of the PN junction between source and well. However, a large number of carriers are not generated in the substrate. Thus, neither parasitic transistors latch up nor a large current flows therethrough. Therefore, no influence is given on elements.
With the embodiment, when the boosted potential Vpp falls and the N-channel transistor 22 comprising a transistor having a low threshold value turns on, the P-channel transistor 21 turns off. As the result, floating of the potential does not occur.
According to the embodiments described above, even if the boosted potential Vpp falls, the PN junction between source and well (or substrate) is prevented from being forward-biased, so that it can be prevented from turning on. As a result, it is possible to prevent the influence on semiconductor elements.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2003-023324 | Jan 2003 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 5467048 | Watanabe | Nov 1995 | A |
| 5966043 | Jinbo | Oct 1999 | A |
| RE37217 | Kobayashi | Jun 2001 | E |
| 6242971 | Manstretta et al. | Jun 2001 | B1 |
| 6333571 | Teraoka et al. | Dec 2001 | B1 |
| 6469568 | Toyoyama et al. | Oct 2002 | B2 |
| Number | Date | Country |
|---|---|---|
| 04-000753 | Jan 1992 | JP |
| 07-131332 | May 1995 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20040227566 A1 | Nov 2004 | US |
