Patent Application
20150137780
This invention relates to linear regulators for integrated circuits, and more particularly to low-dropout (LDO) regulators having an adjustable bias current.
DC linear voltage regulators are circuits utilized to supply a regulated output voltage to a load circuit, and typically include an output stage transistor (e.g., a power FET) and a differential (operational) amplifier (error amplifier). The differential amplifier compares a fraction of the regulated output voltage (which is fed back by way of a voltage divider to the non-inverting input terminal of the differential amplifier) with a stable (bandgap) reference voltage that is supplied to the amplifier's inverting input terminal, and generates a gate voltage that is applied to the gate terminal of the power FET, which is connected between an unregulated voltage supply and the load. During operation, the differential amplifier adjusts (increases or decreases) the gate voltage as needed such that the output voltage is maintained at the desired regulated voltage level. For example, if R/C load conditions change such that the output voltage increases relative to the reference voltage (e.g., by way of the load circuit entering a hibernation or sleep mode), the differential amplifier reduces the gate voltage applied to the power FET, thereby adjusting (reducing) the output voltage to the desired regulated voltage level. Conversely, if the output voltage decreases relative to the reference voltage (e.g., due to the load switching from a sleep mode to a normal operating mode), the differential amplifier increases the gate voltage applied to the power FET, thereby adjusting (increasing) the output voltage to the desired regulated voltage level. By constantly adjusting the output voltage in this way, the LDO regulator maintains a constant regulated voltage across the load.
A low-dropout (LDO) regulator is a type of DC linear voltage regulator that can operate with a very small input-output differential voltage, which provides advantages over other linear voltage regulators by supporting lower minimum operating voltages, providing higher efficiency operations, and reducing heat generation. LDO regulators utilize a current source circuit to stabilize and maintain the regulated output voltage under low or zero load current conditions. The current source circuit is typically coupled in parallel with the load between the regulated output voltage and ground, and functions to draw a minimal sink current through the power FET. That is, when the load enters a standby or sleep mode (i.e., is drawing zero or a very small load current), the current source functions to draw a minimum sink current from the FET in order to maintain the desired regulated voltage across the load.
During periods of zero or low load current, the energy consumption and heat generation produced by the current source circuitry of an LDO are considered acceptable because the generated sink current serves the beneficial purpose of maintaining the regulated output voltage at a stable operating bandwidth, and also because the total amount of heat generated by the LDO is relatively small during these periods. However, under normal operating (i.e., high load current) conditions, unless the current source circuitry is disabled, the current through the power FET is higher than load current (i.e., by the amount of the sink current) without providing a functional benefit, which unnecessarily increases power consumption and heat generation. That is, during high load current conditions, the sink current drawn through the current source circuit provides no benefit in exchange for the consumed energy and generated heat because the high load current facilitates stable LDO operating bandwidth. Moreover, because the sink current flows from the FET output to ground, the amount of heat generated is proportional to the regulated LDO output voltage. As such, in circuits requiring high regulated voltages, heat dissipation in the current source is a significant factor in overall LDO heating, and thus may become a critical factor limiting overall performance of the LDO circuit. Accordingly, although the use of current source circuitry is beneficial during periods of zero or very small load currents, the current source circuitry effectively becomes a liability by undesirably consuming energy and generating heat during periods of high load current.
To reduce power consumption and to avoid possible overheating problems, LDO regulators typically include a mechanism for turning off the sink current source during periods when the load consumes more than the minimum sink current (i.e., when the load is in a normal operating state). Prior art approaches used to turn off the sink current source during high load current conditions use control circuitry to monitor (sense) the load current (or LDO output voltage), and to turn off the sink current source when the load current is higher than the minimum sink current (or when the output voltage falls below a minimum voltage level). A problem with these prior art approaches is that the control circuitry remains active (i.e., continuously draws current) in order to monitor the load conditions. That is, the prior art solution control circuitry continues to draw operating current through the output stage/amplifier at all times in order to continuously monitor the load current, so even when the bias current provider/transistor has been turned off because the load current is greater than the minimum sink current, the control circuitry continues to generate heat and to draw a significant amount of power that reduces battery life in portable devices. Moreover, the complicated control circuitry of the prior art approaches requires a significant amount of chip area, which increases production costs.
What is needed is a linear regulator having an self-adjustable sink current bias source that reliably draws a sink current through the output stage during zero or low load current conditions, and that reliably turns-off the sink current to reduce power consumption and heat generation in the output stage during high load current conditions without requiring a complicated and continuously active control circuit.
The present invention is directed to a self-adjustable current source control circuit for a linear (e.g., a LDO) regulator circuit in which a replica output stage transistor, a reference current source and a negative feedback circuit are arranged to generate a minimum sink current through the regulator's output stage only during zero or low load current conditions, where the negative feedback circuit automatically turns-off the sink current when the load current increases above the minimum sink current, thereby reduce power consumption and heat generation in the output stage during high load current conditions without requiring a complicated and continuously active control circuit.
According to an exemplary embodiment, a circuit system includes a linear regulator circuit that supplies a regulated output voltage to a load circuit connected to its output terminal, where the regulator circuit includes the self-adjustable current source control circuit that draws a minimum sink current from the regulator's output terminal only during zero or low load current conditions. The linear regulator includes a feedback circuit for generating an output stage gate voltage that controls an output stage transistor connected between an unregulated voltage supply and the regulator's output terminal such that the output stage transistor generates the regulated output voltage on the output terminal. The self-adjustable current source control circuit includes a replica output stage that utilizes the output stage gate voltage and a 1:N scale replica transistor of the output stage transistor to generate a replica regulated output voltage at a replica output node, a sink current source for generating a reference current through the replica output node, and negative feedback circuit that includes a pair of negative feedback transistors connected to form a common gate amplifier, where the first negative feedback transistor is connected in a diode-type arrangement between the replica output node and the sink current source, and the second negative feedback transistor is connected between the regulator output terminal and a low voltage source (e.g., ground or 0V). With this arrangement, the second negative feedback transistor is only enabled (turned on) to draw a sink current through the output stage transistor when the load ent falls below a predetermined minimum current level determined by the reference current.
According to an aspect of the present invention, the replica output stage transistor is a 1:N scale replica of the regulator output stage transistor, and the first negative feedback transistor is a 1:N scale replica of the second negative feedback transistor, whereby the second negative feedback transistor is only enabled (turned on) to draw a sink current through the output stage transistor when the load current falls below N times the reference current. Accordingly, by fabricating self-adjustable current source control circuit using a high scale value N, a very low reference current can be used to control the minimum sink current, which minimizes power consumption and heat generation during high load conditions.
According to alternative exemplary embodiments, linear regulators are fabricated using either MOSFET or bipolar transistors.
These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings, where:
The present invention relates to an improvement in linear regulators, and in particular to improvements in low dropout (LDO) regulators. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. The terms “coupled” and “connected”, which are utilized herein, are defined as follows. The term “connected” is used to describe a direct connection between two circuit elements, for example, by way of a metal line formed in accordance with normal integrated circuit fabrication techniques. In contrast, the term “coupled” is used to describe either a direct connection or an indirect connection between two circuit elements. For example, two coupled elements may be directly connected by way of a metal line, or indirectly connected by way of an intervening circuit element (e.g., a capacitor, resistor, inductor, or by way of the source/drain terminals of a transistor). Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
Similar to conventional linear regulators, linear regulator 110 includes circuitry for generating a regulated output voltage VREG on an output terminal 112 to which load circuit 150 is connected (i.e., such that load circuit 150 is connected between regulated output voltage VREG and a low voltage source (e.g., 0V or system ground). In the embodiment shown in
According to an aspect of the present invention, linear regulator 110 also includes a self-adjustable current source control circuit 130 that activates to generate a minimum sink current through output stage transistor 111 only when load circuit 150 is in the low power state in order to satisfy minimal required load current conditions maintaining regulated output voltage VREG, and de-activates during normal operation states in order to prevent unnecessary current consumption heat heat generation. As set forth below self-adjustable sink current source circuit 130 is distinguishable over conventional current source control circuits in that it utilizes a small number (e.g., three) of 1:N scaled transistors, and does not require an externally generated reference signal, whereby the present invention avoids the complicated and large control circuitry utilized in conventional circuits.
Referring to
According to an aspect of the present invention, replica output stage transistor 131 is a 1:N scale replica of output stage transistor 111 that is connected between unregulated voltage supply VUNREG and replica output node 132, and has a gate terminal connected to the output terminal of differential amplifier 113 (i.e., such that both output stage transistor 111 and replica output stage transistor 131 are controlled by output stage gate voltage VG). The phrase “1:N scale replica” is defined herein to mean that replica output stage transistor 131 is fabricated using the same transistor layout pattern and is produced during the same photolithographic processing steps, but has effective width/length ratio that is 1/N times the effective width/length ratio of output stage transistor 111, where N is a real number/integer greater than 1. In the exemplary embodiment shown in
According to another aspect of the present invention, first negative feedback transistor 135 and second negative feedback transistor 137 are connected to form a common gate amplifier that is controlled by sink current source 138. Specifically, the gate and drain terminals of first negative feedback transistor 135 are connected in a diode-type arrangement to sink current source 138, and its source terminal connected to replica output node 132, whereby a reference current IREF generated by sink current source 138 continuously passes from replica output stage transistor 131 and first negative feedback transistor 135, whereby a negative feedback voltage VP generated on a negative feedback node 136 is generated in the manner described in additional detail below. Second negative feedback transistor 137 has a gate terminal connected to negative feedback node 136 (i.e., to sink current source 138), a source terminal connected to regulator output terminal 112, and a drain terminal connected to ground. Feedback transistors 135 and 137 are thus connected to form a common gate amplifier, where negative feedback voltage VP controls the operating states of feedback transistors 135 and 137 in the manner described below such that second negative feedback transistor 137 only turns on when load current ILOAD falls below a predetermined minimum current level determined by reference current IREF.
According to yet another aspect of the present invention, second PMOS transistor 137 is a 1:N scale replica of the first PMOS transistor 135 in order to generate sink current I137 through output stage transistor 111 only when load current ILOAD is zero or below a predetermined minimum current level determined by the scale factor 1:N. In the embodiment shown in
Operation of circuit 100 is described below with reference to
Referring to system 100 (t1) (i.e., system 100 at time t1, shown in
V
REG
=V
G
−V
th111
−I
111
/g
m111 (Eq. 1)
where Vth111 is the threshold voltage of output stage transistor 111 and gm111 is the transconductance of output stage transistor 111. In a similar manner, replica output voltage VREP (which is generated at replica output node 132 between replica output stage transistor 131 and negative feedback transistor 135) is established by Equation 2:
V
REP
=V
G
−V
th131
−I
REF
/g
m131 (Eq. 2)
where Vth131 is the threshold voltage of replica output stage transistor 131, gm131 is the transconductance of replica output stage transistor 131, and IREF is the fixed current drawn by current source 138 through replica transistor 131 and second transistor 135. By rearranging the variables to solve for gate voltage VG, Equation 2 may be rewritten as Equation 2A:
V
G
=V
REP
+V
th131
+I
REF
/g
m131 (Eq. 2A)
Because replica transistor 131 is an 1:N scale replica of output stage transistor 111, their threshold voltages are equal (i.e., Vth131=Vth111). Using this relationship and substituting the value of gate voltage VG from Equation 2A into Equation 1 leads to:
V
REG
=V
REP
−I
111
/g
m111
+I
REF
/g
m131 (Eq. 3)
Negative feedback gate voltage VP, which is the voltage generated at the gate terminals of negative feedback transistors 135 and 137, is established by conventional circuit analysis as follows:
V
P
=V
REP
−V
th135
−I
REF
/g
m135 (Eq. 4)
where Vth135 is the threshold voltage of first negative feedback transistor 135, and gm135 is the transconductance of first negative feedback transistor 135. In a similar manner, regulated output voltage VREG can be expressed as:
V
REG
=V
P
+V
th137
+I
137
/g
m137 (Eq. 5)
where Vth137 and gm135 are the threshold voltage and transconductance of second negative feedback transistor 137, respectively. Because first negative feedback transistor 135 is replica of second negative feedback transistor 137, the threshold voltages of these two transistors are equal (i.e., Vth135=Vth137). Therefore, solving (4) and (5) relative to regulated output voltage VREG leads to:
V
REG
=V
REP
+I
137
/g
m137
−I
REF
/g
135 (Eq. 6)
Equalizing equations 3 and 6 leads to:
I
137
/g
m137
−I
REF
/g
m135
=I
REF
/g
m131
−I
111
/g
m111 (Eq. 7)
As mentioned above, this structure in its operational region forms a negative feedback loop with amplifier 113. Regulated output voltage VREG is always regulated through the feedback network (i.e., resistors 115 and 117 and amplifier 113). Self-adjustable current source control circuit 130 causes output stage current I111 to equal N*I131 by way of negative feedback transistors 135 and 137, which are connected as common gate amplifier, so regulated output voltage VREG equals replica output voltage VREP. Because the current densities through output stage transistor 111 and replica transistor 131 are equal, and their gate voltages are common (i.e., both are equal to gate voltage VG), the transconductances of the two transistors is proportion, i.e.:
g
m131
=g
m111
/N (Eq. 8)
Also, because replica output stage transistor 131 is scaled 1:N to output stage transistor 111 and both receive same gate voltage VG, the gate-source voltage (Vgs) of replica output stage transistor 131 is equal to that of output stage transistor 111. Similarly, because the current densities through negative feedback transistors 135 and 137 are equal, and their gate voltages are common (i.e., both are equal to negative feedback gate voltage VP), the transconductances of the negative feedback transistors 135 and 137 is proportion, i.e.:
g
m135
=g
m137
/N (Eq. 9)
Also, because first negative feedback transistor 135 is scaled 1:N to second negative feedback transistor 137 and both receive same gate voltage VP, the gate-source voltage (Vgs) of first negative feedback transistor 135 is equal to that of second negative feedback transistor 137, which means the current through second negative feedback transistor 137 is equal to N times the current through first negative feedback transistor 135, which is equal to reference current IREF generated by current source 138, or:
I
137
=N*I
135
=N*I
REF (Eq. 10)
Substituting Equations 8, 9 and 10 into Equation 7 provides:
N*I
REF
/g
m131
−N*I
REF
/g
m131
=N*I
REF
/g
m111
−I
111
/g
m111 (Eq. 11)
Subtracting and minimizing the terms in Equation 11 provides:
I
111
=I
137
=N*I
REF (Eq. 12)
That is, during zero/low load current conditions, the output stage current I111 is maintained at N times reference current IREF by way of the sink current drawn through second negative feedback transistor 137.
As set forth above, differential amplifier 113 applies the same gate voltage VG to the gate terminals of output stage transistor 111 and replica transistor 131. When the sum of load current ILOAD and feedback current IFB is lower than N*IREF, self-structure current source control circuit 130 activates (by way gate voltage VG applied to the gate terminal of replica transistor 131) to form a negative feedback network that applies the desired sink current to output terminal 112 (i.e., current I137 through second negative feedback transistor 137), whereby output stage current I111 is approximately equal to sink current I137, which in turn is approximately equal to N*IREF.
As set forth above, self-adjustable current source control circuits of the present invention achieve the ideal functionality (i.e., reliably applying a sink current to the output stage during zero/low load current conditions, and terminating the sink current during high load current conditions) without requiring an externally generated reference signal, thereby avoiding the complicated and large control circuitry utilized in conventional circuits. Further, because the self-adjustable current source control circuits utilize 1:N scaled transistors to determine the amount of sink current consumed during zero/low load current conditions, the amount of sink current drawn through the output stage is reliably set by the 1:N scale factor, whereby the sink current is limited to the current consumed by the negative feedback amplifier. Moreover, the present invention guarantees by its design that the sink current is only drawn during zero/low load currents and shuts off during high load current conditions, thus minimizing power consumption and heat generation.
Although the present invention has been described with respect to certain specific embodiments, it will be clear to those skilled in the art that the inventive features of the present invention are applicable to other embodiments as well, all of which are intended to fall within the scope of the present invention.
