Claims
- 1. An electrically programmable and erasable memory device comprising:
a substrate of semiconductor material having a first conductivity type and a horizontal surface; a trench formed into the surface of the substrate; first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region formed in the substrate therebetween, wherein the first region is formed underneath the trench, and the channel region includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate; an electrically conductive floating gate having at least a lower portion thereof disposed in the trench adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion; and an electrically conductive control gate disposed over and insulated from the channel region second portion for controlling a conductivity of the channel region second portion, wherein there is at most only a partial vertical overlap between the control gate and the floating gate.
- 2. The device of claim 1, further comprising:
a block of conductive material having at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate.
- 3. The device of claim 2, wherein the conductive material block is electrically connected to the first region.
- 4. The device of claim 2, wherein the control gate is disposed adjacent to the floating gate and insulated therefrom with insulation material having a thickness that permits Fowler-Nordheim tunneling.
- 5. The device of claim 2, further comprising:
a spacer of insulating material disposed between the control gate and the block of conductive material, and over the floating gate.
- 6. The device of claim 1, wherein:
the floating gate includes an upper portion that extends above the substrate surface; the control gate has a first portion that is disposed laterally adjacent to and insulated from the floating gate upper portion; and the control gate has a second portion that is disposed over and insulated from the floating gate upper portion.
- 7. The device of claim 6, wherein:
the control gate includes a notch formed by the first and second portions thereof; and the floating gate upper portion includes an edge that faces the notch.
- 8. The device of claim 7, wherein the control gate is a spacer of conductive material.
- 9. The device of claim 1, wherein the floating gate is a spacer of conductive material.
- 10. The device of claim 1, wherein the channel region first and second portions are non-linear with respect to each other, with the channel region second portion extending in a direction directly toward the floating gate to define a path for programming the floating gate.
- 11. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material having a first conductivity type and a surface; spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions; and each of the active regions including a plurality of pairs of memory cells, wherein each of the memory cell pairs comprises:
a trench formed into the surface of the substrate and including a pair of opposing sidewalls, a first region formed in the substrate underneath the trench, a pair of second regions formed in the substrate, with a pair of channel regions each formed in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, and wherein each of the channel regions includes a first portion that extends substantially along one of the opposing trench sidewalls and a second portion that extends substantially along the substrate surface, a pair of electrically conductive floating gates each having at least a lower portion thereof disposed in the trench adjacent to and insulated from one of the channel region first portions for controlling a conductivity of the one channel region first portion, and a pair of electrically conductive control gates each disposed over and insulated from one of the channel region second portions for controlling a conductivity of the one channel region second portion, wherein there is at most only a partial vertical overlap between the control gates and the floating gates.
- 12. The array of claim 11, wherein each of the memory cell pairs further comprises:
a block of conductive material having at least a lower portion thereof disposed in the trench adjacent to and insulated from the pair of floating gates.
- 13. The array of claim 12, wherein each of the conductive material blocks is electrically connected to one of the first regions.
- 14. The array of claim 12, wherein each of the control gates is disposed adjacent to one of the floating gates and insulated therefrom with insulation material having a thickness that permits Fowler-Nordheim tunneling.
- 15. The array of claim 12, wherein each of the memory cell pairs further comprises:
a pair of spacers of insulating material each disposed between the block of conductive material and one of the control gates, and over one of the floating gates.
- 16. The array of claim 11, wherein:
each of the floating gates includes an upper portion that extends above the substrate surface; each of the control gates has a first portion that is disposed laterally adjacent to and insulated from one of the floating gate upper portions; and each of the control gates has a second portion that is disposed over and insulated from one of the floating gate upper portions.
- 17. The array of claim 16, wherein:
each of the control gates includes a notch formed by the first and second portions thereof; and each of the floating gate upper portions includes an edge that faces one of the notches.
- 18. The array of claim 17, wherein each of the control gates is a spacer of conductive material.
- 19. The array of claim 11, wherein each of the floating gates is a spacer of conductive material.
- 20. The array of claim 11, wherein first and second portions for each of the channel regions are non-linear with respect to each other, with each of the channel region second portions extending in a direction directly toward one of the floating gates to define a path for programming the one floating gate.
- 21. The array of claim 11, further comprising:
a plurality of conductive control lines of conductive material each extending across the active and isolation regions in a second direction perpendicular to the first direction and each electrically connecting together one of the control gates from each of the active regions.
- 22. The array of claim 13, further comprising:
a plurality of conductive source lines of conductive material each extending across the active and isolation regions in a second direction perpendicular to the first direction and each electrically connecting together one of the conductive blocks from each of the active regions.
- 23. A method of forming a semiconductor memory cell, comprising:
forming a trench into a surface of a semiconductor substrate, wherein the substrate has a first conductivity type; forming first and second spaced-apart regions of a second conductivity type in the substrate with the first region formed underneath the trench, wherein a channel region is defined in the substrate between the first and second regions such that the channel region includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate; forming an electrically conductive floating gate having at least a lower portion thereof disposed in the trench adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion; and forming an electrically conductive control gate disposed over and insulated from the channel region second portion for controlling a conductivity of the channel region second portion, wherein there is at most only a partial vertical overlap between the control gate and the floating gate.
- 24. The method of claim 23, further comprising:
forming a block of conductive material having at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate.
- 25. The method of claim 24, wherein the formation of the conductive material block includes forming the conductive material block in electrical contact with the first region.
- 26. The method of claim 23, further comprising:
forming insulation material between the control gate and the floating gate with a thickness that permits Fowler-Nordheim tunneling.
- 27. The method of claim 24, further comprising:
forming a spacer of insulating material that is disposed between the control gate and the block of conductive material, and is disposed over the floating gate.
- 28. The method of claim 23, wherein:
the formation of the floating gate includes forming an upper portion of the floating gate that extends above the substrate surface; and the formation of the control gate includes:
forming a first portion of the control gate that is disposed laterally adjacent to and insulated from the floating gate upper portion, and forming a second portion of the control gate that is disposed over and insulated from the floating gate upper portion.
- 29. The method of claim 28, wherein the formation of the control gate includes:
forming a layer of conductive material over the substrate; and performing an anisotropic etch process to remove the layer of conductive material except for a spacer of the conductive material disposed laterally adjacent to and over the floating gate upper portion.
- 30. The method of claim 23, wherein the formation of the floating gate includes:
forming a layer of conductive material over the substrate; and performing an anisotropic etch process to remove the layer of conductive material except for a spacer of the conductive material at least partially disposed in the trench.
- 31. A method of forming an array of electrically programmable and erasable memory devices, comprising:
forming spaced apart isolation regions on a semiconductor substrate that are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, wherein the substrate has a surface and a first conductivity type; and forming a plurality of pairs of memory cells in each of the active regions, wherein the formation of each of the memory cell pairs includes:
forming a trench into the surface of the substrate having a pair of opposing sidewalls, forming a first region in the substrate and underneath the trench, forming a pair of second regions in the substrate, with a pair of channel regions each defined in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, and wherein each of the channel regions includes a first portion that extends substantially along one of the opposing trench sidewalls and a second portion that extends substantially along the surface of the substrate, forming a pair of electrically conductive floating gates each having at least a lower portion thereof disposed in the trench adjacent to and insulated from one of the channel region first portions for controlling a conductivity of the one channel region first portion, and forming a pair of electrically conductive control gates each disposed over and insulated from one of the channel region second portions for controlling a conductivity of the one channel region second portion, wherein there is at most only a partial vertical overlap between the control gates and the floating gates.
- 32. The method of claim 31, wherein the formation of each of the memory cell pairs further comprises:
forming a block of conductive material having at least a lower portion thereof disposed in the trench adjacent to and insulated from the pair of floating gates.
- 33. The method of claim 32, wherein the formation of the conductive material blocks includes forming each of the conductive material blocks in electrical contact with one of the first regions.
- 34. The method of claim 31, further comprising:
forming insulation material between each of the control gates and one of the floating gates with a thickness that permits Fowler-Nordheim tunneling.
- 35. The method of claim 32, further comprising:
forming a plurality of spacers of insulating material, wherein each of the spacers is formed between one of the blocks of conductive material and one of the control gates, and over one of the floating gates.
- 36. The method of claim 31, wherein:
the formation of the floating gates includes forming an upper portion of each of the floating gates that extends above the substrate surface; the formation of the control gates includes:
forming a first portion of each of the control gates that is disposed laterally adjacent to and insulated from one of the floating gate upper portions, and forming a second portion of each of the control gates that is disposed over and insulated from one of the floating gate upper portions.
- 37. The method of claim 31, wherein the formation of the control gates further includes forming a plurality of conductive control lines of conductive material each extending across the active and isolation regions in a second direction perpendicular to the first direction and each electrically connecting together one of the control gates from each of the active regions.
- 38. The method of claim 32, wherein the formation of the conductive material blocks further includes forming a plurality of conductive source lines of conductive material each extending across the active and isolation regions in a second direction perpendicular to the first direction and each electrically connecting together one of the conductive material blocks from each of the active regions.
- 39. The method of claim 31, wherein for each of the memory cell pairs, the formation of the pairs of floating gates in the trench includes:
forming a block of conductive material in the trench; forming a pair of spacers of material over the block of conductive material, wherein the pair of spacers leave a portion of the block of conductive material exposed; performing an etch process that removes the exposed portion of conductive material block and leaves portions of the conductive material block underneath the pair of spacers that constitute the pair of floating gates.
- 40. The method of claim 31, wherein the formation of each of the trenches and one of the memory cell pairs associated therewith includes:
forming a material over the substrate surface; forming an opening in the material; forming a pair of opposing spacers in the opening; forming the trench into the substrate and between the opposing spacers; forming a block of conductive material in the trench, wherein the block of conductive material is insulated from the substrate; removing the spacers to expose a portion of the substrate; removing the exposed portion of the substrate to expand a width of the trench; and forming the pair of floating gates in the expanded trench, wherein each of the floating gates is insulated from the substrate and the block of conductive material.
- 41. The method of claim 36, wherein the formation of the control gates includes:
forming a layer of conductive material over the substrate; and performing an anisotropic etch process to remove the layer of conductive material except for spacers of the conductive material disposed laterally adjacent to and over the floating gate upper portions.
- 42. The method of claim 31, wherein the formation of the floating gates includes:
forming a layer of conductive material over the substrate; and performing an anisotropic etch process to remove the layer of conductive material except for spacers of the conductive material at least partially disposed in the trenches.
- 43. The method of claim 31, wherein the formation of the floating gates includes:
forming a conductive layer of material over the isolation and active regions; forming a layer of insulating material over the isolation and active regions; etching the layer of insulating material using a portion of the conductive layer of material in the active regions as an etch stop; and etching the layer of insulating material using a portion of the conductive layer of material in the isolation regions as an etch stop; wherein the layer of insulating material is removed from the isolation regions, and is removed from active regions except for blocks thereof disposed in the trenches.
Parent Case Info
[0001] This application claims the benefit of U.S. Provisional Application No. 60/370,888, filed Apr. 5, 2002, and entitled High Coupling Non-Volatile Trench Memory Cell; U.S. Provisional Application No. 60/393,696, filed Jul. 2, 2002, and entitled Non-Volatile Memory Trench Cell and Method of Making Same; and U.S. Provisional Application No. 60/398,146, filed Jul. 23, 2002, and entitled Non-Volatile Memory Trench Cell With Buried Floating Gate, all of which are incorporated herein in their entirety by reference.
Provisional Applications (3)
|
Number |
Date |
Country |
|
60370888 |
Apr 2002 |
US |
|
60393696 |
Jul 2002 |
US |
|
60398146 |
Jul 2002 |
US |