Claims
- 1. A method for forming a self-aligned multiple crown storage cell structure for use in a semiconductor memory device, comprising:
- providing a planarized base layer;
- patterning a contact via into the base layer;
- forming a first sacrificial layer on the base layer;
- depositing a first conductive layer onto the patterned via and the first sacrificial layer;
- etching the first conductive layer to expose the first sacrificial layer;
- removing the first sacrificial layer;
- depositing a second conductive layer onto the conductive material-coated patterned via and also on the base layer;
- depositing a second sacrificial layer onto the second conductive layer to fill the via;
- etching the second sacrificial layer to expose portions of the second conductive layer;
- depositing a third conductive layer onto the exposed portions of the second conductive layer and the remaining second sacrificial layer;
- performing an etch of the conductive layer to expose portions of the base layer; and
- removing remaining portions of the second sacrificial layer to form a double crown storage cell structure.
- 2. The method of claim 1, wherein both the first sacrificial layer and the second sacrificial layer comprise an oxide.
- 3. The method of claim 1, wherein the base layer further comprises an etch stop layer.
- 4. The method of claim 1, further comprising:
- depositing a fourth conductive layer onto the conductive material-coated patterned via and the base layer;
- depositing a third sacrificial layer onto the fourth conductive layer;
- etching the third sacrificial to expose portions of the fourth conductive layer;
- depositing a fifth conductive layer onto the exposed portions of the fourth conductive layer and the remaining third sacrificial layer;
- performing an etch to expose the base layer; and
- etching the remaining third sacrificial layer, thereby forming a three crown storage cell structure.
- 5. The method of claim 1, further comprising:
- depositing a fourth conductive layer onto the conductive material-coated patterned via and the base layer;
- depositing a fourth sacrificial layer onto the fourth conductive layer;
- etching the fourth sacrificial layer to expose portions of the fourth conductive layer;
- depositing a fifth conductive layer onto the exposed portions of the fourth conductive layer and the remaining fourth sacrificial layer;
- etching conductive material to expose the base layer; and
- etching the remaining fourth sacrificial layer;
- depositing a sixth conductive layer onto the conductive material-coated patterned via and the etch stop layer;
- depositing a fifth sacrificial layer onto the sixth conductive layer;
- etching the fifth sacrificial layer to expose portions of the sixth conductive layer;
- depositing a seventh conductive layer onto the exposed portions of the sixth conductive layer and the remaining fifth sacrificial layer;
- etching conductive material to expose the base layer; and
- etching the remaining fifth sacrificial layer, thereby forming a four crown storage cell structure.
- 6. The method of claim 1, wherein etching conductive material to expose the base layer further comprises:
- etching the third conductive layer to expose the remaining second sacrificial layer and a portion of the second conductive layer; and
- etching the exposed portion of the second conductive layer to expose the base layer.
- 7. The method of claim 1, wherein the base layer further comprises an insulating layer formed from an oxide and an the etch stop layer comprising Si.sub.3 N.sub.4 deposited onto the insulating layer.
- 8. The method of claim 1, wherein each conductive layer comprises polysilicon deposited using chemical vapor deposition.
- 9. The method of claim 1, wherein the second sacrificial layer comprises SiO.sub.2 deposited using chemical vapor deposition.
- 10. The method of claim 1, further comprising depositing a dielectric onto the storage cell structure and depositing a top plate over the dielectric to form a multiple crown storage capacitor.
Parent Case Info
This is a Non Provisional application filed under 35 USC 119(e) and claims priority of prior provisional, Ser. No. 60/033,722 of inventor Tsu, et al, filed Dec. 20, 1996.
US Referenced Citations (15)
Non-Patent Literature Citations (1)
Entry |
Multilayer Vertical Stakced Capacitors (MVSTC) for 64Mbit and 256Mbit DRAMS, D. Temmler, pp. 13-14. |