Claims
- 1. A clock deskew circuit, comprising:
- a voltage controlled delay module having an input terminal for receiving a cyclic digital input clock signal that has first type edges and second type edges, a first control terminal for receiving a first control signal and a second control terminal for receiving a second control signal, and a delay means which propagates said input clock signal from said input terminal to an output terminal such that a) said first type signal edges are delayed between said input and output terminals with a first delay which is variable in a continuous fashion by the magnitude of said first control signal and b) said second type signal edges are delayed between said input and output terminals with a second delay which is variable in a continuous fashion independent of said first delay by the magnitude of said second control signal;
- a control module having a feedback lead which is coupled to receive the delayed clock signal from said output terminal of said delay module, and having another lead which is coupled to receive said input clock signal;
- said control module further including a first control signal generating means which sends said first control signal to said first control terminal of said delay module with a magnitude that increases said first delay when the delayed clock edges of said first type lag the corresponding input clock edges by less than one clock cycle, and vice versa; and,
- said control module also including a second control signal generating means which generates said second control signal with a magnitude that is not determined by the magnitude of said first control signal and vice-versa.
- 2. A clock deskew circuit according to claim 1 wherein said first type signal edges are rising signal edges and said second type signal edges are falling signal edges.
- 3. A clock deskew circuit according to claim 1 wherein said first type signal edges are falling signal edges and said second type signal edges are rising signal edges.
- 4. A clock deskew circuit according to claim 1 wherein said first control signal generating means generates said first control signal with an amplitude that decreases when rising clock edges from said output terminal lag corresponding edges on said input terminal by less than one clock cycle, and vice versa; and said second control signal generating means generates said second control signal with a fixed amplitude.
- 5. A clock deskew circuit according to claim 1 wherein said first control signal generating means generates said first control signal with an amplitude that decreases when rising clock edges from said output terminal lag corresponding edges on said input terminal by less than one clock cycle, and vice versa; and said second control signal generating means generates said second control signal with an amplitude that increases when falling clock edges from said output terminal lag corresponding edges on said input terminal by less than one clock cycle, and vice versa.
- 6. A clock deskew circuit according to claim 1 wherein said first control signal generating means generates said first control signal with an amplitude that decreases when rising clock edges from said output terminal lag corresponding edges on said input terminal by less than one clock cycle, and vice versa; and said second control signal generating means generates said second control signal with an amplitude that increases when falling clock edges from said output terminal follow preceding rising clock edges by less than one-half clock cycle, and vice versa.
- 7. A clock deskew circuit according to claim 1 wherein said first control signal generating means includes a first capacitor and a first plurality of serially connected transistors which generate said first control signal by charging and discharging said first capacitor, and said second control signal generating means includes a second capacitor and a second plurality of serially connected transistors which generate said second control signal by charging and discharging said second capacitor.
- 8. A clock deskew circuit according to claim 1 wherein said delay means includes a plurality of serially coupled stages with each stage including means for delaying said rising clock signal edges and falling clock signal edges independently in response to said first control signal and said second control signal respectively.
- 9. A clock deskew circuit according to claim 8 wherein in each stage said means for delaying includes a capacitor, and transistors which charge said capacitor at a rate which is inversely proportional to the magnitude of said second control signal and which discharge said capacitor at a rate which is proportional to the magnitude of said first control signal.
- 10. A clock deskew circuit according to claim 1 wherein said delay module and said control modules are integrated circuits on a single semiconductor chip.
Parent Case Info
This is a continuation of application Ser. No. 07/785,895 filed on Oct. 30, 1991, now abandoned, which is a continuation of application Ser. No. 07/504,776 filed on Apr. 4, 1990, now abandoned.
US Referenced Citations (17)
Non-Patent Literature Citations (1)
Entry |
Nilsson; "Electric Circuits"; 1983; p. 153. |
Continuations (2)
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Number |
Date |
Country |
Parent |
785895 |
Oct 1991 |
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Parent |
504776 |
Apr 1990 |
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