The present invention relates to self-oscillating amplifiers or modulators.
Self-oscillating pulse width modulation (PWM) amplifiers, e.g. for audio applications, are generally recognised as advantageous over common PWM amplifiers that modulates the input signal by means of a triangle or saw tooth reference signal, as they provide for a significant better error attenuation, e.g. easily more than 20 dB better error attenuation at 20 kHz.
Known self-oscillating PWM amplifiers do, however, also suffer from a disadvantage, as their switch frequency fluctuates with the level of the input signal. The switch frequency decreases with increasing input level, and may typically be halved at input signals at 80% of maximum level. Among other things, this problem complicates operating more amplifiers simultaneously, e.g. in a multi-channel application, due to cross-talk, and moreover, it also increases problems with cross-talk to other system components such as, e.g., converters, phase-locked-loops, tuners, etc.
In the past, this problem has been addressed by injecting a relatively small, periodic, typically triangular, reference signal into the loop, whereby the oscillation tends to lock to the frequency of the reference signal, within certain limits. The amplitude of the reference signal compared to the maximum input signal level determines how firmly the switch frequency locks, and a triangular reference signal of, e.g. 15% of the maximum input signal level, stabilises the switch frequency significantly for input signals of up to 70%-80% of maximum, whereas it is still not able to maintain the switch frequency for larger input signals. Reference signals of larger amplitudes may be able to reduce the fluctuation for larger input levels, but will also reduce the advantages of self-oscillation significantly, and result in an overall performance corresponding to non-self-oscillating, reference signal driven PWM amplifiers.
A further problem for known self-oscillating PWM amplifiers is that very large input signals close to 100% maximum level may cause PWM pulses that do not satisfy the minimum pulse widths required by the power output stage in order to avoid distortion, and ensure that a pulse is present for each switch period. As a self-oscillating loop is driven by the pulses inherent in the signal, the oscillation stops when the duty cycle becomes 0% or 100%, as no level shifts occur at such duty cycles. Because of the minimum pulse width requirements of the output stage, caused by the rise- and fall-time of the power switches, which are typically somewhat slower than the low-voltage processing means establishing the pulses, the problem with missing level shifts may in fact occur also for duty cycles close to 0% or 100% of maximum level, e.g. for duty cycles below 4% or above 96%, which may correspond to, e.g., an input signal level above 92% of maximum.
It is an object of the present invention to provide a self-oscillating modulator that features improved switch frequency locking for large input signals.
It is an object of the present invention to provide a self-oscillating modulator that ensures observance of the minimum pulse width requirements.
It is an object of the present invention to provide a self-oscillating modulator or amplifier with improved handling of large input signals, e.g. less cross-talk and less distortion.
The invention relates to a self-oscillating modulator 2 comprising a PWM cycle constrainer 21.
According to the present invention, an advantageous self-oscillating modulator, e.g. an audio amplifier, may be provided, which features improved switch frequency locking also for input utility signals with high levels, i.e. frequency locking in an increased dynamic range compared to known frequency locking methods described above.
Moreover, according to the present invention, an advantageous self-oscillating modulator may be provided, which ensures compliance with the minimum duty cycle requirements typically introduced by power output stages with slower switching capabilities than offered by the modulation circuitry or processing means.
In a preferred embodiment, both objects are fulfilled and hence, a self-oscillating modulator that ensures a stable and synchronised oscillation and thereby, among other things, reduced cross-talk effects, and at the same time guarantees a minimum pulse width to be realised by the output stage, and thereby reduces distortion, is provided according to the invention.
When said PWM cycle constrainer 21 is arranged for establishing switch frequency synchronisation in an increased dynamic range of said self-oscillating modulator, an advantageous embodiment of the present invention has been obtained.
According to the present invention, it is ensured that the pulse width modulated signal supplied to a switching power output stage comprises at least one pulse or level shift in each PWM period, i.e. each period of the switch frequency of the self-oscillating modulator, even when the input utility signal has a high level compared to its maximum possible level. The guarantee of at least one shift in each period causes the switch frequency to stabilise, and thereby avoids frequency fluctuation and momentary oscillation pauses, which again avoids or reduces cross-talk problems.
When said PWM cycle constrainer 21 is arranged for ensuring that a pulse width modulated signal 18 of said self-oscillating modulator 2 comprises a pulse of at least a predetermined minimum width in each switch period, an advantageous embodiment of the present invention has been obtained.
According to the present invention, it is ensured that the pulse width modulated signal supplied to a switching power output stage never comprises pulses narrower than a predetermined pulse width. Thereby distortion due to the power switches not being able to realise very narrow pulses because of their relative long rise- and fall-times is avoided.
When said PWM cycle constrainer 21 is arranged for ensuring that a pulse width modulated signal 18 of said self-oscillating modulator 2 comprises a pulse of less than or equal to a predetermined maximum width in each switch period, an advantageous embodiment of the present invention has been obtained.
When said PWM cycle constrainer 21 is arranged for ensuring that said pulse in each switch period is in synchrony with the oscillation of said self-oscillating modulator, an advantageous embodiment of the present invention has been obtained.
When said PWM cycle constrainer 21 comprises a PWM cycle constraint generator 23 arranged for establishing at least one PWM cycle constraint representative signal 26; 32, 33, an advantageous embodiment of the present invention has been obtained.
When said PWM cycle constraint representative signal 26; 32, 33 is applied to a pulse width modulated signal 18 within said self-oscillating modulator 2 by means of a limit pattern logic 24.
When said PWM cycle constraint representative signal 26; 32, 33 is a pulse width modulated signal, an advantageous embodiment of the present invention has been obtained.
When said PWM cycle constraint representative signal 26; 32, 33 comprises a maximum duty cycle representative signal 32 and a minimum duty cycle representative signal 33, an advantageous embodiment of the present invention has been obtained.
When said maximum duty cycle signal 32 comprises at least one pulse per switch period of said self-oscillating modulator 2, and wherein the duty cycle of said maximum duty cycle signal 32 is in the range of 90% to 99%, preferably substantially 96%, an advantageous embodiment of the present invention has been obtained.
A predetermined minimum pulse width that suits a typical switching power output stage, may, e.g., be 100 ns. In a self-oscillating amplifier with a switch frequency of, e.g., 400 kHz, this minimum pulse width corresponds to 4% or 96% duty cycle, as one switch period last for 2500 ns. It is noted, however, that the principles of the present invention applies to any self-oscillating modulators running at any suitable switch frequencies, and supplies any suitable power output stages or other kinds of subsequent processing blocks, having any minimum pulse width requirements. In such alternative embodiments, the maximum and minimum duty cycle signals should be designed according to the principles described herein, and on the basis of the desired or needed switch frequency and the actual minimum pulse width requirements.
When said duty cycle of said maximum duty cycle signal 32 corresponds to one full switch period of said self-oscillating modulator 2 subtracted by an amount of time in the range of 50 ns to 200 ns, preferably 100 ns, an advantageous embodiment of the present invention has been obtained.
When said minimum duty cycle signal 33 comprises at least one pulse per switch period of said self-oscillating modulator 2, and wherein the duty cycle of said minimum duty cycle signal 33 is in the range of 1% to 10%, preferably substantially 4%, an advantageous embodiment of the present invention has been obtained.
When said pulse length of said minimum duty cycle signal 33 is in the range of 50 ns to 200 ns, preferably 100 ns, an advantageous embodiment of the present invention has been obtained.
When the low part of said pulse per switch period of said maximum duty cycle signal 32 is located in the beginning of each switch period, an advantageous embodiment of the present invention has been obtained.
When the low part of said pulse per switch period of said maximum duty cycle signal 32 is located in the end of each switch period, an advantageous embodiment of the present invention has been obtained.
When the low part of said pulse per switch period of said maximum duty cycle signal 32 is located so that the middle in terms of time of said low part is located substantially at the shift between two switch periods, an advantageous embodiment of the present invention has been obtained.
When the high part of said pulse per switch period of said minimum duty cycle signal 33 is located so that it starts at the middle of each switch period, an advantageous embodiment of the present invention has been obtained.
When the high part of said pulse per switch period of said minimum duty cycle signal 33 is located so that it ends at the middle of each switch period, an advantageous embodiment of the present invention has been obtained.
When the high part of said pulse per switch period of said minimum duty cycle signal 33 is located so that the middle in terms of time of said high part is located substantially at the middle of each switch period, an advantageous embodiment of the present invention has been obtained.
When said locating said pulses of said PWM cycle constraint representative signal 26; 32, 33 is controlled at least partly by a delay in a feedback path of said PWM cycle constraint generator 23, an advantageous embodiment of the present invention has been obtained.
When said limit pattern logic 24 applies said PWM cycle constraint representative signal 26; 32, 33 to said pulse width modulated signal 18 by means of logic operations, an advantageous embodiment of the present invention has been obtained.
When said logic operations comprise applying said maximum duty cycle signal 32 to said pulse width modulated signal 18 by means of an AND operation, and applying said minimum duty cycle signal 33 to said pulse width modulated signal 18 by means of an OR operation, an advantageous embodiment of the present invention has been obtained.
When said PWM cycle constraint generator 23 establishes said PWM cycle constraint signal 26; 32, 33 on the basis of a periodic signal 17; 25; 31, an advantageous embodiment of the present invention has been obtained.
When said periodic signal 17; 25; 31 is in synchrony with the oscillation of said self-oscillating modulator 2, an advantageous embodiment of the present invention has been obtained.
When said periodic signal 17; 25; 31 is a triangle signal, a sawtooth signal, a square wave signal or another signal having a distinct amplitude-time relationship, an advantageous embodiment of the present invention has been obtained.
When said PWM cycle constraint generator 23 establishes said PWM cycle constraint representative signal 26; 32, 33 on the basis of a square wave signal 31 established on the basis of said periodic signal 17, an advantageous embodiment of the present invention has been obtained.
When a synchronization signal 17 is further added to the input signal 3 of said self-oscillating modulator 2, or applied within the loop of the self-oscillating modulator, an advantageous embodiment of the present invention has been obtained.
When said synchronization signal 17 is applied within the loop of the self-oscillating modulator 2 by providing it as reference signal to a modulator 12 of said self-oscillating modulator 2, an advantageous embodiment of the present invention has been obtained.
When said synchronization signal 17 comprises a representation of said periodic signal 17, an advantageous embodiment of the present invention has been obtained.
When said periodic signal 17 is established by means of a self-oscillating loop 22, an advantageous embodiment of the present invention has been obtained.
The self-oscillating loop 22 is also referred to as periodic signal generator 22 or reference signal generator 22 elsewhere in this application.
When said periodic signal 17 is variable, and is controlled at least partly on the basis of the level of said input signal 3 of said self-oscillating modulator 2, an advantageous embodiment of the present invention has been obtained.
When said self-oscillating modulator 2 comprises a controller 11, an advantageous embodiment of the present invention has been obtained.
When said controller 11 comprises a loop filter arranged for at least partly controlling the oscillation of said self-oscillating modulator 2, an advantageous embodiment of the present invention has been obtained.
When said controller 11 comprises at least one integrator, an advantageous embodiment of the present invention has been obtained.
When said self-oscillating modulator 2 comprises a power output stage 13, an advantageous embodiment of the present invention has been obtained.
When said self-oscillating modulator 2 comprises an output filter 14, an advantageous embodiment of the present invention has been obtained.
When said self-oscillating modulator 2 comprises a feedback path 16 from the output of said power output stage 13 to said controller 11, an advantageous embodiment of the present invention has been obtained.
When said self-oscillating modulator 2 comprises a feedback path from the output of said output filter 14 to said controller 11, an advantageous embodiment of the present invention has been obtained.
When said self-oscillating modulator is arranged for establishing a pulse width modulated signal 18 on the basis of an input signal 3, and wherein said self-oscillating modulator comprises
When said self-oscillating modulator comprises a power output stage 13, an advantageous embodiment of the present invention has been obtained.
When said self-oscillating modulator further comprises a reference signal generator 22 arranged for establishing a periodic reference signal 17; 25; 31, an advantageous embodiment of the present invention has been obtained.
When said PWM cycle constraint representative signals 26; 32, 33 are in synchronization with the switch frequency of said self-oscillating modulator 2, an advantageous embodiment of the present invention has been obtained.
The present invention further relates to a method of stabilising the switch frequency of a self-oscillating modulator operating on a high level input signal, whereby at least one PWM cycle constraint representative signal 26; 32, 33 is applied to a pulse width modulated signal 18 within said self-oscillating modulator 2.
When said application of said PWM cycle constraint representative signal 26; 32, 33 to said pulse width modulated signal 18 ensures that said pulse width modulated signal comprises at least one pulse for each switch period, an advantageous embodiment of the present invention has been obtained.
When said at least one PWM cycle constraint representative signal 26; 32, 33 comprises a maximum duty cycle signal 32 that is applied to said pulse width modulated signal 18 by means of an AND operation, and a minimum duty cycle signal 33 that is applied to said pulse width modulated signal 18 by means of an OR operation, an advantageous embodiment of the present invention has been obtained.
When said self-oscillating modulator 2 comprises a self-oscillating modulator according to any of the above described, an advantageous embodiment of the present invention has been obtained.
The present invention further relates to a method of avoiding pulses narrower than a predetermined minimum pulse width or wider than a predetermined maximum pulse width in a self-oscillating modulator 2 operating on a high level input signal, whereby at least one PWM cycle constraint representative signal 26; 32, 33 is applied to a pulse width modulated signal 18 within said self-oscillating modulator.
When said at least one PWM cycle constraint representative signal 26; 32, 33 comprises a maximum duty cycle signal 32 that is applied to said pulse width modulated signal 18 by means of an AND operation, and a minimum duty cycle signal 33 that is applied to said pulse width modulated signal 18 by means of an OR operation, an advantageous embodiment of the present invention has been obtained.
When said maximum duty cycle signal 32 for each switch period of said self-oscillating modulator 2 comprises a low part that is wider than or equal to said predetermined minimum pulse width, and whereby said minimum duty cycle signal 33 for each switch period of said self-oscillating modulator 2 comprises a high part that is wider than or equal to said predetermined minimum pulse width, an advantageous embodiment of the present invention has been obtained.
When said self-oscillating modulator 2 comprises a self-oscillating modulator according to any of the above-described, an advantageous embodiment of the present invention has been obtained.
The present invention further relates to a method of providing at least one PWM cycle constraint representative signal 26; 32, 33 for use in a self-oscillating modulator, whereby said PWM cycle constraint representative signal is established by the steps of:
When said reference signal generator 22 comprises a self-oscillating loop with a hysteresis comparator, an advantageous embodiment of the present invention has been obtained.
When said hysteresis comparator has its reference input coupled to ground, an advantageous embodiment of the present invention has been obtained.
When said hysteresis comparator has its reference input coupled to a synchronization signal source, an advantageous embodiment of the present invention has been obtained.
When said providing said PWM cycle constraint representative signal 26; 32, 33 comprises providing a maximum duty cycle signal 32 which for each period of said periodic signal 17; 25; 31 comprises a low part that is wider than or equal to a predetermined minimum pulse width, and further providing a minimum duty cycle signal 33 which for each period of said periodic signal 17; 25; 31 comprises a high part that is wider than or equal to a predetermined minimum pulse width, an advantageous embodiment of the present invention has been obtained.
When said PWM cycle constraint representative signal 26; 32, 33 is used in a self-oscillating modulator 2 according to any of the above-described, an advantageous embodiment of the present invention has been obtained.
The invention will in the following be described with reference to the drawings where
The theory and principles behind self-oscillating modulators and amplifiers, as well as examples of embodiments suitable for use with the present invention, are described in more detail in the prior art, for example in the published, international patent applications WO 2005/002050 A1, WO 2005/029707 A1 and WO 2005/029708 A1, hereby incorporated by reference.
Instead of coupling the reference input of the modulator 12 to ground or a DC value as in a simple, self-oscillating amplifier, a periodic signal generator 15 is provided for establishing a periodic signal 17 that is coupled to the reference input of the comparator of the modulator 12. The periodic signal may, e.g., have a level of 15% of maximum input signal level, and should have a frequency corresponding to the switch frequency of the self-oscillating modulator.
As described above, a self-oscillating amplifier as shown in
The principles behind partially controlling the switch frequency by means of a periodic signal 17, preferably a triangle signal, and different examples of how and where to inject such a signal into the self-oscillating loop, as well as examples of signal types, may, e.g., be found in the published, international patent applications WO 2005/029707 A1, WO 2005/029708 A1, WO 2005/036734 A1 (in particular the parts about the compensation means) and WO 2005/036735 A1 (in particular the parts about the compensation means), hereby incorporated by reference.
In an alternative embodiment, the periodic signal generator 22 is substituted for an external periodic signal generator or source, or it is controlled by an externally generated signal, e.g. a clock signal established elsewhere in the system. In such embodiments the externally provided periodic signal may be used directly for periodic signals 17 and/or 25, or the periodic signal generator 22 may comprise circuitry for deriving suitable periodic signals 17 and/or 25 from the externally provided signal.
The second wave form is a periodic signal 31 indicated in
The third wave form 32 is the maximum duty cycle signal 32 of
The fourth wave form 33 is the minimum duty cycle signal 33 of
Hence, by AND'ing the maximum duty cycle signal 32 to the pulse modulated signal 18, and OR'ing the minimum duty cycle signal 33 to the output of the AND'ing, it is ensured that there will be at least one level shift in each switch period, thereby supporting self-oscillation which requires the signal itself to oscillate, and thereby supporting stabilisation of the switch frequency, even at high level input signals, and at the same time it is ensured that no un-realisably short pulses are provided to the output stage for realising.
The error introduced by the non-linear limiting performed by the limit pattern logic 24 according to the present invention, is attenuated effectively because of the feedback and advantageous error attenuation of self-oscillating loops.
In a preferred embodiment, the pulses of the maximum and minimum duty cycle signals may be located at earlier time positions by means of a small delay in the feedback path from the square wave signal 31 to the input of the integrator in the periodic signal generator 22. Thereby the middle of the narrow pulses may be positioned at the triangle corners instead of starting at the corners, and thereby a more symmetric control signal is established.
In a preferred embodiment of the present invention, the periodic signal generator is further controlled by an external synchronization signal, which may, e.g., be fed to the comparator of the generator 22.
In a preferred embodiment of the present invention, the periodic signal generator may further be controlled by the input signal 3, in order to make the periodic signal generator depending on the input signal level. Thereby further possibilities of controlling the switch frequency on the basis of the input signal level is provided. Examples of such an input signal level controlled signal generator may, e.g., be found in the published, international patent application WO 2005/117253 A1 (in particular the parts about the level controlled generator), hereby incorporated by reference.
In a preferred embodiment of the present invention, the self-oscillating amplifier may comprise an additional feedback path from the output of the output filter 14 to the controller 11.
Number | Date | Country | Kind |
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PA 2006 00957 | Jul 2006 | DK | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/DK07/50091 | 7/11/2007 | WO | 00 | 1/12/2009 |