Patent Grant
11078073
The invention generally concerns a self-processing synthesis of hybrid nanostructures, novel nanostructures and uses thereof.
Nanometer-scale systems play central roles in numerous fields related to material science and are applied in various ways due to their unique chemical and physical properties. Accordingly, the controlled synthesis of building blocks featuring nanometer-scale structural motifs has resulted in much technological interest and research.
The construction of nanometer-scale components mainly relies on two complementary approaches: top-down techniques and bottom-up synthesis. Typically, top-down techniques involve a pre-defined processing sequence with an explicit blueprint of patterns and processing steps, which are applied to a macroscopic substrate and result in the desired structure, dimensions and composition [1]. In contrast, bottom-up synthesis mainly relies on the meticulous design of physical and chemical interactions among different components, such as molecules and particles that undergo assembly or self-assembly processes and yield more complex structures [2]. In bottom-up synthesis, the information required for the assembly process is embedded in the system components by designing their physical interactions and chemical reactivity. Each of these approaches has advantages and disadvantages. For example, multi-step processing, high reproducibility, and ease of design are hallmarks of top-down fabrication, and bottom-up synthesis is better for parallel processing, diversity, and scalability.
Bottom-up and top-down approaches are often used to construct nanosystems that are comprised of two or more components with distinct chemical compositions, structural domains and physical properties, which are commonly referred to as hybrid nanostructures (HNS) [3-7]. Overall, HNS are central for designing novel materials with desired optical, mechanical, and electronic properties at the nanometer scale by introducing architectures with programmed compositions and heterogeneous shapes. It is important to combine several materials and morphologies within the same nanostructure to attain new and synergistic functionalities because properties at the nanoscale depend on the composition, size, and dimensionality of the nanostructures [4]. Such structures can be prepared using a large spectrum of approaches, including template-assisted synthesis, colloid surface chemistry, and protein assembly [8-12].
However, these approaches often suffer from limited and generally complex control over the synthesis parameters of various system materials; thus, their synthesis development is typically time and cost intensive.
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[2] Koch, C. C. Nanostructured Materials Processing, Properties, and Applications. (William Andrew Pub., Norwich, N.Y., 2007).
[3] Cölfen, H. & Mann, S. Higher-order organization by mesoscale self-assembly andtransformation of hybrid nanostructures. Angew. Chem. Int. Ed. Engl. 42, 2350-2365 (2003).
[4] Costi, R., Saunders, A. E. & Banin, U. Colloidal hybrid nanostructures: a new type of functional materials. Angew. Chem. Int. Ed. Engl. 49, 4878-4897 (2010).
[5] Reddy, A. L. M., Gowda, S. R., Shaijumon, M. M. & Ajayan, P. M. Hybrid nanostructures for energy storage applications. Adv. Mater. 24, 5045-5064 (2012).
[6] Walther, A. & Müller, A. H. E. Janus particles: synthesis, self-assembly, physical properties, and applications. Chem. Rev. 113, 5194-5261 (2013).
[7] Loget, G. & Kuhn, A. Bulk synthesis of janus objects and asymmetric patchy particles. J. Mater. Chem. 22, 15457-15474 (2012).
[8] Zeeshan, M. A. et al. Structural and magnetic characterization of batch-fabricated nickel encapsulated multi-walled carbon nanotubes. Nanotechnology 22, 275713 (2011).
[9] Jia, G. et al. Couples of colloidal semiconductor nanorods formed by self-limited assembly. Nat. Mater. 13, 301-307 (2014).
[10] Kurppa, K. et al. Controlled hybrid nanostructures through protein-mediated noncovalent functionalization of carbon nanotubes. Angew. Chemie 119, 6566-6569 (2007).
[11] Fischer, V., Lieberwirth, I., Jakob, G., Landfester, K. & Muñoz-Espí, R. Metal oxide/polymer hybrid nanoparticles with versatile functionality prepared by controlled surface crystallization. Adv. Funct. Mater. 23, 451-466 (2013).
[12] Xu, C. et al. Controlled soft-template synthesis of ultrathin C@FeS nanosheets with high-Li-storage performance ACS Nano 6, 4713-4721 (2012).
[13] Mokari T. Synthesis and characterization of hybrid nanostructures. NanoReviews 2, 5983 (2011).
To address the disadvantages of processes of the art, the inventors of the technology disclosed herein have developed a novel synthetic method for attaining hybrid nanostructures (HNS) of metals and semiconductor materials. The methodology of the present invention, herein referred to as “self-processing synthesis”, SP, can be used to synthesize a variety of HNSs in one step by triggering a programmable cascade of events that is executed autonomously, without needing external stimulus or multi-step manipulations. The structures are formed using a self-propagating sequence that unlike other hybrid systems such as those described, for example in [13], involves etching, deposition, modification and self-termination of the transformations, all in one continuous wet process. The self-processing synthesis does not involve nor requires isolation, purification and identification of intermediate structures, rather proceeds in a continuous manner that nevertheless may be pre-defined and controllable.
The synthetic strategy takes advantage of the inherent asymmetry exhibited by a metal-semiconductor junction, such as that present in nanowires prepared by metal-catalyzed chemical vapor deposition (CVD) methods. Where nanowires are concenrned, the metal-semiconductor junction is used for activating the self-processing to a localized region at the tip area using a wet-chemistry approach. The hybrid nanostructures obtained for metals such as the coinage metals: Cu, Ag, and Au, resemble the morphology of grass flowers. Thus, structures formed according to the SP synthesis are termed herein “nano floret” (NF) hybrid nanostructures. These nanostructures consist of a high aspect ratio nanowire (NW) with a metallic nanoshell cap.
However, the novel and generic approach may be utilized not only in the construction of nanowire hybrid nanostructures but also in the construction of, e.g., 2-dimensional and planar 3-dimensional nanostructures.
As the results provided herein indicate, the SP synthesis involves distinct processing steps including localized oxide etch around a metal-semiconductor junction, metal deposition, and process termination, resulting in growth of a metallic region onto and surrounding the metal-semiconductor junction. The mechanism of the process of the invention was demonstrated in the synthesis of an exemplary Au-nano-floret (Au—NF) hybrid nanostructure, based on SiGe alloy nanowires (SiGe NWs). Despite the fact that Au—SiGe NWs were used, growth of a metallic region of a metal different from Au was made possible, onto and surrounding the Au-SiGe junction.
The process is initiated by mild etching of an oxide layer which may be a native oxide on the semiconductor material or an oxide layer intentionally formed thereon, using an etchant such as water, that removes a region of the oxide layer at the metal (e.g., Au)-semiconductor junction or vicinity thereof. Catalytic metal deposition occurs at the metal (e.g., Au) catalyst edge, and metal deposition subsequently occurs at the exposed semiconductor surface, namely at the etched region. Without wising to be bound by theory, the semiconductor oxide layer is locally removed in the presence of the etchant, e.g., water, by metal-assisted chemical etching due to the semiconductor-metal junction that is present. Galvanic redox reactions at the exposed semiconductor region result in metal cation reduction and nucleation. Metal clusters grow at the metal nuclei, assisted by the catalytic redox reactions driven by a reducing agent. The process stops when the exposed semiconductor region is completely covered with a metal layer, probably involving surface poisoning with metal—H species at the anaerobic conditions employed in the synthesis, resulting in a self-limiting process.
Thus, the process is triggered or initiated by removal of a oxide material at the vicinity of the metal-semiconductor junction, evolving a programmable cascade of events that result in the controllable growth of a metallic region around the metal-semiconductor junction. The metal grown on said junction may or may not be the same as the metal of the metal-semiconductor junction.
In a first aspect, the invention provides a process for patterning a semiconductor material at a metal-semiconductor interface, a region of said interface having a layer of a semiconductor oxide (namely an oxide which is formed on the semiconductor material, not necessarily an oxide of an atom of the semiconductor material), the process comprising patterning said region of a semiconductor oxide with a processing solution comprising at least one etchant and at least one metal source, and causing deposition of at least one metal from said at least one metal source at said patterned region.
In some embodiments, the oxide formed on the semiconductor material is an oxide of at least one metal atom which is not an atom of the semiconductor material. IN such cases, the oxide film or layer of at least one metal is intentionally formed as a protective layer on top of the semiconductor material for the purpose of protecting the semiconductor material or for the purpose of enabling patterning steps according to the invention.
In some embodiments, the at least one etchant is selected to cause exposure of the semiconductor material (namely removal of the oxide material, as defined) to deposition thereonto of said at least one metal.
In some embodiments, the processing solution comprises at least one etchant, at least one metal source and optionally at least one reducing agent.
In some embodiments, the oxide present on the semiconductor material may be a native oxide layer or an oxide of the semiconductor material which is intentionally formed (synthetically derived) on the semiconductor surface. As used herein, the term “patterning” refers to forming an oxide-free region(s) on the semiconductor material. In other words, the process of the invention permits selective removal of an oxide material from the semiconductor surface, yielding an oxide-free semiconductor material onto which metal deposition can take place; thus permitting patterning or decorating of the semiconductor region (from which oxide material has been removed, or etched) with the metal.
The invention further provides a process for forming a metal region at a metal-semiconductor junction, the process comprising causing material removal (etching, patterning) from a region of an oxide layer present at the vicinity of the metal-semiconductor junction, to thereby expose a region of an underlining semiconductor surface, and subsequent metal cluster growth at the semiconductor surface and/or at the metal semiconductor interface.
The invention further provides a bottom-up process for forming a metal region on a semiconductor surface, the process comprising selective metal deposition at a metal-semiconductor interface under reductive conditions.
The invention further provides a process for forming a metal region at a metal-semiconductor junction, the process comprising
The invention further provides a process comprising contacting a semiconductor material comprising at least one metal-semiconductor junction of a first metal and a semiconductor material, the junction being surrounded by an oxide layer of said semiconductor material, with at least one metal source of a second metal (i.e., of a metal which may or may not be the same as the metal of the metal-semiconductor junction), at least one reducing agent and at least one etchant, e.g., water, under conditions permitting etching of at least a region of said native oxide and surface deposition of the second metal at said etched region.
The invention further provides a self-processing method for forming a metallic region at a metal-semiconductor junction present on a substrate, the method comprising contacting said substrate with at least one metal source (i.e., of a metal which may or may not be the same as the metal of the metal-semiconductor junction), at least one reducing agent and water, under conditions permitting autonomous etching of at least a region of an oxide layer present at the vicinity of the junction and surface deposition of a metal at said etched region.
The “metal-semiconductor junction” is a region on the semiconductor material surface which is in direct contact with a metal. The junction may be in the form of a single metal region on the surface of the semiconductor material or may in the form of a plurality of such regions. Thus, the metallic regions may be considered as decorating a semiconductor surface, in a random or predefined form, size and density. The form and size of the metal region on the semiconductor material surface may vary based on the type of the device and the intended purpose.
Where the semiconductor surface is flat or substantially two-dimensional, the metal region forming the metal-semiconductor junction may be a single region on the flat surface or multiple spaced apart regions, which density on the surface may be homogenous, inhomogeneous, predefined or random. Where the semiconductor surface is a three-dimensional surface, the junction may be formed at any region of the three-dimensional structure. In some embodiments, the semiconductor is in the form of an elongated or star-like three-dimensional structure and the metal junction is present on one or more ends (or tips or edges) of said elongated or star-like structure.
The metal-semiconductor junction may be formed by any one method known in the art. Such may include molecular beam epitaxy (MBE), pulsed laser deposition (PLD), thermal evaporation, electron-beam evaporation, atomic layer deposition (ALD), and chemical vapor deposition (CVD).
The metal of the metal-semiconductor junction may be any metal provided that at the metal-semiconductor interface local changes in the electronic structure are formed that is then used for local changes in reactivity. In some embodiments, the metal of the metal-semiconductor junction is selected amongst transition metals selected from Groups IIIB, IVB, VB, VIB, VIIB, VIIIB, IB and IIB of block d the Periodic Table, as further defined hereinbelow. In some embodiments, the metal is gold.
Irrespective of the metal of the junction, the process of the invention permits growth of a metal region of a metal different from the metal of the junction onto and/or at the vicinity of the junction. In some embodiments, the metal region comprises or consists a metal which is the same as the metal of the junction. In other embodiments, the metal region comprises or consists a metal which is different from the metal of the junction.
The metal grown onto or at the vicinity of the junction is obtained from at least one metal source which is contacted with the semiconductor junction. When the semiconductor native oxide layer is locally removed in the presence of the etchant, by metal-assisted chemical etching, galvanic redox reactions at the exposed semiconductor region result in metal cation reduction and nucleation. Metal clusters grow at the nuclei assisted by the catalytic redox reactions driven by the reducing agent. Thus, the metal is first produced by reduction of the metal source by the exposed semiconductor material and assisted by the reducing agent. As such, the metal and metal source may be selected irrespective of the metal of the metal-semiconductor junction. In some embodiments, the metal is selected amongst transition metals selected from Groups IIIB, IVB, VB, VIB, VIIB, VIIIB, IB and IIB of block d the Periodic Table. In some embodiments, the transition metal is a metal selected from Sc, Ti, V, Cr, Mn, Fe, Ni, Cu, Zn, Y, Zr, Nb, Tc, Ru, Mo, Rh, W, Au, Ag, Mn, Co, Cd, Hf, Ta, Re, Os, Ir, Pd, Pt and Hg.
In some embodiments, the metal is Cu, Au or Ag.
In some embodiments, the metal of the metal-semiconductor junction is Au and the metal grown onto or at the vicinity of the junction is selected from Cu, Au and Ag. In some embodiments, the metal of the metal-semiconductor junction is Au and the metal grown onto or at the vicinity of the junction is Cu. In some embodiments, the metal of the metal-semiconductor junction is Au and the metal grown onto or at the vicinity of the junction is Au. In some embodiments, the metal of the metal-semiconductor junction is Au and the metal grown onto or at the vicinity of the junction is Ag.
The semiconductor material may be any semiconductor material typically used in electronic or optoelectronic devices. Typically, where the process of the invention is applied onto an existing metal-decorated semiconductor material, the process features and conditions may be engineered and selected to meet the limitations of the semiconductor material. In other cases, where a device is constructed bottom-up, and the semiconductor material may be selected to meet the requirements of the device or the process for its manufacture, the semiconductor material may be chosen from a variety of elements of the periodic table to form semiconductor materials or alloys that suite the particular application. Generally speaking, such semiconductor materials may be selected from elements of Group I-VII, Group II-VI, Group III-V, Group IV-VI, Group and Group IV semiconductors and combinations thereof.
In some embodiments, the semiconductor material is a Group I-VII semiconductor, selected optionally from CuCl, CuBr, CuI, AgCl, AgBr, AgI and the like.
In other embodiments, the semiconductor material is a Group II-VI material being selected, in a non-limiting fashion from CdSe, CdS, CdTe, ZnSe, ZnS, ZnTe, HgS, HgSe, HgTe, CdZnSe, ZnO and any combination thereof.
In further embodiments, Group III-V semiconductor materials may be selected. In such cases, the semiconductor materials may be any one or more of InAs, InP, InN, GaN, InSb, InAsP, InGaAs, GaAs, GaP, GaSb, AlP, AN, AlAs, AlSb, CdSeTe, ZnCdSe and any combination thereof.
In additional embodiments, the semiconductor material is selected from Group IV-VI, the material being optionally selected from PbSe, PbTe, PbS, PbSnTe, Tl2SnTe5 and any combination thereof.
In other embodiments, the material is or comprises an element of Group IV. In some embodiments, the material is selected from C, Si, Ge, Sn and Pb. In some embodiments, the semiconductor material comprises at least one of Si and Ge. In further embodiments, the semiconductor material is SiGe.
In some embodiments, the semiconductor material is a surface region or bulk material of a three-dimensional object. The three-dimensional object may be any symmetric or asymmetric object or device. In some embodiments, the object is a feature of an electronic or optoelectronic device, e.g., a surface of the device, an electrode, etc.
In some embodiments, the object is a semiconductor wire, e.g., a nanowire, having at least one of the wire dimensions in the nanoscale, and may be in any length. The nanowire may be characterized by a length in the micrometer scale and a thickness in the nanometer scale. Thus, a nanowire may have an aspect ratio of between 1,000 and 1,000,000.
In some embodiments, the length of the nanowire is between 900 nm and 1,000 microns. In some embodiments, the nanowire length is between 900 and 1,000 nm, between 900 and 1,500 nm, between 900 and 2,000 nm, between 900 and 2,500 nm, between 900 and 3,000 nm, between 900 and 3,500 nm, between 900 and 4,000 nm, between 900 and 4,500 nm, between 900 and 5,000 nm, between 900 and 5,500 nm, between 900 and 6,000 nm, between 900 and 6,500 nm, between 900 and 7,000 nm, between 900 and 7,500 nm, between 900 and 8,000 nm, between 900 and 8,500 nm, between 900 and 9,000 nm, between 900 and 9,500 nm or between 900 and 10,000 nm.
In some embodiments, the nanowire length is between 10 microns and 1,000 microns, between 10 microns and 950 microns, between 10 microns and 900 microns, between 10 microns and 850 microns, between 10 microns and 800 microns, between 10 microns and 750 microns, between 10 microns and 700 microns, between 10 microns and 650 microns, between 10 microns and 600 microns, between 10 microns and 550 microns, between 10 microns and 500 microns, between 10 microns and 450 microns, between 10 microns and 400 microns, between 10 microns and 350 microns, between 10 microns and 300 microns, between 10 microns and 250 microns, between 10 microns and 200 microns, between 10 microns and 150 microns, between 10 microns and 100 microns, between 10 microns and 90 microns, between 10 microns and 80 microns, between 10 microns and 70 microns, between 10 microns and 60 microns, or between 10 microns and 50 microns.
In some embodiments, the nanowire length is between 100 and 1,000 microns, between 100 and 950 microns, between 100 and 900 microns, between 100 and 850 microns, between 100 and 700 microns, between 100 and 650 microns, between 100 and 600 microns, between 100 and 550 microns or between 100 and 500 microns.
In some embodiments, the nanowire diameter, thickness, is between 1 nm and 100 nm. In some embodiments, the diameter is between 1 and 90 nm, between 1 and 80 nm, between 1 and 70 nm, between 1 and 60 nm, between 1 and 50 nm, between 1 and 40 nm, between 1 and 30 nm, between 1 and 20 nm or between 1 and 10 nm.
In some embodiments, the nanowire diameter, thickness, is between 10 nm and 100 nm, between 10 and 90 nm, between 10 and 80 nm, between 10 and 70 nm, between 10 and 60 nm, between 10 and 50 nm, between 10 and 40 nm, between 10 and 30 nm, between 10 and 20 nm, between 20 nm and 100 nm, between 20 and 90 nm, between 20 and 80 nm, between 20 and 70 nm, between 20 and 60 nm, between 20 and 50 nm, between 20 and 40 nm, between 20 and 30 nm, between 30 and 100 nm, between 30 nm and 90 nm, between 30 and 80 nm, between 30 and 70 nm, between 30 and 60 nm, between 30 and 50 nm, between 30 and 40 nm, between 40 and 100 nm, between 40 and 90 nm, between 40 and 80 nm, between 50 nm and 70 nm, between 50 and 60 nm, between 60 and 100 nm, between 60 and 90 nm, between 60 and 80 nm, between 60 and 70 nm, between 70 and 100 nm, between 70 and 90 nm, between 70 and 80 nm, between 80 and 100 nm, between 80 and 90 nm or between 90 and 100 nm.
In some embodiments, the semiconductor wire comprises a wire core of one material, which may or may not be a semiconductor material and an external coat of a second material, which may or may not be a semiconductor material and which may or may not be the same as the core material. In some embodiments, the semiconductor material is made of a single material.
In some embodiments, the semiconductor nanowire is a core/shell structure comprising a core wire and one or more shells coating the core wire.
The semiconductor nanowire may have one or more metallic regions in contact with the semiconductor material making up the surface of the nanowire; namely, the nanowires have one or more metal-semiconductor junctions as herein defined. In some embodiments, the metallic regions are at the ends, tips or edges of the nanowire (at one or both ends), thus being metal caps at the nanowire end(s). As demonstrated herein, the metal caps may be achieved by any one method known in the art, such as molecular beam epitaxy (MBE), pulsed laser deposition (PLD) and chemical vapor deposition (CVD). The metal cap may be formed during the production process of the nanowire, or may be formed, as a separate step, on the nanowire after its manufacture.
In some embodiments, the metal cap is gold.
The metal which is grown onto or at the vicinity of the nanowire-metal cap junction may be selected amongst transition metals selected from Groups IIIB, IVB, VB, VIB, VIIB, VIIIB, IB and IIB of block d the Periodic Table. In some embodiments, the transition metal is a metal selected from Sc, Ti, V, Cr, Mn, Fe, Ni, Cu, Zn, Y, Zr, Nb, Tc, Ru, Mo, Rh, W, Au, Ag, Mn, Co, Cd, Hf, Ta, Re, Os, Ir, Pd, Pt and Hg.
In some embodiments, the metal is Cu, Au or Ag.
In some embodiments, the metal cap is Au and the metal grown is selected from Cu, Au and Ag. In some embodiments, the metal cap is Au and the metal grown is Cu. In some embodiments, the metal cap is Au and the metal grown is Au. In some embodiments, the metal cap is Au and the metal grown is Ag.
The nanowire semiconductor material may be selected from elements of Group I-VII, Group II-VI, Group III-V, Group IV-VI, Group and Group IV semiconductors and combinations thereof.
In some embodiments, the nanowire semiconductor material is a Group I-VII semiconductor, selected from CuCl, CuBr, CuI, AgCl, AgBr, AgI and the like.
In other embodiments, the semiconductor material is a Group II-VI material selected from CdSe, CdS, CdTe, ZnSe, ZnS, ZnTe, HgS, HgSe, HgTe, CdZnSe, ZnO and any combination thereof.
In further embodiments, Group III-V material are selected from InAs, InP, InN, GaN, InSb, InAsP, InGaAs, GaAs, GaP, GaSb, AlP, AlN, AlAs, AlSb, CdSeTe, ZnCdSe and any combination thereof.
In additional embodiments, the nanowire semiconductor material is selected from Group IV-VI, the material being selected from PbSe, PbTe, PbS, PbSnTe, Tl2SnTe5 and any combination thereof.
In other embodiments, the nanowire material is or comprises an element of Group IV. In some embodiments, the nanowire material is selected from C, Si, Ge, Sn and Pb. In some embodiments, the nanowire material comprises at least one of Si and Ge. In further embodiments, the nanowire material is SiGe.
Where the semiconductor material is in the form of a nanowire, the hybrid nanostructure obtained by the process of the invention, comprising the semiconductor nanowire and the metal growth at one of its ends, resemble grass flowers or “florets” as presented in
As noted hereinabove, the synthetic strategy takes advantage of the inherent asymmetry of the initial structure, e.g., the nanowire, having a semiconductor region and a metal region. In the case of such materials obtained by, e.g., CVD processes and vapor-liquid-solid (VLS) synthesis mechanism, the metal region may be a remnant of the metal-seed derived deposition mechanism. The process of the invention which includes etching and deposition steps, derived by the presence of at least one etchant material (e.g., water), the semiconductor composition, the presence of at least one reducing agent, the selection of a metal source to be deposited as metal on the junction, and optionally the presence of surfactants and/or ligands for controlling grain size, confine the self-processing synthesis to a well defined region of the structure with self-limiting reactions. The presence of the etchant, a reducing agent and the metal source allow for structural control that is typically associated with top-down fabrication capabilities and not with bottom-up fabrication processes, such as the process of the invention.
Thus, the presence and concentration of each of the etchant, reducing agent and metal source govern the progression of the self-processing synthesis. The respective amounts of each of these components should be effective to achieve selective etching of a (native) oxide layer at the vicinity of the metal-semiconductor junction, reduction of the metal source and metal deposition onto the etched region.
The metal source is any metal-containing material which provides a metal to be deposited on an etched region of the semiconductor according to the invention.
In some embodiments, the metal in the metal source is in a reducible form; namely in the form which may be reduced to a metal of zero valance. Thus, in some embodiments, the metal may be in the form of a metal cation. In some embodiments, the metal source is selected from the following, wherein “M” represents the metal atom:
In each of the above metal sources, the value of x, which may or may not be an integer, is dependent on the nature of M and the particular case, and may vary to produce any known metal source, as defined.
In some embodiments, the metal source is selected from AuCl3, silver acetylacetonate and copper acetylacetonate.
In the above representative selection of metal sources, the metal M may be selected amongst transition metals selected from Groups IIIB, IVB, VB, VIB, VIIB, VIIIB, IB and IIB of block d the Periodic Table. In some embodiments, the transition metal is a metal selected from Sc, Ti, V, Cr, Mn, Fe, Ni, Cu, Zn, Y, Zr, Nb, Tc, Ru, Mo, Rh, W, Au, Ag, Mn, Co, Cd, Hf, Ta, Re, Os, Ir and Hg. In some embodiments, the metal is Cu, Au or Ag.
The at least one reducing agent is a co-reductant selected to reduce the metal source to a metal (zero valency). As explained herein, once a region of the semiconductor oxide layer is etched and the semiconductor material exposed, in the presence of the at least one metal source, reduction of the metal source may occur by the semiconductor material, which is, in some cases, assisted by or occurs also by the at least one reducing agent also present. The at least one reducing agent is selected amongst mild reducing agent, that is not by itself capable of substantially reducing the at least one metal source.
The at least one reducing agent is selected from organic and inorganic reducing agents. In some embodiments, the at least one reducing agent is selected from alcohols, such as methanol, ethanol, tert-butanol, phenol and glucose, and organic acids such as ascorbic acid.
In some embodiments, the at least one reducing agent is selected from ethanol, glucose, phenol and ascorbic acid. In some embodiments, the at least one reducing agent is ethanol.
The at least one etchant is selected to selectively remove (etch) a region of the oxide layer or film which is present or is intentionally formed for the purpose of e.g., protecting the semiconductor material, on the semiconductor surface at the vicinity of the first metal. The oxide layer on the semiconductor material may be a native oxide, namely an oxide which spontaneously formed on the surface of the semiconductor material, when exposed to, e.g., air, oxygen, humidity, oxidation material, etc. The oxide layer may alternatively be used as a protecting layer on top of the semiconductor material and thus may be caused to form at any one or more regions of the semiconductor surface.
As noted herein, the oxide layer need not be an oxide form of any one or more atoms making up the semiconductor material. In some embodiments, the oxide material, or otherwise a protective film of at least one etchable material may be formed on the semiconductor material so that it may protect the semiconductor material or for purposes of patterning as disclosed herein.
In some embodiments, the oxide layer is a native oxide layer.
The etchant is selected such that it is reactive towards or capable of removing the semiconductor oxide layer only at the junction region. It may not be reactive enough to remove the semiconductor oxide layer in the rest of the semiconductor structure. Thus, the at least one etchant is selected amongst Lewis acids and Lewis bases that are soluble in a non-aqueous solvent, incase water is not present. In some embodiments, the at least one etchant is water. In other embodiments, the at least one etchant is selected from at least one Lewis acid and/or at least one Lewis base and water.
The etchant employed in accordance with the invention is a chemical etchant. The etchant is typically a component in the processing solution, a liquid medium, which the semiconductor material is contacted with or in. The etchant may be the solvent of the processing solution or one of solvents or materials making up the solution.
The etchant is a mild etchant to the oxide layer, so that etching is selective and occurs at the vicinity of the metal-semiconductor junction. Such etching permits patterning of the oxide layer and eventually patterning of the metal regions (second metal regions) grown onto the semiconductor and/or first metal object. The etching removes at least a region of an oxide layer, at the vicinity of the metal semiconductor junction. The size of the “at least a region of the oxide layer” which is removed by etching may be dependent upon process conditions, the particular etchant (e.g., reactivity, concentration, etc.), the constitution and nature of the oxide layer, the semiconductor material, the metal-semiconductor junction, the solution (solvents, other agents therein), etc. The at least a region of an oxide layer may be in any shape and size.
In some embodiments, the at least one region of an oxide layer or the sum of all oxide regions which are etched at the vicinity of the metal-semiconductor junction may be at the nanometer size or at a few micrometer size. In some embodiments, the region of the oxide layer removed is between 1 nm to 3,000 nm. In some embodiments, the region of the oxide layer removed is between 1 nm to 1,000 nm. In some embodiments, the region of the oxide layer removed is between 10 nm to 1,000 nm. In some embodiments, the region of the oxide layer removed is between 1 nm to 500 nm. In some embodiments, the region of the oxide layer been removed is between 10 nm to 500 nm. In some embodiments, the region of the oxide layer removed is between 50 nm to 500 nm. In some embodiments, the region of the oxide layer removed is between 50 nm to 300 nm. In some embodiments, the region of the oxide layer removed is above 1 nm. In some embodiments, the region of the oxide layer removed is above 10 nm. In some embodiments, the region of the oxide layer removed is above 20 nm. In some embodiments, the region of the oxide layer removed is above 30 nm. In some embodiments, the region of the oxide layer removed is above 50 nm.
The etching is selective at the vicinity of the metal-semiconductor junction (interface), and the at least one oxide region removed is at the vicinity of said junction. The term “at the vicinity of the junction” or alternatively “at the vicinity of the first metal” encompass etching or oxide material or layer or film removal at the interface (junction). The vicinity of the interface may also encompass a few nanometers from said interface, e.g., 1 or 2 or 3 or 4 or 5 or 6 or 7 or 8 or 9 or 10 or 15 or 20 or 30 or 40 or 50 nm from said interface.
The “contacting” step of the at least one metal-semiconductor junction with reactants of the hybrid structure is carried out, in solution, by e.g., adding, immersing, mixing, injecting, a processing or reactant solution (e.g., at least one etchant, at least one metal source and optionally at least one reluctant) with or to the metal-semiconductor junction. In some embodiments, the metal-semiconductor junction or the substrate it is on is immersed in the solution. In some embodiments, the solution is added drop-wise or placed by any other means onto the metal-semiconductor junction and/or the substrate it is on. In some embodiments, the substrate may comprise one or more metal-semiconductor junctions and/or one or more objects (e.g., nanowires) comprising said at least one metal-semiconductor junction.
The solution may comprise of additional reactants for building the hybrid nanostructure of the invention, e.g., organic ligands which support the metal clusters or tip growth, organic solvents and ligands used for assisting the process (etching and/or metal growth) and others. In some embodiments, the ligand is at least one thioalkyl, e.g., hexane thiol.
In some embodiments, the process temperature is room temperature (between 22 and 30° C.). In further embodiments, the temperature range is between 20° C. and 50° C. In other embodiments, the process involves heating. In some embodiments, the temperature range is between 15° C. and 100° C.
The etching and the metal region(s) growth (second metal regions) are carried out in chemical manners or by chemical synthesis. The etching and the metal regions growth may be carried out in solution.
The metal region(s) (or metal clusters of the at least one second metal) grown at the vicinity of the junction may cover essentially the entire removed oxide layer region. In some embodiments, the metal region(s) covers essentially the entire metal semiconductor interface. In some embodiments, the metal region(s) covers essentially the entire first metal region. In some embodiments, the metal region(s) covers partially the removed oxide layer region. In some embodiments, the metal region(s) covers partially metal semiconductor interface. In some embodiments, the metal region(s) covers partially the first metal region. In some embodiments, the number of regions on the object (first metal and/or interface and/or exposed semiconductor region) is at least one. In some embodiments, the number of metal regions on a substrate is 2 or 3 or 4 or 5 or 6 or 7 or 8 or 9 or 10.
Where nanowires are substrates of the invention, the metal regions are, in some cases, only at the nanowire tip or tips (ends or edges). Thus, nano-florets of the invention consist of a single tip-formed and tip-concentrated metal region. Each such single metal region may be composed of a plurality of metal clusters, provided that they cover a continuous semiconductor-metal region.
The plurality of metal clusters may be densely packed. In some embodiments, each cluster is in contact with at least one other metal cluster in the metal region. In some embodiments, each cluster is in contact with at least two other metal clusters in the metal region. In some embodiments, each cluster is in contact with at least other metal cluster and all metal clusters in the metal region are directly or indirectly in contact.
These metal clusters may be of any shape. The size of the metal clusters or tips is typically in the nanometric regime. Typically, these metal clusters or metal tips are smaller than the first metal region (metal cap). The size (diameter, cross section) of the metal clusters may be less than 40% or 35% or 30% or 20% or 15% or 10% or 5% or 4% or 3% or 2% or 1% of the size of the metal cap in a bare nanowire. In some embodiments, the size of the metal clusters is below 500 nm. In some embodiments, the size of the metal clusters is below 300 nm. In some embodiments, the size of the metal clusters is below 200 nm. In some embodiments, the size of the metal clusters is below 100 nm. In some embodiments, the size of the metal clusters is below 50 nm. In some embodiments, the size of the metal clusters is below 40 nm. In some embodiments, the size of the metal clusters is below 30 nm. In some embodiments, the size of the metal clusters is below 20 nm. In some embodiments, the size of the metal clusters is below 15 nm. In some embodiments, the size of the metal clusters is below 10 nm. In some embodiments, the size of the metal clusters or the metal tips is between 1 and 500 nm. In some embodiments, the size of the metal clusters or the metal tips is between 1 and 300 nm. In some embodiments, the size of the metal clusters is between 1 and 100 nm. In some embodiments, the size of the metal clusters is between 1 and 50 nm. In some embodiments, the size of the metal clusters is between 1 and 30 nm. In some embodiments, the size of the metal clusters is between 1 and 20 nm. In some embodiments, the size of the metal clusters is between 1 and 10 nm.
In another aspect, the invention provides a self-formed hybrid semiconductor-metal nanostructure manufactured according to any one process of the invention.
In some embodiments, the hybrid nanostructure is a nano-floret structure.
The invention thus provides in another of its aspects a nano-floret comprising or consisting each a semiconductor nanowire having a metallic tip. The metal tip may be in the form of a metal cap connected at the end of the nanowire or in the form of a coat which covers the tip of the nanowire and a region of the nanowire neck (in the form of a so-called finger glove).
In some embodiments, the nano-floret structures of the invention are constructed of a metallic tip which is 100 s of nanometers in length (e.g., between 90 nm and 900 nm) along the long axis of the nanowire, starting at the tip of the nanowire, and of a semiconductor nanowire which is 10 s of micron long (e.g., between 10 and 100 microns).
The aspect ratio of the nanowire may be above 100. In some embodiments, the nanowire aspect ratio is above 1,000. In some embodiments, the nanowire aspect ratio is above 10,000. In some embodiments, the nanowire aspect ratio is above 100,000. In some embodiments, the nanowire aspect ratio is above 1,000,000.
The aspect ratio of the nanowire may be between 1,000 and 100,000.
In some embodiments, the nanowire aspect ratio is between 100 and 1,000,000. In some embodiments, the nanowire aspect ratio is between 1,000 and 1,000,000. In some embodiments, the nanowire aspect ratio is between 10,000 and 1,000,000. In some embodiments, the nanowire aspect ratio is between 100,000 and 1,000,000.
The nano-floret structures of the invention benefit from superior physics of tunneling devices and may be utilized for sensing while making use of conventional device processing techniques and compatibility with semiconductor processing technologies.
Thus, the invention further contemplates a surface associated with one or a plurality of nano-florets according to the invention. In some embodiments, the nano-florets are substantially perpendicular to the surface. In other embodiments, the nano-florets are substantially parallel to the surface.
The hybrid (nano-floret) nanostructure of the invention and those prepared according to the invention may be used in a variety of electronic and opto-electronic applications and in the construction of a variety of electronic and opto-electronic devices or elements thereof.
The device of the invention implements one or more of the hybrid nanostructures of the invention and/or a hybrid nanostructure obtained by a process of the invention.
The processes and the hybrid nanostructure of the invention find utility in a vast range of industrial applications, such as application in electrical devices, optical devices, plastic devices, transparent devices, consumer electronics, industrial electronics, wireless systems, space applications, military applications, civil applications, medical applications and many other applications.
In some embodiments, the device of the invention may be used for constructing a field effect transistor (FET) on an active device area of a device substrate.
In some embodiments, the device of the invention is used for producing heating elements and thermal insulators.
In some embodiments, the device of the invention is used for producing catalytic materials.
In a further aspect, the invention provides a device comprising at least one hybrid nanostructure of the invention or plurality or array of hybrid nanostructures according to the invention or obtainable by a process of the invention.
In some embodiments, the device is an electronic device (transistor, diode) in a form selected from n-p-n, p-n-p and n-i-p.
In some embodiments, the device is selected from a diode and/or a transistor and/or an electronic circuit component and/or an integrated circuit and/or a detector and/or a switch and/or an amplifier and/or a transducer and/or a laser and/or a tag and/or a photoconductor; a photodiode and/or a photovoltaic cell and/or a light emitting diode (LED) and/or a light sensor and/or a display and/or and a large area display array.
In some embodiments, the device of the invention is used as a detector. In some embodiments the detector is a thermal detector. Non-limiting examples of detectors are Near Infrared (NIR), Short-wave infrared (SWIR) and mid-wave infrared (MWIR) detectors.
In some embodiments, the device of the invention is used as a bolometer.
In some embodiments, the nano-florets of the invention may be utilized as nano-gap sensors for the detection and monitoring of a variety of materials.
As known in the art, detection and monitoring of volatile chemical compounds in the environment is in increasing need for numerous aspects of every-day life and well-being. Electrical detection is advantageous over a variety of other available detection methods because it allows relatively simple and low cost design of the end products and relying on Si nanowires makes the fabrication process compatible with current semiconductor industry standards.
Most nanowire sensors operate as Field-effect transistors (FET) where the chemical binding event changes the local electric field and results in the detection signal. Other class of sensors and devices relies on nano-gap devices where a tunneling current is passed through nano-scale gap. Any binding event that takes place within or next to the nano gap alters the tunneling current and translates to a detection event.
The invention disclosed herein is further directed to a simple sensitive tunneling nano-gap device such as a nano-gap field effect transistor, which offers superior performance over nanowire FET devices. In an exemplary device, a pair of nano-floret structures is connected head-to-head (metal-to-metal) with a molecular moiety, forming well-defined nano-gap structure.
The tunneling device acts as an ultra-sensitive detector. Molecular binding by the molecular moiety or at the vicinity of the moiety alters the surface electrical potential, resulting in variation of the tunneling current through the device. This mechanism is analogous to a field effect transistor whereby the electric field gates the current through the channel underneath. The tunneling device mechanism introduces a gain to the readout signal and therefore can serve as a sensitive sensor. The tunneling current is very sensitive to the surface potential shape therefore it is possible to tune the device gain to be different in the ‘on’ and ‘off’ states (larger for the ‘on’ state). This mode of operation provides signal to noise ratio improvement. This effect should be analogous and even stronger to that of tuning a field effect transistor to work in the sub-threshold limit for the off state.
In order to better understand the subject matter that is disclosed herein and to exemplify how it may be carried out in practice, embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:
(
The ability to control the process was studied using various water concentrations, different metals, and different SiGe alloy compositions, as exemplary system of the invention, to deduce the roles of each factor and the respective mechanisms involved. Overall, ex situ transmission electron microscopy (TEM), in situ scanning transmission electron microscopy (STEM) using a novel fluid cell TEM holder and inductively coupled plasma mass spectrometry (ICP-MS) techniques were used to study the mechanistic reaction details and progression of the various processes. The analyses provided structural and chemical information regarding the processes that occurred and explained the underlying mechanisms.
The structural evolution with respect to the process parameters, such as water concentrations in the deposition solutions and the SiGe alloy composition, were studied using energy dispersive X-ray spectroscopy (EDS). In addition, ICP-MS analyses were performed on the process solutions to quantify the dissolved Ge levels as a function of the process parameters. The SC-Au nanoparticle (NP) junction present at the SiGe NW tip set an inherent asymmetry in the nanowire electronic structure (
Overall, dH remained constant and was independent of the water concentration (dH<65 nm for the SiGe NWs diameter used). In contrast, the metal deposition length L at the SiGe NW surface abruptly increased to <360 nm in water in EtOH concentrations greater than <1.0M (
The structures of the fully evolved Au—NFs were further characterized by preparing cross-sectional focused ion beam (FIB) lamellae, which were subsequently analyzed using TEM, EDS, and scanning electron microscopy (SEM) at different regions of the structure (
To quantify the dissolved Ge concentration as it evolves during the deposition process, ICP-MS was used for a range of water concentrations (
The ICP-MS results indicate an increase in dissolved Ge concentrations with increased water addition (with saturation at approximately 8 mmol H2O for both the blank and deposition solutions). An increase of approximately 7-fold was obtained in dissolved Ge comparing the deposition solution with blank solution processes for each water concentration (
Subsequently, the Au-NF morphology and dissolved Ge levels were studied for various SiGe nanowire alloy compositions (TEM,
The ICP-MS results showed similar trends with an abrupt increase in the dissolved Ge concentration for Ge contents of 70% or more for the deposition and blank solution processes (
To account for the dissolved Ge levels and the progression of cap deposition, an electroless-type metal deposition process was assumed to have occurred in the presence of noble metal cations (Au3+) because of galvanic displacement and metal assisted chemical etching (MACE) mechanisms. While SiO2 is a stable oxide that requires relatively harsh etch conditions, such as HF for dissolution, pure GeO2 is prone to dissolution in mild conditions and even in moist environments due to assistance by the MACE mechanism. Therefore, water can be used as a mild etchant for removing the native oxide of Si—Ge alloys. Adjusting the SiGe nanowire composition tuned the overall stability of the SiGe alloy native oxide toward dissolution in the presence of water to a level where the native oxide is stable toward water dissolution as long as it is decoupled from the metal assisted etch. The removal of the native oxide from the SiGe nanowire surface results in an exposed surface that is prone to undergo a galvanic displacement reaction with Au3+ metal ions, generating oxidized semiconductor and resulting in additional Ge dissolution.
Generally, MACE promotes semiconductor oxidation near the semiconductor-noble metal junction, where holes accumulate and the gold NP used during the CVD synthesis of the nanowire function as an electron acceptor, further catalyzing metal deposition at the Au NP surface at the tip of the nanowire. In other words, the metal assisted catalytic deposition occurring at the Au catalyst surface is coupled with the MACE process that occurs at the semiconductor portion.
In addition, the EtOH serves not only as a solvent but also as a reducing agent during the neck deposition step. This was studied by mixtures of tert-butanol-EtOH for the deposition process (
It is further demonstrated that EtOH acts not only as solvent but also for promoting redox reactions. Alternative reducing agents may be selected from glucose, phenol and ascorbic acid; all reducing agents resulted in nano-floret structures with different morphologies while keeping similar overall dH and L dimensions (
Nano-floret synthesis was studied for other metals, including Ag and Cu, which together with Au constitute the coinage metal elements, all showing NF structures with different morphologies as detailed below (see
Furthermore, a constant ratio of approximately 7 was identified for dissolved Ge for all studied SiGe alloy compositions when analyzing the resulting solutions for deposition and blank (without gold) processes (
This result indicated that dissolved Ge was independent of the nanowire length and the total nanowire surface area, which increase linearly with the nanowire length. This finding agrees with the MACE mechanism, in which the oxide etch is restricted to the metal-semiconductor junction near the nanowire tip, irrespective of the total native oxide layer surface (see
Overall, the Au-nano-floret synthesis involves a sequence of localized etching of the semiconductor oxide layer and self-limiting metal deposition to yield Au0 cap deposition with well-defined dimensions at the nanowire tip. The cap deposition process involves two metal deposition mechanisms, direct galvanic displacement at the exposed semiconductor surface and catalytic metal deposition, metal assisted catalytic deposition, at the nanowire tip, resulting in dissolved Ge in the solution, and self-termination of the process upon full coverage of the exposed semiconductor region. A summary of the NF synthesis mechanisms and various processes is presented in
Additional fine-tuning of the Au-nano-floret structures morphology was demonstrated for controlling the size of deposited Au clusters by adding alkylthiols to the Au-nano-floret process solution. Au-nano-floret prepared using the same procedure while adding 5 mM hexanethiol in the deposition solution result in a significantly smaller average Au cluster size (3±0.3 nm) compared with Au-nano-florets prepared in the absence of hexanethiol (17±3 nm) (
Overall, the results revealed that distinct processing steps can be identified that are analogous to those of conventional top-down processing, as depicted in
It is suggested that the reduction of Cu2+ to Cu0 is restricted to the semiconductor-Au NP surface by metal assisted catalytic deposition and occurs at the Au tip of the SiGe nanowire. In other words, the SiGe-Au junction catalyzes Cu2+ reduction and deposition by promoting the accumulation of holes at the semiconductor-noble metal interface and injection of electrons to the Au catalyst surface. The lower standard redox potential for Cu only results in deposition via metal-assisted catalytic deposition because the driving force for the direct galvanic displacement process is not sufficient. In contrast, for Au- and Ag-nano-floret, the standard redox potential is sufficiently positive for activating the direct galvanic displacement at the exposed semiconductor interface (where the native oxide is removed by MACE) and the metal-assisted catalytic deposition mechanism at the nanowire tip. Finally, the formation of bimetallic nano-floret structures was achieved by stepwise deposition of (Au, Ag)-nano-floret and (Au, Cu)-nano-floret, as shown in
The optical absorbency of the nano-floret films was measured on quartz slides using an integrating sphere showing a broad plasmonic band (
Metallic nano structures are well known for their utility in probing adsorbed probe molecules with high amplification of the Raman signal commonly termed SERS. The plasmonic absorption was utilized to demonstrate the application of nano-floret films as SERS substrates using thiophenol monolayer. Raman spectra measured for thiophenol-functionalized Au-nano-floret, Ag-nano-floret, and (Au,Ag)-nano-floret are presented in
In summary, the inventors present a synthetic strategy that takes advantage of the inherent asymmetry of the NW structure with the SiGe—Au NP seed resulting from the VLS synthesis step. The SiGe—Au junction is important for activating etching, deposition, and modification steps. Control over the deposition and etching processes has been demonstrated by several knobs: (i) SiGe alloy composition, (ii) deposited metal redox potential, and (iii) etchant (water) concentration. Both the etching and deposition processes were confined to a well-defined region of the structure with similar processes and self-limiting kinetics. These traits allowed for structural control that is typically associated with top-down fabrication capabilities. It is demonstrated that such levels of control can be attained for bottom-up synthesis by cuing the local etching (MACE) of the SiGe alloy oxide layer, catalytic deposition of metal cations at the NW tip by MCD, and deposition at the exposed NW tip by GD. Introducing surfactants (HT) allowed further control over the deposited cluster size and morphology. Finally, demonstrated is the synthesis of bimetallic NFs when employing the coinage metals Au, Ag, and Cu. These bimetallic building blocks are highly attractive for catalysis, optical applications and more. The overall synthesis is termed SP due to the controllable, localized, and self-limiting sequence of events that occurs autonomously and results in the transformation of the SiGe NW structure into nano-flora-like hybrid nanostructures. In addition, the SP strategy demonstrated here for NF—HNS architectures enables interesting possibilities regarding controlled symmetry breaking at the nanoscale, which is an important feature for attaining complex nanosystems with intriguing functionalities. Such HNSs consist of metal and SC with distinct dimensionalities that encompass significant effects in a wide range of applications, such as photocatalysis, photovoltaics, sensing, energy harvesting and storage, and electronic devices. For example, the combination of SC nanorods with metallic NPs improved light harvesting because of the enhanced absorbance and charge separation properties of the combined nanosystem relative to the individual components.
Methods:
Synthesis of Silicon-Germanium (Si—Ge) Alloy Nanowire (NW)
Glass slides were cleaned using O2 plasma (Pico plasma cleaner, Diener electronic GmbH) at 60 W for 2 min. Next, the slides were immediately incubated for 5 min in a poly-L lysine solution (0.1% in H2O, Sigma-Aldrich) before being washed with ultra pure DI water (>18MΩ, ELGA purification system). Then, Au NPs were deposited from a citrate-stabilized water suspension (Ted Pella Inc.) and washed with DI water. The slides were then cleaned using O2 plasma to remove any organic residues and contaminants. The NW synthesis was conducted using a custom-built CVD system. In addition, SiGe NWs with various alloy compositions were obtained by varying the appropriate process flow parameters for GeH4 (10% in H2) and pure SiH4 for specified time durations. The specific process parameters for the various SiGe alloys are provided in Table 1.
SiGe Nano-Floret (NF) Synthesis
First, SiGe alloy NWs were prepared on substrates and stored in an ambient atmosphere for 24 hr to form a native oxide layer. Then, Au—NFs were prepared by reacting the substrates with NWs in an EtOH solution (99%, ACROS Organics) containing 1 mM AuCl3 (99%, ACROS Organics) and a specified water content for 3 min at room temperature. The treated substrates were carefully washed with EtOH and TDW to remove excess salts. Next, Ag-NFs were prepared using the same procedure with 1 mM silver acetylacetonate (98%, Aldrich) in acetonitrile (≥99.9% Merck). Then, Cu-NFs were prepared using a 10 mM copper acetylacetonate (98%, ACROS Organics) solution with EtOH/DCM 1/1 (v/v) (>99.8%, Sigma-Aldrich) and at the specified water content.
Transmission Electron Microscopy (TEM)
First, NW and NF were synthesized directly on TEM grids with 50 nm silicon nitride support films (Ted Pella Inc.) following the NF synthesis procedure described above. Then, TEM and STEM imaging were performed using an FEI Tecnai F20 G2 microscope with EDAX EDS detector.
Fluid Cell Scanning Transmission Electron Microscopy (STEM)
In situ observations of the Au growth on SiGe nanowires were performed using a Poseidon 200 fluid cell transmission electron microscopy holder (Protochips Inc.) in a double Cs-corrected JEOL 2200 FS microscope operated in scanning mode using a high-annular angular X-ray detector. The 3C probe setting and the smallest condenser aperture were used to optimize the contrast and resolution.
For these studies, SixNy membranes with nitride (50 nm thick) on top of Si chips were used with a spacer thickness of 500 nm (minimum fluid layer thickness in the beam direction). Before the observations, the SiGe nanowires were deposited on the lower chip to ensure a sufficient wire density on the membrane for TEM observation.
First, an anhydrous EtOH solution was pumped at a rate of 300 μl/hr before the 1 mM Au/EtOH solution was introduced after approximately 30 minutes. Next, alignment was performed, and suitable nanowires were selected. After adding the Au/EtOH solution, the sample was imaged under low magnification (20 k) to minimize beam-induced reactions. After the solution was pumped at a rate of 300 μl/hr, approximately 15 min passed before an increased STEM intensity could be observed at the nanowire tips. Subsequent, increasing the magnification to 100 k resulted in the deposition of Au nanoparticles within the observation area. To ensure that the Au deposition at the tips was not induced by electron beam nanowires outside the observation area were investigated and showed similar Au tip diameters and lengths.
Mass Spectroscopy (ICP-MS)
Quantification of dissolved Ge was performed by MS analysis using an Agilent Technologies 7500 cx ICP-MS with an Octopole Reaction System (ORS). An external calibration technique using Ge standards containing 0, 0.1, 0.5 and 1 ppm of Ge in 1% HNO3 was used to obtain a calibration curve. Finally, the SiGe NW films were prepared on 22×22 mm slides, allowed to stand in the air for 24 hr after synthesis, and immersed in EtOH/H2O/AuCl3 and EtOH/H2O solutions.
Detection and Monitoring of Volatile Chemical—Background
Detection and monitoring of volatile chemical compounds in the environment is in increasing need for numerous aspects of every-day life and well-being. This includes the monitoring of air quality in urban areas, detection of volatile compounds associated with various diseases, and even the detection of explosives in airports and more. Accordingly, many methods were developed for sensing volatile compounds based on a large array of physical detection mechanisms, including electrical, optical, and fluorescence, and biological mechanisms using enzymes and even living bacteria. Among the physical mechanisms, some of the most promising approaches for constructing sensors are based on the use of nanowires for electrical detectors. Electrical detection is advantageous because it allows relatively simple and low cost design of the end products and relying on Si nanowires makes the fabrication process compatible with current semiconductor industry standards. As such, nanowire-based electrical detection of volatile compounds is an active field with both academic research and commercial applications developments. Most nanowire sensors operate as Field-effect transistors (FET) where the chemical binding event changes the local electric field and results in the detection signal. Other class of sensors and devices relies on nano-gap devices where a tunneling current is passed through nano-scale gap. Any binding event that takes place within or next to the nano gap alters the tunneling current and translates to a detection event. Nano-gap devices may offer superior performance over nanowire FET devices however the fabrication of the nano-gap is quite difficult using current methods.
The synthesis of a new class of hybrid nano-structures with floret-like architectures enables structures that consist of a metallic tip with 100 s of nanometer length scale, connected to a highly conductive semiconductor nanowire with 10 s of micron length scale. A key advance in making this approach feasible is the method developed for preparing pairs of such structures (dimers) where the gold tips of the nano-florets are connected with molecular linkers that result in well-defined nano-gap structures, determined precisely by the molecular details of the linker used. Overall, the newly developed synthesis offers an unprecedented method for the formation of a nano-gap devices connected to micron scale contacts using low-cost standard methods.
The self-processing nano-flora-based devices were realized using standard processing techniques. Two macroscopic contacts were formed on a substrate with patterned areas for selective growth. The electrical circuit was formed, as depicted in
These properties supply the required device flexibility for detecting different targets.
On the gold tips thiol and amine end group molecules may be self-assembled to form a MIM junction. As
Improved device sensitivity was achieved using junctions with fewer NF bridging across the macroscopic electrodes. The number of bridges was control by the selective growth on the gold covered area. Therefore, in the final device, junctions with different bridge concentration may help cover all sensitivity ranges.
The Tunneling Device Act as an Ultra-Sensitive Detector
Nano-Gap Devices Formed with Functional Materials
Devices according to the invention may be functionalized by materials such as thiols, amines and others, for achieving superior detection of molecules in, e.g., the gas phase. Such functional materials serve as bridges between the nano-floret heads and act as ligands for forming, e.g., charge-transfer complexes, analyte molecules, such as nitro-aromatics materials. Non-limiting examples of such functional materials are thiolated organic materials.
Near Infrared (NIR) and Short Wave Infrared (SWIR) Detectors
The research improves and extends the range of near infrared (NIR) and short wave infrared (SWIR) detectors for operating at the 1.7-2.5 μm range. The improved detector architecture makes use of conventional top-down complementary metal-oxide semiconductor (CMOS) fabrication of available detectors and integration of nanoshell structures with extended plasmonic absorption made by novel bottom-up synthesis which is compatible with standard CMOS processes. By using the plasmonic nanoshells the purpose was to enhance the response and the spectral range of polycrystalline Ge on Si detectors and enhance the responsivity for selected infrared bands in bolometers. Application-oriented end points offer a two-fold strategy: (I) a low cost, ‘good enough’ solution which is key for extending the applicability of NIR-SWIR detectors for currently out of reach appliances because of the poor performance of available low cost solutions or the high cost of high performance solutions, (II) a high-end solution offering enhanced capabilities for bolometers making them better tuned for specialized applications where cost is not the main concern.
The technology of the invention may thus be used for improving the performance of existing detectors at the Low SWIR range operating in the 1.7-2.5 μm window by two convenient approaches that rely on utilization of nanoshell structures with extended LSPR absorption: enhancement of the detector response range by spectral broadening and enhancement of the sensitivity for currently available CMOS compatible process.
The above improvements are obtained by coupling NIR-SWIR plasmonic absorbers with broad spectral response (0.8-3.0 μm) to existing detectors. The LSPR absorption is obtained by novel and simple synthesis of nanoshells with adjustable spectral response covering the desired range.
In
In
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/IB2016/052276 | 4/21/2016 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2016/135713 | 9/1/2016 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20080081388 | Yasseri | Apr 2008 | A1 |
| 20080088899 | Kamins | Apr 2008 | A1 |
| 20080266556 | Kamins | Oct 2008 | A1 |
| 20100215915 | Norton | Aug 2010 | A1 |
| 20160079452 | Seok | Mar 2016 | A1 |
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| Number | Date | Country | |
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| 20180065842 A1 | Mar 2018 | US |
| Number | Date | Country | |
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| 62119445 | Feb 2015 | US | |
| 62312063 | Mar 2016 | US |
