Patent Application
20070200608
The present invention is directed to delay circuits and, more particularly, to thermally-sensitive circuits that can be used to regulate gate delays.
As the power density of modern integrated circuits continues to increase with shrinking feature size, power and temperature management become increasingly important. Thermal profiling, along side analog simulation, is crucial to designing large and power-hungry circuits (see IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(8):1211-1220, October 2000, “A temperature aware simulation environment for reliable ULSI chip design”, Y. K. Cheng and S. M. Kang; and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(8):668-681, August 1998, “ILLIADS-T: An electro-thermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips”, Y. K. Cheng, et al.) Static thermal profile information can be used to place circuits on a die to maximize temperature uniformity, thereby reducing the peak temperature (see IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(2):253-266, February 2000, “Cell-level placement for improving substrate thermal distribution” C. H. Tsai and S. M. Kang.) Likewise, dynamic temperature profiling can be used to direct operation, e.g. halting the system when the circuit is too hot, or switching to a lower power mode.
Circuits that overheat beyond specified operating conditions may suffer timing failures, or become damaged for various reasons, including thermal runaway. Traditional power management in synchronous systems often involves transitions to different system states or modes, typically involving changes in clock frequencies or voltage levels. However, as computational operations are performed more rapidly and involve increasingly larger amounts of computational circuitry, it is becoming progressively harder to synchronize computational operations with reference to a single global clock signal. In many cases, enforcing such synchronization greatly constrains the performance of the computational circuitry. To remedy this problem, some designers have begun to investigate the possibility of using “asynchronous” circuits that do not operate with reference to a global clock signal, and are hence not constrained by the need to continually synchronize computational operations with the global clock signal. In many cases, such asynchronous circuits can increase computational speed by an order of magnitude or more.
Asynchronous circuits operate without any global clock, and use handshakes to move and communicate data. The data-driven nature of asynchronous circuits allows a circuit to idle with no switching activity when there is no work to be done. Increasing the computational speed of an asynchronous circuit causes the circuit to switch more frequently, resulting in increased power consumption and consequently a significant amount of heat. Computing systems typically employ various components to dissipate this heat, such as heat sinks and cooling fans. However, as the computational speed of semiconductor chips continues to increase, and as these chips are packed more closely together to minimize propagation delay between the chips, it is becoming progressively harder to effectively dissipate this heat. This leads to excessive heat buildup, which can cause a computer system to fail, and in some cases can permanently damage circuitry within the computer system.
Asynchronous circuits are capable of operating correctly in the presence of continuous and dynamic changes in delays. Sources of delay variation may include temperature, supply voltage, manufacturing, noise, radiation and other transient phenomena. The frequency of an asynchronous pipeline is determined by the gate delays on the critical path rather than an external frequency source. As the circuit heats up, the gate delays increase and the frequency naturally drops, thereby reducing the circuit's dynamic power consumption and self-heat generation. However, the natural negative feedback retardation of this self-heating rate is too weak to halt the increase in temperature (see “An Energy-Complexity model for VLSI computations”, J. A. Tierno. PhD thesis, California Institute of Technology, 1995.)
It would, thus, be useful to provide a method and apparatus that automatically regulates the performance, power consumption and resultant generated heat of asynchronous circuits.
Some conventional voltage reference circuits requiring PVT (process, supply voltage, temperature) independence have used diode or bipolar junction transistor (BJT) bandgap reference circuits to generate temperature dependent signals used in voltage and/or current compensation. Circuits such as these typically require a supply voltage of at least 1.3 volts. As technology improves, and components become smaller, the supply voltages continues to drop. Some current processors operate with supply voltages of 1.4 volts, close to the limit at which diode or BJT bandgap circuits will become ineffective for use as supply voltages due to the silicon bandgap of 1.23 volts.
In light of the increasing use of non-power supply voltages in integrated circuit devices, there is an additional need for thermal management circuits and methods to impose negligible implementation overhead.
The present invention provides a mechanism and a method for automatically regulating the performance and power consumption of integrated circuits. The self-timed nature of asynchronous circuits is leveraged to allow delays to vary continuously during operation, enabling stall-free performance-throttling and the limiting of heat build up. The timing-robustness of asynchronous circuits also facilitates use of a thermally-sensitive delay elements to automatically, continuously modulate the speed of selected circuits without interrupting operation, and without imposing significant implementation overhead.
In one aspect, the present invention provides easily-implemented, thermally-sensitive circuits and methods for regulating the performance of asynchronous (or self-timed) circuits. The approach does not require complex temperature measurement circuitry, rather, the respective temperature response of sub-threshold devices is used to construct a signal for controlling the speed of other circuits. An explicit temperature sensitivity is introduced to amplify the dynamic range of a temperature controlled delay element. A properly designed delay element can then be used to adjust the frequency of a local circuit, wherein, for example, an increase in circuit temperature increases the delay of the digital circuits.
In another aspect, the present invention provides apparatus and methods for regulating heat within an asynchronous circuit. During operation, a temperature sensitive voltage source generates a voltage signal indicative of the temperature within the asynchronous circuit. The voltage signal reflects non-linear temperature sensitivity above a predetermined threshold temperature, such that the delay introduced into the asynchronous circuit grows non-linearly above said threshold temperature. The temperature sensitive voltage signal is received as an input by a voltage-controlled delay mechanism that is configured to automatically continuously modulate the speed of signal propagation through the circuit in response to said voltage signal, causing circuit elements within the asynchronous circuit to switch less frequently and consequently causing the circuit elements to generate less heat with increasing circuit temperature.
In one embodiment, the temperature sensitive voltage source comprises a pair of transistors forming a resistive voltage divider, each judiciously sized and sub-threshold biased to have explicit temperature sensitivity characteristics. A first of the transistors is preferably biased for near-threshold operation, while the second transistor is biased for deep sub-threshold operational region. The voltage signal indicative of the circuit temperature is output at a node coupling the source electrode of the first electrode to the drain of the second transistor. Voltage sources biasing the transistors may be disposed off-chip remote from any local heating effects. An advantage of an apparatus in accordance with the present invention is that temperature sensing is performed indirectly by the transistors, without additional, direct temperature sensors. Additionally, the transistors do not require significant power to operate. For example, during operation peak current flowing through the transistors is on the order of picoamperes to tens of nanoamperes. All the voltages used for biasing to set the delay characteristics can be designed in a way to allow calibration following production, as known in the art.
In another embodiment, the voltage sensitive delay mechanism comprises a foot transistor of a pull-down circuit, wherein the output node of the temperature sensitive voltage source biases the gate electrode of the foot transistor. The drain electrode of the foot transistor is connected to a logic gate such as, for example, a logic circuit inverter, and the source electrode of the foot transistor is shunted to ground, such that changes in the temperature sensitive voltage source voltage modulates source-drain current of the foot transistor and thereby the speed of a pull-down transition, i.e., an increase in circuit temperature is translated into a lower output voltage signal and corresponding lower foot transistor current and increased delay in the pull-down transition. The apparatus operates automatically and continuously, such that changes in the circuit temperature will result in an almost immediate corresponding change in the introduced delay.
In yet another embodiment, an apparatus in accordance with the present invention also includes a state-holding component such as, for example, a conditional staticizer, coupled to the output node of said temperature sensitive voltage source. The conditional staticizer is configured with the logic gate of the asynchronous circuit to maintain the logic gate voltage level existing when the temperature of the asynchronous circuit exceeds a predetermined threshold temperature until the circuit temperature falls below the predetermined threshold temperature.
In another aspect, and as described below, the present invention provides integrated circuit devices incorporating thermally-sensitive circuits, such as, for example, delay circuits, ring oscillators, and/or any asynchronous logic family that uses handshaking, such as field programmable gated arrays (FPGAs).
In yet another aspect, the present invention provides integrated circuit devices and methods for thermally-aware dynamic resource scheduling. Such devices typically include an asynchronous dispatcher adapted to forward data among multiple similar function units and, preferably, an arbiter adapted to select the multiple similar function units to which data should be sent. A modified logic gate as described above is integrated within each logic block buffer of each function responsible for generating acknowledges for the arbiter indicating the readiness of the associated function unit to receive and process data. The speed of signal propagation through the at least one logic gate in each function block is automatically continuously modulated in response to the indirectly sensed temperature of the particular function block, and adjustments to the switching frequency of the logic gate are made, consequently causing the frequency of readiness acknowledges transmitted from each particular function unit to the arbiter to vary with temperature of that unit. The arbiter receives and selects from among the readiness acknowledges, and sends data to the function unit associated with the selected acknowledge.
An advantage of the present invention is that the circuits and methods providing thermal regulation may be selectively, rather than globally, utilized. That is, thermally-aware modified logic gates may be incorporated into certain logic pathways of a circuit but not other logic pathways in the same circuit. Thus, if it has been determined that it is acceptable for particular logic pathways to operate faster than others, there is no need to slow the entire circuit down with a global delay. Also, the present invention is not limited to asynchronous circuits. For example, the mechanisms and methods described herein may also be applicable in Globally-Asynchronous, Locally Synchronous circuit designs, by local frequency scaling in a clock domain using a temperature-sensitive frequency synthesizer.
For a better understanding of the present invention, together with other and further objects thereof, reference is made to the accompanying drawings and detailed description, wherein:
The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of particular applications and their requirements. Various modifications to the preferred embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
A. Performance and Temperature Regulating System
It is the self-timed nature of asynchronous circuits that allows delays to vary continuously during operation, enabling stall-free performance-throttling. The present invention leverages the temperature response of subthreshold devices 22,34 to construct voltage signal Vg 16, which is utilized to control the speed of other circuits. Increases in the temperature of circuits, generally, increases the delay of digital circuits. The present invention introduces explicit temperature sensitivity to amplify the dynamic range of a temperature controlled delay element, delay mechanism 18. A properly designed delay element can then be used to adjust the frequency of a local circuit such as, for example, asynchronous circuit 14.
Asynchronous circuits operate without any global clock, and use handshakes to move and communicate data. The data-driven nature of asynchronous circuits allows a circuit to idle with no switching activity when there is no work to be done. Asynchronous circuits are capable of operating correctly in the presence of continuous and dynamic changes in delays. Sources of delay variation may include temperature, supply voltage, manufacturing, noise, radiation and other transient phenomena. The timing-robustness of asynchronous circuits facilitates the use of the thermally-sensitive delay element 18 to automatically continuously modulate the speed of selected circuits of circuit 14 without interrupting operation.
B. Thermal Dependence
In certain embodiments, the thermally-sensitive voltage source 12 includes a first transistor M222 having a source electrode 24 coupled to an output node 26, a gate electrode 28 coupled to a first bias voltage 30 biasing transistor M222 in a sub-threshold region so as to have a first thermal sensitivity, and a drain electrode 32. A second transistor M134 having a drain electrode 36 is coupled to the output node 26 and the source electrode 24 of transistor M222. Gate electrode 38 of transistor M134 is coupled to a second bias voltage 40 biasing transistor M134 in a sub-threshold region so as to have a second thermal sensitivity distinct from the thermal sensitivity of M222. Transistors M134 and M222 form a resistive voltage divider, such that the temperature sensitive voltage signal Vg 16 is produced at the output node 26.
The operation of transistors, generally, in the sub-threshold region is more sensitive to temperature than the above-threshold region. In the sub-threshold region, the source-drain current is exponentially dependent on temperature (see Behzad Razavi. Design of Analog CMOS Integrated Circuits. Tata McGraw-Hill, 2004, incorporated herein by reference):
where ID is the drain-source current, I0 depends on channel width, channel length, diffusion constant of carriers, carrier density and electron charge (see Neil Weste and David Harris. CMOS VLSI Design: A Circuits and Systems Perspective. Addison-Wesley, 2005, incorporate herein by reference), ζ is a nonideality factor (greater than 1), and T is temperature in Kelvin.
In thermally-sensitive voltage source 12, transistors M134 and M222 are biased differently to have contrasting thermal sensitivities. In one embodiment, transistor M134 is designed and biased to operate in deep subthreshold (more temperature-sensitive), while transistor M222 operates near-threshold. The bias voltages 30,40 and the respective sizes of transistors M1 and M2 are chosen to achieve the desired temperature response for a given technology. The bias voltages 30,40 can be generated off-chip relative to transistors M1, M2 for post-fabrication tuning and runtime controlling. This circuit was sufficient to meet the intended design goals, however the circuit can be more generally characterized as using different temperature-sensitive structures to produce arbitrary temperature-delay characteristics.
What follows is an example of the circuit with parameters tuned for a particular temperature response.
C. Design Example
The inventors simulated the temperature-dependent circuit 14 shown in
In a simplified setup, where the drain electrode 52 of the foot transistor 44 is connected directly to a Vdd voltage source, the drain-source current through foot transistor 44 was also measured. The results of the current measurement are shown
The delay through the modified circuit 14 was measured and is plotted as a function of temperature in
Above 113° C., Vout never switches because the current through the pull-down logic is insufficient to overpower the pull-up staticizer, so the delay is infinite. This means the circuit will naturally halt above a critical temperature, and resume once the temperature drops sufficiently. The delay-derating factor was approximated with a piecewise-continuous function of temperature in the digital-thermal simulator.
The static power consumption of the temperature dependent voltage source 12 is due to the current through the sub-threshold, weakly-sized transistors M134 and M222.
D. Delay Model
For normal (not thermally-sensitive) transistors, the following model can be used for delay-derating as a function of voltage and temperature (here denoted as θ). The derating function can be factored into three components: a voltage dependent factor f, a temperature-dependent factor g, and a mixed threshold voltage term h.
Table 1 lists the parameters used for the simulations, using a TSMC 0.18 micron technology. Some parameters have separate values for NFETs and PFETs, denoted by additional subscripts N and P. The coefficients were determined through empirically fitting to hspice data.
E. Evaluation
This section presents the results of exemplary simulations or circuits that use proposed thermally-sensitive transistors. As shown below, in each non-limiting example, one or more logic gates modified with temperature-sensitive voltage sources and delay mechanisms in accordance with the present invention are substituted for one or more selected logic gates (inverters) in example digital circuits. The result is are circuits that regulates their speed based on the local circuit temperature with minimal hardware overhead. Several examples of varying complexity are now described to demonstrate the effectiveness of the thermally-sensitive modified circuits.
The simulator employed was an event-driven digital simulator, extended to capture the transient effects of temperature and supply voltage on delay. The input to the simulator comprised a sized netlist including event rules describing the logic. Event rules were tagged with a voltage domain (all the same in these cases), a thermal region corresponding to physical placement, and a flag for thermal-sensitive performance response. Delays and capacitances are based on the logical effort model and calibrated against a TSMC 0.18 micron technology. The simulator accounts for gate and parasitic output capacitances in computing switching energy and delay, but does not account for internal capacitances in transistor stacks. Digital simulation is coupled with a finite-element thermal simulator, where switching circuits inject heat into their respectively mapped thermal regions. For the present purposes, the systems were modeled as a silicon die mounted on an aluminum heat sink in contact with constant temperature air. This simple simulator has the advantage of the fast digital simulation with the added realism of transient thermal effects.
Ring Oscillator
With reference to
Generally speaking, thermally-sensitive delays can be used to limit the maximum frequency of operation of a synchronous block when its frequency is determined by the actual delay of a reference circuit by modifying the reference circuit to include the thermally-sensitive delay element.
Logic Devices
A 5×5 asynchronous field programmable gated array (FPGA), a specific type of asynchronous logic that uses handshaking, running a function-block-intensive benchmark was simulated to demonstrate a circuit transiently reaching a self-heating equilibrium. The design of the particular FPGA simulated is described in J. Teifel and R. Manohar, “Highly pipelined asynchronous FPGAS”, Proceedings of International Symposium on Field Programmable Gate Arrays, February 2004, the contents of which are hereby incorporated by reference. The original design was modified by adding thermally-sensitive inverters to the handshake acknowledges coming from the input buffers of each logic block, resulting in a total of four modified inverters per FPGA tile. (In practice, all four modified sites could even share the same thermally-sensitive voltage source 12 from
The asynchronous FPGA benchmark is a finely-pipelined feed-forward computation and, thus, its performance is expected to be limited by the slowest handshake in the forward path. Since critical cycle was expected to be in the hottest thermal region, the normalized throughput is reported against the peak surface temperature in Table 2. As the temperature of the original FPGA increases, its frequency drops at a rate similar to that of the normal ring oscillator, but not enough to keep from self-heating to destructive temperatures. The thermally-aware FPGA's average surface temperature stabilizes at around 100° C. after 1 millisecond of simulated time at an operating frequency of 27% of the room-temperature throughput.
This FPGA example demonstrates an application where global performance is determined by the hottest spots on the die surface. The data-driven nature of asynchronous designs makes it extremely easy to thermally regulate the performance of the entire system by modifying very few points with thermally-sensitive circuits.
Dynamic Resource Scheduling
The final example presented demonstrates how thermally-sensitive circuits can be used in a method according to an embodiment of the invention to dynamically schedule activity away from hot-spots. Chip dies naturally have nonuniform thermal signatures depending on physical design and dynamic operation characteristics. While synchronous circuits may benefit from a more uniform thermal profile, asynchronous circuits have an additional benefit where high performance may be sustained by scheduling work to cooler units. The entire system need not slow down on account of a single hot-spot.
One simulation run used a heat source with negative-thermal-feedback, so the temperature never exceeded 100° C. Table 3 summarizes the correlation between function unit temperatures (Temp. A and B) and the corresponding number of arbitrated iterations (A and B cycles) for a fixed-size window of time. As unit A 64 approaches the threshold temperature, its acknowledges to the arbiter/dispatcher 62 arrive less frequently. In steady-state (at 99.8° C.), the arbitration ratio is approximately 2:1.
A second simulation run used a heat source without thermal-feedback to demonstrate the effect at even higher temperatures, shown in the bottom part of Table 3. Beyond 100° C., unit A 64 practically stops operating, yielding almost all of the computation work to unit B 66. Once unit A 64 cools down, it will begin to request data from the dispatcher 62 more frequently.
It is to be emphasized that the present invention uses no direct temperature-sensing in arbitration, and is thus, very simple and efficient. No explicit temperature monitoring and scheduling logic is needed to be incorporated into the dispatcher, as might be required if conventional temperature sensors were used to control the scheduling. Proper application of a thermally-sensitive circuit can achieve a simple form temperature-aware resource-scheduling with minimal modifications to an existing asynchronous circuit.
The present invention provides thermally-sensitive circuit that can be used in inventive methods to regulate gate delays in digital circuits. The temperature response of a circuit is first characterized, using one particular set of bias voltages and transistor sizes. Then, a temperature-sensitive voltage source can be constructed that can be used to throttle the speed of selected logic gates. The output of a thermally-sensitive delay element is suitable for digital asynchronous circuits (see Alain 1. Martin. “The limitations to delay-insensitivity in asynchronous circuits”, Proceedings of the 6th Conference on Advanced Research in VLSI, pages 263-278. Massachusetts Institute of Technology, 1990, incorporated herein by reference.) Several applications of the thermally-sensitive transistors in self-regulating the performance of asynchronous circuits in temperature-critical situations have been described.
Of importance is the simplicity of the technique. With only local and minimal modifications to an existing asynchronous circuit, a design can be made thermally-aware and slow itself down without interruption of operation to prevent self-overheating. An asynchronous circuit may even halt and resume operation correctly at an arbitrarily later time later with no additional control circuitry, which makes performance-regulating thermal circuits trivial to apply. The timing robustness alone mitigates the need for additional control circuitry and redesign effort. A small number of strategically placed thermally-sensitive gates is sufficient to regulate the global operating performance across an entire asynchronous system. By significantly slowing down the operation of circuits in hot-spots, it has been shown that the same circuits may be used to dynamically steer work to cooler units, thereby localizing performance regulation and achieving better temperature uniformity.
Although the invention has been described with respect to various embodiments, it should be realized this invention is also capable of a wide variety of further and other embodiments within the spirit of the invention.
