Semi-Flattened Pin Optimization Process for Hierarchical Physical Designs

Abstract

In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter, which is regarded as the invention, is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic block diagram illustrating the hierarchical design of a typical electronic device such as a computer component.

FIG. 2 is a schematic block diagram illustrating the prior art design of a macro in which the input/output pins a located on the periphery of the macro.

FIG. 3 is a flow diagram of the steps in the design of functional block in accordance with the teachings of this invention.

FIG. 4 is a schematic block diagram of the macro shown in FIG. 2 but with input/output pin locations in accordance with the teachings of this invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to FIG. 3 of the drawings, the initial step in the design of a macro in accordance with the teachings of this invention is to set to zero the input/output pin net weights in a suitable prior art computer automated design program used to design functional block macros. The result of this initial step is a synthesized block of leaf cells lc to implement the macro function. As explained above, in prior art synthesized designs, pin placement is determined prior to synthesizing the logical block via the abstract. The synthesis tool uses the abstract fed to it to create a synthesized block that attempts to meet logical and timing constraints based on the pin placement. In the process of this invention, the synthesized block is a result of a zero net weight synthesis resulting in the leaf cells being placed independently of pin locations in the original abstract.

In the next step, the synthesized block is compared with the functional abstract of the macro in order to create a pin grid based on the possible legal pin locations required by the abstract. Next, each required input/output pin is located at a legal pin location that is nearest to the receiving/driving leaf cell that it is intended to serve. It will be appreciated that the original abstract contains more information than just the original pin locations. The power grid locations and wiring contract locations are also contained in the abstract. When determining where to place the pins with respect to the leaf cell location, these aspects must be respected. Legal pin locations are locations exclusive of power grid and wire contact locations. For inputs serving multiple leaf cells, the legal grid point closest to the geometric center of the leaf cells is selected. The final step is the elimination of un-needed re-powering circuitry between the pin and the leaf circuit because of the pin's initial remote position from the leaf circuit. This can be accomplished by re-synthesizing the macro with the pins in the locations developed in the previous step, or by other suitable software programs.

As will be apparent from a comparison of FIGS. 2 and 4, the result is a macro with pin locations that are optimally located with respect to minimizing internal path length and internal signal delay.

The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof.

As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately.

Additionally, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided.

The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.

While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.

Claims

1. In a hierarchal semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement comprising: locating each input terminal providing access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access.

2. In a hierarchal semiconductor digital unit as in claim 1 the improvement further comprising locating each input terminal providing access to a plurality of leaf cells at a legal position proximate the geometric center of said plurality of leaf cells.

3. In a hierarchal semiconductor digital unit as in claim 1 the improvement further comprising locating each output terminal providing access to a leaf cell at a legal location proximate the leaf cell to which the output terminal provides access.

4. In a hierarchal semiconductor digital unit as in claim 2 the improvement further comprising locating each output terminal providing access to a leaf cell at a legal location proximate the leaf cell to which the output terminal provides access.

5. A hierarchal semiconductor digital unit comprising in combination: a plurality of macro functional logic blocks within a perimeter, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal;each input terminal providing access to a single leaf cell located at a legal location inboard of said perimeter proximate the leaf cell to which the input terminal provides access.

6. A hierarchal semiconductor digital unit as in claim 5 further including each input terminal providing access to a plurality of leaf cells located at a legal location inboard of said perimeter proximate the geometric center of said plurality of leaf cells.

7. A hierarchal semiconductor digital unit as in claim 5 further including each output terminal providing access to a leaf cell located at a legal location inboard of said perimeter proximate the leaf cell to which the output terminal provides access.

8. A hierarchal semiconductor digital unit as in claim 6 further including each output terminal providing access to a leaf cell located at a legal location inboard of said perimeter proximate the leaf cell to which the output terminal provides access.

9. A hierarchal semiconductor digital unit as in claim 5 wherein said legal location is nearest the leaf cell to which the input terminal provides access.

10. A hierarchal semiconductor digital unit as in claim 6 wherein said legal location is nearest the geometric center of said plurality of leaf cells.

11. A hierarchal semiconductor digital unit as in claim 7 wherein said legal location is nearest the leaf cell to which the output terminal provides access.

12. A hierarchal semiconductor digital unit as in claim 8 wherein said legal location is nearest the leaf cell to which the output terminal provides access.

13. A method for designing a hierarchal semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said blocks comprised of leaf cells accessed via input/output pins, including the steps of synthesizing each macro functional block without regard to location of said input/output pins;determining a grid of legal input/output pin locations for the macro functional block synthesized in the previous step;locating an input pin that provides access to a single leaf cell at a legal location proximate the leaf cell to which the input pin provides access.

14. A method for designing a hierarchal semiconductor digital unit as in claim 13 including the step of locating an input pin that provides access to a plurality of leaf cells at a legal position proximate the center of said plurality of leaf cells.

15. A method for designing a hierarchal semiconductor digital unit as in claim 13 including the step of locating an output pin that provides access to a leaf cell at a legal location proximate the leaf cell to which the output pin provides access.

16. A method for designing a hierarchal semiconductor digital unit as in claim 14 including the step of locating an output pin that provides access to a leaf cell at a legal location proximate the leaf cell to which the output pin provides access.

17. A method for designing a hierarchal semiconductor digital unit as in claim 13 including the step eliminating re-powering circuitry resulting from the first synthesizing step made un-necessary by the pin location.

18. A method for designing a hierarchal semiconductor digital unit as in claim 14 including the step eliminating re-powering circuitry resulting from the first synthesizing step made un-necessary by the pin location.

19. A method for designing a hierarchal semiconductor digital unit as in claim 15 including the step eliminating re-powering circuitry resulting from the first synthesizing step made un-necessary by the pin locations.

20. A method for designing a hierarchal semiconductor digital unit as in claim 16 including the step eliminating re-powering circuitry resulting from the first synthesizing step made un-necessary by the pin locations.