Semi-physical modeling of HEMT high frequency small signal equivalent circuit models

Abstract

A semi-physical device model for HEMTs that can represent known physical device characteristics and measured high frequency small signal characteristics relatively accurately. The semi-physical device model in accordance with the present invention uses analytical expressions to model the fundamental electric charge and field structure of a HEMT internal structure. These expressions are based on the device physics but are in empirical form. In this way, the model is able to maintain physical dependency with good fidelity while retaining accurate measured-to-modeled DC and small signal characteristics. The model in accordance with the present invention provides model elements for a standard small signal equivalent circuit model of FET. The model elements are derived from small signal excitation analysis of intrinsic charge and electric field as modeled within the device by the semi-physical HEMT model. As such, the RF performance can be predicted at arbitrary bias points.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for modeling semiconductor devices and more particularly to a method for modeling semiconductor devices, such as field effect transistors (FET) and high electron mobility transistors (HEMT) for relatively accurately determining the physical device characteristics and small-signal characteristics to enable the high frequency performance of the device to be forecasted.

2. Description of the Prior Art

HEMT technology provides unparalleled, high-performance characteristics at high frequencies (microwave to millimeter wave). As such, HEMTs are used in various RF applications. In order to accurately forecast the performance of such devices it is necessary accurately model the effect of the components physical structure on its high frequency small signal characteristic. Thus, it is necessary to know how physical changes to the device will effect device performance in order to determine what process changes may be acceptable to improve RF yield product and which may be unacceptable which decrease yield.

Physical changes in such devices are known to occur as a result of various uncontrolled process events, manufacturing equipment changes or intentional process enhancement. Currently two methods for modeling the small signal characteristics of HEMT devices are known: equivalent circuit modeling; and physical device simulation.

Equivalent circuit modeling utilizes networks of linear electrical elements to model the small signal performance of the device. In the case of HEMT devices, a typical equivalent circuit topology is shown in FIG. 1 . This equivalent circuit model is known to accurately model measured S-parameters (small signal characteristics) of HEMT devices up to 120 GHz.

Unfortunately, there is little correlation between the topology of the equivalent circuit and the physical structure of the device. The rough correlation of each equivalent circuit element to a location and function within a typical HEMT structure is shown in FIG. 2 . As such, the small signal models are known to perform well at modeling measured S-parameters but usually contain model elements that drastically diverge from known physical quantities and characteristics. These misrepresentations of the physical device are know to manifest as violations of basic semiconductor device principles. For example, basic device laws dictate that small signal model parameters “scale” in a predictable manner as the periphery is changed. However, most models produced by conventional means become less and less accurate as scaling is applied. As discussed above, small signal characteristics can also be simulated directly from physical device simulators. Such physical device simulators utilize comprehensive data about material characteristics and the basic device physics to simulate the actual physical location and structure of HEMT devices. Such simulators are known to be based upon finite element and Monte Carlo approaches. Such analytical tools are adapted to accept input in the form of the device physical structure, as generally shown in FIGS. 3 , 4 and 5 . In particular, these figures show the typical cross section and the “epi” stack used for physical simulation of specific device structures. In particular, FIG. 3 illustrates a rough scale drawing of a cross section of an exemplary HEMT device. FIG. 4 illustrates how the cross section of information regarding device structure is input into a known physical device simulator tool, such as APDS 1.0 by Agilent. FIG. 5 illustrates how the epi stack information is input into the physical device simulator. FIG. 6 illustrates where the epi stack physically resides within the total device structure.

Since these tools use a physical structure to simulate performance, the correspondence between simulated small signal performance and the device's physical characteristics are relatively strong. However the ability of the device simulators to accurately model real measured small signal characteristics is relatively inaccurate. An example of such results is shown below in Table 1 which provides a comparison of the extracted equivalent circuit model elements using equivalent circuit modeling of measured S-parameter data and the results as modeled using a physical device simulator, for example, using APDS 1.0.

TABLE 1
Comparison of Modeled
Equivalent Circuit Results from Prior Art Methods
Intrinsic Equivalent	Equivalent Circuit	Physical Device
Circuit Parameter	Model	Simulator
Cgs	0.227745 pF	0.1619 pF
Rgs	64242 Ω	infinite Ω
Cgd	0.017019 pF	0.01019 pF
Rgd	133450 Ω	infinite Ω
Cds	0.047544 pF	0.044823 pF
Rds	160.1791 Ω	736 Ω
Gm	135.7568 mS	66 mS
Ri	3.034 Ω	2.304 Ω
Tau	0.443867 pS	1.433 pS

As such, there is a need for a relatively accurate method for relating known physical characteristics of a HEMT device to its measured small signal characteristics. Specifically accurate methods are needed for producing small signal models that are consistent for: measured to model accuracy; physical properties; periphery scaling and bias dependence.

SUMMARY OF THE INVENTION

Briefly the present invention relates to a semi-physical device model that can represent known physical device characteristics and measured small signal characteristics relatively accurately. The semi-physical device model in accordance with the present invention uses analytical expressions to model the fundamental electric charge and field structure of a HEMT internal structure. These expressions are based on the device physics but are in empirical form. In this way, the model is able to maintain physical dependency with good fidelity while retaining accurate measured-to-modeled small signal characteristics. The model in accordance with the present invention provides model elements for a standard small signal equivalent circuit model of FET. The model elements are derived from small signal excitation analysis of intrinsic charge and electric field as modeled within the device by the semi-physical HEMT model. As such, the RF performance can be predicted at arbitrary bias points.

DESCRIPTION OF THE DRAWINGS

These and other advantages of the present invention will be readily understood with reference to the following specification and attached drawings wherein:

FIG. 1 is schematic diagram of an exemplary small signal equivalent circuit model for a HEMT device.

FIG. 2 is a sectional view of an exemplary HEMT illustrating the rough translation of the physical origins for each of the equivalent circuit elements illustrated in the small signal circuit model in FIG. 1 .

FIG. 3 is a cross-sectional view of a HEMT illustrating the regions in the HEMT which correspond to the various circuit elements in the small signal equivalent circuit model illustrated in FIG. 1 .

FIG. 4 is an example of a cross-sectional descriptive input of a physical HEMT device structure by a conventional physical device simulation tool.

FIG. 5 is an example of an epi stack descriptive input of a physical HEMT device structure for a known physical device simulation tool.

FIG. 6 is an example illustrating the location of the epi stack within the device structures cross-sectional view.

FIG. 7 is an example of a relatively accurate measured-to-model I-V characteristics using the semi-physical modeling method in accordance with the present invention.

FIG. 8 is a elevational view illustrating an epi stack for an exemplary HEMT.

FIG. 9 is a cross-sectional view of a HEMT for the exemplary epi stack illustrated in FIG. 8 .

FIG. 10 is a blown up diagram of the cross-sectional parameters pertaining to the T-gate geometry for the exemplary epi stack illustrated in FIG. 8 .

FIG. 11 is a diagram of an electric conductance model used in the semi-physical example.

FIG. 12 is a Smith chart illustrating the measured vs modeled S-parameters S11, S12 and S22 simulated in accordance with the method in accordance with the present invention.

FIG. 13 is similar to FIG. 12 and illustrates the measured vs. modeled values for the S21 parameter.

FIG. 14 is similar to FIG. 12 but for the S12 S-parameter.

FIG. 15 is a graphical illustration of the semi-physically modeled vs measured small signal Gm.

FIG. 16 is a graphical illustration of the semi-physically simulated bias dependence of the small-signal output conductance Rds.

FIG. 17 is a graphical illustration of the semi-physically simulated bias dependence of the small signal gate-source and gate-drain capacitance Cgs and Cgd.

FIG. 18 is a graphical illustration of the semi-physically simulated bias-dependence of the small signal gate source charging resistance Ri.

FIG. 19 is a graphical illustration of the semi-physically bias dependence of the small signal source and drain resistance Rs and Rd.

FIG. 20 is a graphical illustration of the measured vs modeled bias dependent gain at 23.5 Ghz for a K-band MMIC amplifier.

FIG. 21A and 21B are graphical illustrations of the extracted parameters from measured device I-V's for process control monitor testing.

FIG. 22 is a graphical illustration of the measured vs semi-physically simulated process variation for Gmpk and Vgspk.

FIG. 23 is a graphical illustration of the measured vs semi-physically simulated process variation for Idpk and Gmpk.

FIG. 24 is a graphical illustration of the measured vs semi-physically simulated process variation for Imax and Vpo.

FIG. 25 is a graphical illustration of the measured/extracted vs semi-physically simulated process variation for the small signal equivalent model Rds and Gm.

FIG. 26 is a graphical illustration of the measured/extracted vs semi-physically simulated process variation for the small signal equivalent model Cgs and Gm.

FIG. 27 is a graphical illustration of the measured vs semi-physically simulated physical dependence for Imax as a function of physical gate length.

FIG. 28 is a graphical illustration of the measured/extracted model vs semi-physically simulated physical dependence for Rds as a function of physical recess undercut width.

DETAILED DESCRIPTION

The present invention relates to a semi-physical device model which can be used to simulate RF performance through physically-based device models. The semi-physical model is an analytical model based upon empirical expressions that model the physics of HEMT operation, hence the terminology “semi-physical”. The model incorporates real process parameters, such as gate length recess, etch depth, recess undercut dimensions, passivation nitrite thickness, and the like. By using empirical expressions, the semi-physical model is able to maintain relatively good measured to modeled accuracy while accounting for the effects of process variations on the device performance.

The semi-physical model in accordance with the present invention provides model elements for the standard small signal equivalent circuit model or FET as illustrated in FIG. 1 . However, unlike conventional methods, the model elements are derived from small signal excitation analysis of the intrinsic charge and electric fields within the device. As such, the simulated small signal model elements represent a relatively accurate physical equivalent circuit description of a physical FET.

The general methodology for the semi-physical modeling of intrinsic charge, electric conductance and electrical field is as set forth below. First, the relationships between the conduction band offsets and electrical permitivities and material composition for the various materials in the epi stack are determined. These relationships can be performed analytically or by fitting simulated data from physical simulators. Subsequently, the basic electron transport characteristics in any of the applicable bulk materials in the epi stack are determined. Once the electron transport characteristics are determined, the undepleted linear channel mobility is determined either through material characterization or physical simulation. Subsequently, the Schottky barrier height value or expressions are determined. Once the Schottky barrier height value is determined, the semi-physical equations are constructed modeling the following characteristics:

Fundamental-charge control physics for sheet charge in the active channel as controlled by the gate terminal voltage.

Average centroid position of the sheet charge within the active channel width.

Position of charge partitioning boundaries as a function of gate, drain and source terminal voltages.

Bias dependence of linear channel mobility and surface depleted regions.

Bias dependence of the velocity saturating electric field in the channel.

Saturated electron velocity.

Electrical conductance within the linear region of the channel, under the gate.

Electrical conductance within the source and drain access regions.

Once the semi-physical equations are determined, the empirical terms of the semi-physical modeling equations are adjusted to fit the model I-V (current voltage) characteristics against measured values. Subsequently, the empirical terms are interactively readjusted to achieve a simultaneous fit of measured C-V (capacitance-voltage) and I-V characteristics. Lastly, the empirical modeling terms are fixed for future use.

By constructing a comprehensive set of semi-physical equations that cover all of the physical phenomenon as mentioned above, the physical operating mechanisms within a HEMT device can be relatively accurately determined. FIG. 7 illustrates a set of relatively accurate measured-to-modeled I-V characteristics for a HEMT using the semi-physical modeling discussed herein. In particular, FIG. 7 illustrates the drain-to-source current I ds as a function of the drain-to-source voltage V ds for various gate biases, for example, from 0.4V to −1.0V. As shown in FIG. 7 , solid lines are used to represent the semi-physical model while the Xs are used to represent measured values. As shown in FIG. 7 , a close relationship exists between the measured values and the modeled parameters.

An example of semi-physical modeling for physical device operation in accordance with the present invention is provided below. The example utilizes an exemplary device as illustrated in FIGS. 8 and 9 . Table 2 represents exemplary values for the physical cross-section dimension parameters in the model. FIG. 10 relates to a blown up T-gate characteristic which is correlated to the parameters identified in Table 2.

TABLE 2
Values for the Physical Dimension
Parameters Input into Device Cross Section
	Layout Parameter	Units	Value
	Gate Length	Lg	[μm]	0.150
	Wing Length	Lgw	[μm]	0.520
	Gate Mushroom Crown Length	Lgmcl	[μm]	0.200
	Total Gate Height	Hg	[μm]	0.650
	Gate Stem Height	Hgstem	[μm]	0.300
	Gate Sag Height	Hgsag	[μm]	0.100
	Gate Cross-Sectional Area	GateArea	[μm 2 ]	0.187
	Max Cross-Sectional Area	MaxArea	[μm 2 ]	0.364
	Total Gate Penph	Wg	[μm]	200.000
	# Fingers	N	[ ]	4.000
	Source-Drain Spacing	Dsd	[μm]	1.800
	Gate-Source Spacing	Dsg	[μm]	0.700
	Gate-Drain Spacing	Dgd	[μm]	1.100
	Gate-Source Recess	RECsg	[μm]	0.160
	Gate-Drain Recess	RECgd	[μm]	0.240
	Recess Etch Depth	Hrec	[A]	780.000
	SiN Thickness	Hsin	[A]	750.000
	Gatefeed-Mesa Spacing	Dgfm	[μm]	2.000
	Gateend-Mesa Overlap	Dgem	[μm]	2.000
	Finger-Finger Spacing Thru Drain	Dffd	[μm]	16.500
	Finger-Finger Spacing Thru Source	Dffs	[μm]	13.500
	Source Airbridge Inset?	AB?	[ ]	P
	Source Airbridge Inset	Dsabin	[μm]	28.000
	Source Airbridge Height	Hsab	[μm]	3.500
	Source-Gate Airbridge Clearance	Hgsab	[μm]	1.640
	Source Pad Width	Ws	[μm]	12.000
	Drain Pad Width	Wd	[μm]	14.000
	Substrate Thickness	Hsub	[μm]	100.000

As mentioned above, the semi-physical modeling of the intrinsic charge and electric field within the HEMT device is initiated by determining the relationships between the conduction band offset, electrical permitivities and material composition for the various materials in the epi stack. Material composition related band offset and electrical permitivity relationships may be obtained from various references, such as “Physics of Semiconductor Devices”, by Michael Shur, Prentice Hall, Englewood Cliffs, N.J. 1990. The basic electron transport characteristics, for example, for the linear mobility of electron carriers in the bulk GaAs cap layer may be determined to be 1350 cm 2 /Vs, available from “Physics of Semiconductor Devices”, supra. The linear mobility of electron carriers in the undepleted channels is assumed to be 5500 cm 2 /Vs. This value may be measured by Hall effect samples which have epi stacks grown identically to the stack in the example, except for some differences in the GaAs cap layer. The Schottky barrier height is assumed to be 1.051 volts, which is typical of platinum metal on a AlGaAs material.

The following equations represent the semi-physical analytical expressions to model the charge control and centroid position in the sample.

Empirical Charge Control Expression	N s	[cm −2 ]	= N s ′/
			[1 + (N s ′/N max ) γ )] 1/γ
Ideal Charge Control with Filling Law	N s ′	[cm −2 ]	= 2 N o In [1 + exp(V gt /(η V th ))]
Ideal Charge Control	N o	[cm −2 ]	= εi η V th /[2 q (d i + Δd i ) 10000]
Maximum Channel Charge	N max	[cm −2 ]	= (N max0 + N maxL V ds nnmax
			H chan /H chanREF )
Initial Gate-Channel Voltage	V gt	[V]	= [V gs − Φ b = ΔE c − V TO − σV ds
Threshold Voltage	V TO	[V]	= Φ b − ΔE c − V T
Doping Threshold Voltage	V T	[V]	= q N sdelta d δ 10000/ εi
Gate-to-Channel Spacing	d i	[m]	= {(H space + H bar + H fdope + H cap ) − H rec )/
			(10 10 )
	note that the expression for di can be changed for different epi-stacks
Movement of Sheet Carrier Centroid	Δ d i	[m]	= H chan [1 = d lK *V gte /H chanREF −
			d iL · V ds /H chanREF ]
Empirical Charge Control Shaping Parameter	γ	[]
Semi-Physical Subthreshold Populating Rate	η	[]
Dielectric Permitivity of the Barrier Layer	ε i	[F/m]
The thermal voltage	V th	[V]	= K B T amb /q
Ambient Temperature	T amb	[K]
Fixed Emprical Maximum Sheet Charge	N max0	[cm −2 ]
Vds Dependent Emprical Maximum Sheet Charge	N maxL	[cm −2 ]
Vds Dependent Emprical Nmax shaping term	n Nmax	[]
Channel Layer Thickness	H chan	[A]
Reference Channel Layer Thickness	H chanREF	[A]
	(Channel Thickness for the sample for which the model was
	first derived)
Schottky Barrier Height	Φ B	[V]
Conduction Band Offset between Channel and Barrier	Δ E C	[V]
Front Delta Doping	N Sdelta	[cm −2 ]
	note that this expression can be modified for non-delta
	doped epi-stacks
Gate-to-Front Delta Doping Spacing	dδ	[m]	= {(H bar + H fdope + H cap ) − H rec }/ (10 10 )
Barrier Thickness between front doping and channel	H space	[A]
Barrier Layer Thickness before front doping layer	H bar	[A]
Front Doping layer thickness	H fdope	[A]
Cap layer thickness	H cap	[A]
Empirical Drain-Induced Barrier-Lowering Term	σ	[]
Sheet Charge Position Gate Bias Factor	d lK	[A/V]
Sheet Charge Position Drain Bias Factor	d lL	[A/V]
Effective Gate Voltage	V gte	[V]	= V th [1 + V gt /2V th +
			sqrt(δ 2 + (V gt /2V th − 1) 2 ]
Empirical Transition Width Parameter	δ	[]

As used herein, Ns represents the model sheet carrier concentration within the active channel. Ns′ represents the ideal charge control law and is modeled as a semi-physical representative of the actual density of state filling rate for energy states within the channel v. gate voltage. The gate-to-channel voltage used for the charge control, Vgt, is a function of the Schottky barrier height, conduction band offsets and doping in the epi stack as is known in the art. The following equations represent the semi-physical expression used to model the position of regional charge boundaries within the HEMT device. These expressions govern how to partition the model charge between the influence of different terminals.

Effective Gate Length	L geff	[ μ m]	= L g + Δ L s + Δ L d
Gate-Source Control Region	L gs	[ μ m]	= L g /2 + Δ L s + X D1
Source-Side Effective Gate Length Extension	Δ L x	[ μ m]	= Δ L s0 + Δ L K * V gte
Drain-Side Effective Gate Length Extension	Δ L d	[ μ m]	= Δ L d0 + Δ LK * V gte + Δ L L * V dse2
Gate-Drain Control Region	L gd	[ μ m]	= (L g /2 + Δ L d ) * {tanh [10(L g /2 − X D1 )]+ 1}/2
Bias Dependent Extension of the Saturated Transport Region	X D1	[ μ m]	= X DL V ds M XdL /
			{M XdK V gfe *(1 + [X DL V ds M Xdl /
			(M XdK V gte (L g /2 + REC gd ))] m } 1/m
Empirical Drain-Saturated Transport Boundary Factor	X DL	[ μ m]	= L g V ds /{2[1 + (V ds /V saten ) m ] (1/m) }
Position of the Boundary between Regions 1 and 2	X S	[ μ m]	= X s0 {M Xs [1/(1 + (V ds /V satn) m } (1/m) −
			V ds m(V ds /V satn ) (m−1) /
			{V satn m[1 + (V ds /V satn ) m ] (1/m+1) }] −
			V ds M XsL + V gte M XsK }
Note: Region 1 denotes the inner region, while Region 2 denotes the saturated region of the channel
Empirical Effective Gate Length Extension Gate Bias Factor	Δ L K	[ μ m/V]
Empirical Effective Gate Length Extension Drain Bias Factor	Δ L L	[ μ m/V]
Effective Drain-Source Voltage Control-2	V dse2	[V]	= V ds /0 [1 + (V ds /V satn ) m ] 1/m
Rough, Intrinsic Saturation Voltage	V satn	[V]	= I sat /g chi
Rough, Intrinsic Saturation Current Level	I sat	[A]	= g chi V gte /
			[1 + g chi R s + sprt(1 + 2g chi R s + (V gte /V L ) 2 )]
Intrinsic Conductance of the Linear Region, Under the gate	g chi	[S]	= (q N 3 μ ave Wg)/Lg
Rough Intrinsic Saturation Voltage Level	V L	[V]	= F s * L g
Empirical Knee Shaping Parameter	m	[]
Empirical Region 2 extension Drain Bias Factor	M XdL	[]
Empirical Region 2 extension Gate Bias Factor	M XdK	[]
Fine Intrinsic Saturation Voltage	V saten	[V]	= I satoom /g chi
Fine Intrinsic Saturation Current Level	I satcom	[A]	= g chi V gte V L * [−V L (A + g chi R s ) +
			sqrt(V L 2 (A + g chi R s ) 2 + V gte 2 − (g chi R s V L ) 2 )]/
			[V gte 2 (1 − g chi R s (V L /V gte ) 2 )]
Saturation Region Length Ratio	A	[]	= X s /L geff
Initial Starting position for Region 1 & 2 Boundary	X s0	[ μ m]	= Lg/2
Region 1 & 2 Boundary Bias Factor	M Xs	[]
Region 1 & 2 Boundary Drain Bias Factor	M XsL	[]
Region 1 & 2 Boundary Drain Bias Factor	M XsK	[]

The following equations represent the semi-physical expressions used to model the bias dependence of linear channel mobility in depleted regions.

Depleted Channel Mobility	μave	[cm 2 /V*s]	= μ dchan + μ dK* V gte
Fixed Depleted Channel Mobility	μdchan	[cm 2 /V*s]
Depleted Channel Mobility Gate Bias Factor	μdK	[cm 2 /V 2 *s]

The following equations are the semi-physical expressions used to model the bias dependence of the saturating electric field and saturation velocity.

Saturating Electric Field	F S	[V/ μ m]	= v s /
			[(μ sat + μ satK V gte )10000]
Fixed Saturating Channel Mobility	μsat	[cm 2 /V*s]
Saturating Channel Mobility Gate Bias Factor	μsatK	[cm 2 /V 2 *s]
Saturation Velocity	V s	[cm/s]

FIG. 11 is a schematically illustrates how electrical conductance in the source and drain access regions are modeled in the example.

The following equations describe the semi-physical expressions for the source access region conductance:

Source Accesa Resistance	R S	[Ω]	= (R SundepCap + R SAccess + R SBoundary )/W g
Source Access Resistance: Channel and Cap	R SundepCap	[Ω* μ m]	= R cont /RF rconF +
			R SH [D sg · (REC sg + L g /2)]
Source Access Resistance. Recess and Undepleted Cap	R SAccess	[Ω* μ m]	= R SdepRec ON * MR s *tanh{[KC fK *
			(V gs = VC fOn + V ds *MC fL )]+ 1{/2* {V gs /
			2*[1-tanh(KR sK (V gs − VR sOn ))]}* {tanh
			[KR sSat (V ds − VR sKnee )] + 1}/2 + R SundepRec * {tanh
			[KR sK (V gs − VR sOn )]+ 1}/2
Source Access Resistance:	R SBoundary	[Ω· μ m]	= R SdepRec ON * MR s * tanh {[KR sK *V gs + KR sL *V ds +
Crowding resistance due to conductance mismatch			VR sOff ] + 1}/2* {(1 + V ds MR sL )*MR sK *[1 −
			tanh(KR sSat (V ds · VR sKnee ))]/ [2*(1 + [V gs /((1 +
			V ds MR sL )*MR sK)] Rs ) (1/γRs) ]}
Resistance of the Source Recess Access region	R SdepRec ON	[Ω* μ m]	= R SHdep (REC sg )
at high on-state bias (V on )
Resistance of the Undepleted Source Recess Access region	R SundepRec	[Ω* μ m]	= R SHundep (REC sg )
Uncapped, Fully Depleted Sheet Resistance	R SHdep	[Ω/sq]	= 1/(q N max μ ave )
Capped, Undepleted Sheet Resistance	R SH	[Ω/sq]	= 1/(1/R SHCap + 1/R SHundep )
Uncapped, Undepleted Sheet Resistance	R SHundep	[Ω/sq]	= F surfUndep /(q N max μ undchan )
Cap Sheet Resistance	R SHCap	[Ω/sq]	= 1/[q N sCap μ cap (H cap − H capEtch )]
Surface Depletion Factor	F surfUndep	[]
High On-state bias: Diode Turn-on voltage	V ON	[V]	= Φ b − ΔE c − ΔE f
Ohmic Contact Resistance	R cont	[Ω* μ m]
RF Ohmic Contact Resistance Reduction Factor	RF rconF	[]
Source Access Resistance Bias Modification Factor	MR s	[]
Cf-Vds Bias Modification Factor	MC fL	[]
Rs-Vds Bias Modification Factor	MR sL	[]
Rs-Vga Bias Modification Factor	MR sK	[]
Cf-Vga Swith point to On-state	VC fOn	[]
Cf-Vgs Bias Expansion Factor	KC fK	[]
Rs-Vga Swith point to On-state	VR SOn	[]
Rs-Vga Swith point to Off-state	VR SOff	[]
Rs-Vds Swith point from Off-On transition	VR SKnee	[]
Rs-Vds Bias Expansion Factor	KR sL	[]
Rs-Vgs Bias Expansion Factor	KR sK	[]
Rs-Vds Bias Expansion Factor @ Rs Saturation	KR sSat	[]
Rs Bias Shaping Factor	γ R s	[]

The following equations describe the drain access region conductance:

Drain Access Resistance	R D	[Ω]	= (R DRF + R DN )
Drain Access Resistance, except for recess access	R DRF	[Ω]	= (R DAccess + R Dundepcap + R DundepRec + R DSaturated )/W g −
			R DN
Drain Recess Access Resistance	R DN	[Ω]	= (R DRec )/W g
Drain Access Resistance: Recess snd Undepleted Cap	R DAccess	[Ω* μ m]	= R DdepRec ON (MR d *V gs + 1)[1 −
			tanh[KR daccK *[V gs − VR dOn + V ds *MR daccL]}]/2
Drain Access Resistance: Channel and Cap	R DundepCap	[Ω* μ m]	= R cont /RF ronF + R SH [D gd ·
			(REC gd + L g /2)]
Resistance of the Undepleted Drain Recess Access region	R DundepRec	[Ω* μ m]	= R SHundep (REC gd )
Resistance of the Saturated Drain Recess Access region	R DSaturated	[Ω* μ m]	= MR dSat *V ds exp {− [V gs + V ds *MR dL + VR dSatOff] 2 / (2
			VR dSatσ )}/{VR dSat [1 + (V ds /VR dSat ) γRd ] (γRdA+1/γRd) }
Resistance of the Drain Recess Access region	R DdepRec ON	[Ω* μ m]	= R SHdep REC gd )
at high on-state bias (V on )
	R DRec	[Ω* μ m]	= δ VL {1 + (R DAccess − R DundepCap )/(2δ VL ) + sqrt[δ 2 +
			((R DAccess − R DundepCap )/(2δ VL ) − 1) 2 ]}
Drain Access Resistance Bias Modification Factor	MR d	[]
Rd-Vds Access Bias Modification Factor	MR accL	[]
Rd-Vgs Swith point to On-state	VR dOn	[]
Rd-Vgs Swith point at saturation	VR dSat	[]
Rdaccess-Vgs Bias Expansion Factor	KR daccK	[]
Rd-Vds Saturation Bias Modification Factor	MR dSat	[]
Rd-Vds Access Resistance Bias Modification Factor	MR dL	[]
Rd-Vgs Saturation Swith point to Off-state	VR dSatOff	[]
Rd-Vgs Saturation Swith point	VR dSat	[]
Rd-Vgs Saturation Swith point transition width	VR dSatσ	[]
Rd Bias Shaping Factor	γ R d	[]

Semi-Physical Determination of Small-Signal Equivalent Circuits

To derive values for the familiar small signal equivalent circuit as shown in FIG. 1 , a small signal excitation analysis must be applied to the semi-physically modeled physical expressions. The method of applying such an analysis is as follows:

1) Gate Terminal Voltage Excitation

Apply a small+/− voltage delta around the desired bias condition, across the gate-source terminals.

Equivalent circuit element Gm=delta(Ids)/delta (Vgs′) where delta (Vgs′) is mostly the applied voltage deltas, but also subtracting out that voltage which is dropped across the gate source access region, shown as RsCont, RsundepCap, RsundepRec, ResdepRec, and RsBoundary in FIG. 11 , above.

Equivalent circuit element Cgs and Cgd takes the form of delta(Nsn)/delta(Vgs)*Lgn, where delta (Nsn) is the appropriate charge control expression, and Lgn is the gate source or gate drain charge partitioning boundary length.

Equivalent circuit element Ri=Lgs/(Cgschannel*vs) where Cgs channel is the portion of gate source capacitance attributed to the channel only, and vs is the saturated electron velocity.

2) Drain Terminal Voltage Excitation

Apply a small +/− voltage delta around te same bias condition as in 1, but the delta is applied across drain source terminals.

Equivalent circuit element Rds=1/{delta(Ids)/delta(Vds′)} where Vds′ is mostly the applied voltage deltas, but also subtracting out voltage which is dropped over both the gate source and gate drain access regions.

Equivalent circuit element Cds is taken to be the sum of the appropriate fringing capacitance Semi-Physical models, or can take the form of delta(Nsd)/delta(Vds′)*Xsat, were Nsd is the charge control expression for charge accumulation between the appropriate source and drain charge boundaries, and Xsat is the length of the saturated region, if in saturation.

3) On-mesa Parasitic Elements: The equivalent circuit elements, Rs and Rd are expressed by the appropriate electrical conduction models of the source and drain access regions.

The RF performance can be predicted at an arbitrary bias point.

Table 4 represents a comparison of the values for a high frequency equivalent circuit model derived from equivalent circuit model extraction from and semi-physical modeling for the sample illustrated in Table 2.

TABLE 3
Comparison of Modeled Equivalent Circuit Results for Semi-physical
Modeling Method, and Equivalent Circuit Model Extraction
Intrinsic Equivalent	Equivalent Circuit	Semi-Physical
Circuit Parameter	Model	Device Model
Cgs	0.227745 pF	0.182 pF
Rgs	64242 Ω	infinite Ω
Cgd	0.017019 pF	0.020 pF
Rgd	133450 Ω	infinite Ω
Cds	0.047544 pF	0.033 pF
Rds	160.1791 Ω	178.1 Ω
Gm	135.7568 mS	124 mS
Ri	3.034 Ω	2.553 Ω
Tau	0.443867 pS	0.33 pS

The results of the semi-physical modeling method produce a small-signal equivalent circuit values which are relatively more accurate than the physical device simulator in this case. Furthermore, given the differences in the parasitic embedding, treatment of the two approaches, the results given in Table 3 yield much closer results than a comparison of equivalent circuit values.

Table 4 lists the values of parasitic elements used in the model derivations. An important difference between the extracted equivalent circuit model and the semi-physically derived one is the use of Cpg and Cpd to model the effect of launch capacitance for the tested structure. This difference leads to the results of the extracted model results being slightly off from the optimum physically significant solution.

TABLE 4
Comparison of Modeled “Parasitic” Equivalent Circuit Results for Semi-
physical Modeling Method, and Equivalent Circuit Model Extraction
Extrinsic Equivalent	Equivalent	Semi-Physical
Circuit Parameter	Circuit Model	Device Model
Rg	1.678 Ω	1.7 Ω
Lg	0.029314 nH	0.03 nH
Rs	1.7 Ω	1.21 Ω
Ls	0.002104 nH	0.003 nH
Rd	3.309899 Ω	5.07 Ω
Ld	0.031671 nH	0.02 nH
Cpg	0 pF	0.02 pF
Cpd	0 pF	0.01 pF

As shown in FIGS. 12 , 13 and 14 , the modeled results that are simulated using the semi-physically derived equivalent circuit model very accurately replicate the measured high frequency, S-parameter data.

The following equations represent the small-signal excitation derivation of a small-signal equivalent circuit modeled Gm. FIG. 15 . illustrates the semi-physically simulated bias equations of the small signal Gm compared to measured data.

Semi-Physically Modeled Drain-Source Current Control	I ds	[A]	= g ch V ds (1 + λV ds )/
			[1 + (V ds /V sate ) m ] 1/m
Small-Signal Deterimination of equiv. Circuit Gm value	g mRF	[S]	= dl ds /d(V gs − V sAcc )
Source-Access voltage drop	V SAcc	[V]	= I dsW *(R SUndepCap + R SAccess +
			R SBoundary +R probeS /W g )
Fine Extrinsic Saturation Voltage	V sate	[V]	= I satcom /g ch
Extrinsic Conductance of the Linear Region, Under the gate	g ch	[S]	= g chi /
			[1 + g chi (R S + R d )]
Intrinsic Conductance of the Linear Region, Under the gate	g chi	[S]	= (q N x μ ave W g )/L g

The following equations represent the small-signal excitation derivation of Rds. FIG. 16 illustrates the semi-physically simulated bias-dependence of the small-signal Rds.

Small-Signal Deterimination of equiv. Circuit Rds value	R ds	[Ω]	= 1/g dsRF
	g dsRF	[S]	= {dl ds /d(V ds − R probeD * I ds − V sAcc − V dAcc V dSat )}
			*r dsF
Drain-Access voltage drop	V DAcc	[V]	= I dsW *(R DundepCap + R DUndepRec + R DAccess +
			R probeD /W g )
Drain-Saturated Region voltage drop	V DSAT	[V]	= I dsW *(R DSaturated )
External Test probe or lead resistance	R probeD	[Ω]
High Frequency conductance dispersion factor	r dSF	[]	= (RF rdsF + 1)*
			tanh(10 *|V ds − V th |) + 1
High Frequency conductance dispersion	RF rdsF	[]

The following equations may be used for the small-signal excitation derivation of Cgs and Cgd. FIG. 17 illustrates the semi-physically simulated bias-dependence of the small-signal Cgs and Cgd.

Small-Signal Deterimination of equiv. Circuit Cgs value	C gs	[fF/ μ m]	= C gsf + β C gcTot L gs *
			{1 − [(V saten − V dse )/(2*V saten − V dse )] 2 }
	C gd	[fF/ μ m]	= C gdf + β C gcTot L gd *
			{1 − [V saten /(2*V saten − V dse )] 2 }
Parasitic Gate-Source Fringing Capacitance	C gst	[fF/ μ m]	= Cg surf C f-form1 SiNF + Cgsf Source + Cgsf Pad
Parasitic Gate-Source Fringing Capacitance	C gdf	[fF/ μ m]	= Cg surf C f-form1 SiNF + Cgdf Cap + C gdf Pad
Total Specific Gate-Channel Capacitance	C gcTot	[fF/ μ m]	= C gc + C gcdonor
Specific Gate-Channel Capacitance	C gc	[fF/ μ M 2 ]	=c gc Msh Kchan /
			{[1 + (N s ′/(N 0 + N max0c ) γc ) (1+1/γc) ]}
Effective Drain-Source Voltage Control	V dse	[V]	= V ds /[1 + (V ds /V saten ) m ] 1/m
Specific Gate-Donor Layer Accumulation Capacitance	C gcdonor	[fF/ μ m 2 ]	= q dN sDonor /dV gs
Ideal Specific Gate-Channel Capacitance	c gc	[fF/ μ m 2 ]	= qdN s ′/dV gs
Empirical Parasitic Donor Charge Control Expression	N sDonor	[cm −2 ]	= (N s ′+ N s )*(d l + Δd l )Msh Kpar * V gte /
			(d l + Δd l )
Fringing capacitance to surface of source-access region	C gsurf	[fF/ μ m]
Empirical Fringing capacitance-bias shaping expression	C f-form1	[]	= {1 − tanh[KC fK(V gs − VC fOn + V ds MC fl )]}/2
Fringing capacitance to source-access region	C gsfSource	[fF/ μ m]
Fringing capacitance to source metal pads	C gsfPad	[fF/ μ m]
Fringing capacitance to drain-access Capped Region	C gdfCap	[fF/ μ m]
Fringing capacitance to drain metal pads	C gdfPad	[fF/ μ m]
Dielectric Coating Thickness Factor	SiNF	[]
Specific Gate-Channel Capacitance Bias ModificationFactor	Msh Kcahn	[]
Donor Charge Bias Modification Factor	Msh Kcahn	[]
Empirical Specific Charge Control Shaping Parameter	γ C	[]

The following equations are involved in the small-signal excitation derivation of Ri. FIG. 18 , which follows, shows the semi-physically simulated bias-dependence of the small-signal Ri.

Gate-Source Non-quasistatic charging resistance	R icharge	[Ω* μm]	= L gs2 W g /[C gsChan W g v s ]
Gate-Channel Source Capacitance	C gsChan	[fF/ μ m]	= C gsf + β C gc L gs *
			{1 − [V saten − V dse )/(2*V saten − V dse )] 2 }

FIG. 19 below shows the semi-physically simulated bias-dependence of the on-mesa parasitic access resistances, Rs and Rd.

Example of Semi-Physical Model and Bias-Dependence Small-Signal Source and Drain Resistance, RS AND RD

The following example verifies how the semi-physical small-signal device model is able to provide accurate projections for bias-dependent small-signal performance. In this example, the same semi-physical device model as used in the previous examples was used because the example MMIC circuit was fabricated utilizing the same HEMT device technology.

In this example, the bias-dependence small-signal gain and noise performance of a two-stage balanced K-band MMIC LNA amplifier is replicated through microwave circuit simulation using small signal and noise equivalent circuits that were generated by the semi-physical model. The results of the measured and modeled results are shown below in Table 5. As seen from these results, the semi-physical device model was able to accurately simulate the measured bias-dependent performance, even though the bias variation was quite wide.

TABLE 5
Measured vs. Modeled Gain NF and Gain @ 23.5 Ghz for
K-band MMIC LNA at Difference Bias Conditions
	Measured	Predicted	Measured
	Gain	Gain	NF	Predicted NF
Bias Condition	@ 23.5 GHz	@ 23.5 GHz	@ 23.5 GHz	@ 23.5 GHz
Vds = 0.5 V	15.2 dB	15.8 dB	2.97 dB	2.77 dB
112 mA/mm
Vds = 1.0 V	20.6 dB	21.0 dB	2.29 dB	2.20 dB
112 mA/mm
Vds = 2.0 V	19.8 dB	20.2 dB	2.25 dB	2.15 dB
112 mA/mm
Vds = 3.0 V	18.9 dB	19.1 dB	2.30 dB	2.11 dB
112 mA/mm
Vds = 3.5 V	18.4 dB	18.5 dB	2.34 dB	2.18 dB
112 mA/mm
Vds = 4.0 V	18.0 dB	18.0 dB	2.37 dB	2.27 dB
112 mA/mm
Vds = 2.0 V	16.4 dB	18.0 dB	2.45 dB	2.21 dB
56 mA/mm
Vds = 2.0 V	21.4 dB	20.9 dB	2.38 dB	2.21 dB
170 mA/mm
Vds = 2.0 V	22.2 dB	21.0 dB	2.65 dB	2.6 dB
225 mA/mm
Vds = 3.0 V	21.4 dB	20.3 dB	2.71 dB	2.61 dB
225 mA/mm
Vds = 3.0 V	20.5 dB	20.0 dB	2.42 dB	2.22 dB
170 mA/mm
Vds = 4.0 V	19.6 dB	19.2 dB	2.50 dB	2.29 dB
170 mA/mm

A plot of measured vs. modeled gain for the values listed in Table 5, above, is shown in FIG. 20 .

The following example verifies how the semi-physical small-signal device model is able to provide accurate projections for physically dependent small-signal performance. In this example, the same semi-physical device model as used in the previous examples was used.

In this example, physical process variation was input into the semi-physical device model in terms of statistical variation about known averages, cross-correlation, and standard deviations. The goal of this exercise was to replicate the measured DC and small-signal device variation. The degree of accurate replication indicates the degree to which the semi-physical model is physically accurate.

Table 6 below lists the simulated, and known process variation that was used:

TABLE 6
Statistical Process Variation Model
	Parameter	Nominal	Standard Dev.
	Gate Length	0.15 μm	0.01 μm
	Gate-Source Recess	0.16 μm	0.015 μm
	Gate-Drain Recess	0.24 μm	0.020 μm
	Etch Depth	780 A	25 A
	Pass. Nitride Thickness	750 A	25 A
	Gate-Source Spacing	0.7 μm	0.1 μm
	Source-Drain Spacing	1.8 μm	0.15 μm

In the course of microelectronic component production, sample devices are tested in process in order to gain statistical process control monitor (PCM) data. FIGS. 21A and 21B show schematically the kind of data that is extracted and recorded from measured device I-V's during PCM testing.

Since the semi-physical device model is able to simulate I-V's, it was able to simulate the variation of I-V's due to physical process variation. These I-V's were analyzed in the same fashion to extract the same parameters that are recorded for PCM testing. FIGS. 22 , 23 , and 24 show how accurately the simulated results match with measured process variation. FIG. 19 shows how the semi-physically simulated Vgpk and Gmpk match with actual production measurements. FIG. 20 shows how simulated Idpk and Gmpk match, also. Finally, FIGS. 21A and 21B show how the simulated Imax and Vpo also match very well.

Small-signal S-parameter measurements are also taken in process for process control monitoring. These measurements are used to extract simple equivalent circuit models that fit the measured S-parameters. Since the semi-physical device model is able to simulate these equivalent circuit models, it was able to simulate the variation of model parameters due to physical process variation.

FIGS. 25 , and 26 show how accurately the simulated results match with measured/extracted process variation for the small-signal model parameters. FIG. 25 shows how the semi-physically simulated Rds and Gm match very well with actual extracted model process variation

More direct and convincing evidence supporting the accurate, physical nature of the semi-physical model can be shown be comparing the dependence of simulated and measured performance to real physical variable. As shown in FIG. 27 , the semi-physical model is able to very accurately reproduce the dependence of Imax upon gate length. In addition, the semi-physical model is also able to replicate physical dependence for high-frequency small-signal equivalent circuits. This is shown in FIG. 28 , which shows that it is able to reproduce the dependence of Rds with Recess undercut width.

Obviously, many modifications and variations of the present invention are possible in light of the above teachings. Thus, it is to be understood that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described above.

Claims

1. A method of modeling a semiconductor device comprising the steps of:a) modeling a small signal electrical equivalent circuit for said semiconductor device which includes a plurality of electrical circuit elements defining a small signal model, said small signal equivalent circuit based in part on one or more real process parameters; b) deriving said electrical circuit elements at least in part from a small signal excitation analysis of at least one of the intrinsic charge and electrical field characteristics of said semiconductor device, wherein said real process parameters include at least one of: gate length recess, etch depth, recess undercut dimensions and passivation nitrite thickness.

2. The method as recited in claim 1, wherein said real process parameters further include: gate-source recess, gate-drain recess, gate-source spacing and source-drain spacing.

3. The method as recited in claim 1, wherein step (b) includes the step of:(c) determining the relationships between one or more conduction band offsets and electrical permitivities and the material composition for the materials in the semiconductor device.

4. The method as recited in claim 3, wherein said semiconductor device model is based at least in part as a function of one or more of: conduction band offsets; electrical permitivities; and material composition of the epi stack.

5. The method as recited in claim 3, wherein said semiconductor device is a high electron mobility transistor (HEMT).

6. The method as recited in claim 3, wherein said semiconductor device is a field effect transistor (FET).

7. The method as recited in claim 3, wherein step (c) is determined analytically.

8. The method as recited in claim 7, wherein step (c) is determined by fitting simulated data.

9. The method as recited in claim 3, further including step (d); determining the electron transport characteristics of any bulk materials in the semiconductor device.

10. The method as recited in claim 9, further including step (e); determining an undepleted linear channel mobility.

11. The method as recited in claim 10, wherein step (e) is determined by material characterization.

12. The method as recited in claim 10, wherein step (e) is determined by physical simulation.

13. The method as recited in claim 10, further including step (f) determining the Schottky barrier height expressions.

14. A method of modeling a semiconductor device comprising the steps of:(a) modeling a small signal on an electrical equivalent circuit for said semiconductor device with a plurality of electrical circuit elements defining a small signal model; deriving said electrical circuit elements from a small signal excitation analysis of the intrinsic charge within said semiconductor device by determining the relationships between one or more of the conduction band offsets and electrical permitivities and the material composition for the materials in the semiconductor device; determining the electron transport characteristics of any bulk materials in the semiconductor device; determining an undepleted linear channel mobility; forming semiconductor physical equations with empirical terms for modeling one or more of the following characteristics: fundamental-charge control physics for sheet charge in an active channel as controlled by a gate terminal voltage; average centroid position of the sheet charge within the active channel width; position of charge partitioning boundaries as a function of gate, drain and source terminal voltages; bias dependence of linear channel mobility and surface depleted regions; bias dependence of a velocity saturating electric field of the channel; saturated electron velocity; electrical conductance within the linear region of the channel, under the gate; electrical conductance within the source and drain access regions.

15. The method as recited in claim 14, further including step (i):adjusting the empirical terms of the semi-physical equations to fit the model current-voltage (I-V) characteristics relative to measured values.

16. The method as recited in claim 15, further including steps (j):iteratively readjusting the empirical terms to achieve a simultaneous fit of measured capacitance voltage (C-V) and I-V characteristics.