Patent Application
20230411402
The present invention relates to a semiconductor apparatus.
There has been a technique of varying constituent elements of semiconductor layers of transistors disposed on the same substrate. Patent Document (PTL) 1 discusses a semiconductor apparatus that uses a thin-film transistor (TFT) including polysilicon and another TFT including an oxide semiconductor layer. Patent Document (PTL) 2 discusses a semiconductor apparatus including a first top-gate thin-film transistor using a polycrystal silicon layer as a channel, and a second top-gate thin-film transistor using an oxide semiconductor layer as another channel. In the semiconductor apparatus discussed in (PTL) 2, a common metal layer is used as a source and a drain of the first top-gate thin-film transistor, and a gate of the second top-gate thin-film transistor.
In the technique discussed in PTL 1, consideration of cost reduction is not enough. The effect obtainable with the technique discussed in PTL 2 is applicable only in a limited structure. Thus, the present invention is directed to providing a technique advantageous in reducing cost of a semiconductor apparatus.
In a first aspect of a semiconductor apparatus according to the present invention, the semiconductor apparatus includes a substrate, a first semiconductor layer that is of a first transistor and disposed above the substrate, a first conductor layer disposed above the substrate and overlapping the first semiconductor layer, a second semiconductor layer that is of a second transistor and disposed above the substrate, and a second conductor layer disposed above the substrate and overlapping the second semiconductor layer, wherein a first element with a highest concentration in the first semiconductor layer among elements of Groups 12 to 16 included in the first semiconductor layer differs from a second element with a highest concentration in the second semiconductor layer among elements of Groups 12 to 16 included in the second semiconductor layer, wherein a third element with a highest concentration in the first conductor layer among metal elements or metalloid elements included in the first conductor layer is same as a fourth element with a highest concentration in the second conductor layer among metal elements or metalloid elements included in the second conductor layer, wherein the first conductor layer is in contact with the first semiconductor layer, wherein the second conductor layer is insulated from the second semiconductor layer, wherein the second conductor layer is disposed between the second semiconductor layer and the substrate, and wherein the second conductor layer is contiguous to the first conductor layer.
In the semiconductor apparatus according to a second aspect of the present invention, the second conductor layer is disposed between the second semiconductor layer and the substrate. A third aspect is that a third conductor layer disposed above the substrate and overlapping the second conductor layer is not in contact with the second semiconductor layer and is insulated from the second conductor layer. A fourth aspect is that the first transistor is of a P-type and the second transistor is of an N-type.
Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.
Hereinafter, a mode for carrying out the present invention will be described with reference to the drawing. In the following description and drawings, configurations illustrated in common in a plurality of drawings are assigned the same reference numerals. The common configurations will be sometimes described with reference to the plurality of drawings without notice. In addition, the description of the configurations assigned the same reference numerals is sometimes omitted. Different components with the same name can be distinguished from each other by allocating “n-th” (n is a number”) like a first component and a second component. In this specification, a case where A and B correspond to either C or D means any of a case where A and B correspond to C, a case where A and B correspond to D, a case where A corresponds to C and B corresponds to D, and a case where A corresponds to D and B corresponds to C.
The transistor 10 is disposed in at least either the pixel region 2 or the peripheral region 3. The transistor 20 is disposed in at least either the pixel region 2 or the peripheral region 3. Here, an example in which the transistors 10 are disposed in the pixel region 2 and the peripheral region 3, and the transistor 20 is disposed in the pixel region 2 is illustrated. In addition, a transistor 30 is disposed in the peripheral region 3 together with the transistor 10. The transistor 10 in the peripheral region 3 and the transistor 30 in the peripheral region 3 may together form a complementary integrated circuit, such as a complementary metal-oxide semiconductor (CMOS) circuit. In the complementary integrated circuit, the transistor 10 may be a P-type transistor and the transistor 30 may be an N-type transistor. Alternatively, in the complementary integrated circuit, the transistor 10 can be an N-type transistor and the transistor 30 can be a P-type transistor. While the transistor 10 may be whichever of an N-type transistor and a P-type transistor, it is desirable that the transistor 10 is an N-type transistor because an electron mobility is generally higher than a hole mobility. While the transistor 20 may be whichever of an N-type transistor and a P-type transistor, it is desirable that the transistor is an N-type transistor sing an electron mobility is generally higher than a hole mobility.
In the pixel region 2, a functional element 200 is disposed above the transistor (and the transistor 10). The functional element 200 is an element, such as a liquid crystal element, a light-emitting element, or a photoelectric conversion element, that is generally included in a pixel. The functional element 200 is connected to a transistor included in the pixel circuit PX, and the transistor to which the functional element 200 is connected is the transistor 20 or the transistor 10, for example.
As illustrated in
The pixel PX includes a reset transistor 102, a capacitor 103, the amplifier transistor 104, and a selection transistor 105. A drain of the reset transistor 102 is connected to a node to which a reset voltage Vres is supplied. A source voltage Vs is supplied to a node A including the first electrode 201 of the functional element 200. A source of the reset transistor 102 is connected to the second electrode 209 of the functional element 200 and a gate of the amplifier transistor 104. In this configuration, the reset transistor 102 resets a voltage at a node B to the reset voltage Vres. That is, the reset transistor 102 is a reset unit that supplies the reset voltage Vres to the second electrode 209. When the reset transistor 102 is turned off, the node B including the second electrode 209 of the functional element 200 (photoelectric conversion element) enters an electrically-floating state. A node C is capacitively coupled to the node B via the capacitor 103. A first terminal of the capacitor 103 is connected to the node B. A voltage Vd from a voltage supply unit 410 is supplied to the node C to which a second terminal of the capacitor 103 is connected. The node B includes the gate of the amplifier transistor 104. The amplifier transistor 104 is an amplification unit, and the gate of the amplifier transistor 104 is an input node of the amplification unit. That is, the second electrode 209 of the functional element 200 is electrically-connected to the amplification unit. In this configuration, the amplification unit amplifies a signal generated in the functional element 200 (photoelectric conversion element), and output the amplified signal. A drain of the amplifier transistor 104 is connected to a node to which a source voltage is supplied. A source of the amplifier transistor 104 is connected to an output line 130 via the selection transistor 105. A current source 160 is connected to the output line 130. The amplifier transistor 104 and the current source 160 form a source follower circuit, and output a signal based on charges generated in the functional element 200 to the output line 130. A column circuit 140 is further connected to the output line 130. A signal output to the output line 130 from the pixel circuit PX is input to the column circuit 140.
The pixel circuit PX includes a selection transistor 107, a drive transistor 106, and a capacitor 108. A source voltage Vd is supplied to the drive transistor 106 from a power line PL, and a source voltage Vs is supplied to the first electrode 201. The source voltage Vs may be a voltage lower than the source voltage Vd. In response to a scanning signal applied to a scanning line GL, the selection transistor 107 outputs an applied data signal to a data line DL. The capacitor 108 is charged with a voltage corresponding to a data signal received via the selection transistor 107. A source or a drain of the selection transistor 107 is connected to a node D. A gate of the drive transistor 106 is connected to the node D. The drive transistor 106 is connected to a node E. The drive transistor 106 is connected to the second electrode 209 of the functional element 200. One of a source and a drain of the drive transistor 106 is connected to the node E, and the other one of the source and the drain of the drive transistor 106 is connected to the second electrode 209. The voltage Vd is supplied to the node E from a voltage supply unit. A first terminal of the capacitor 108 is connected to the node D. In this example, a second terminal of the capacitor 108 is connected to the node E, and the node E is capacitively coupled to the node D via the capacitor 108. Alternatively, the capacitor 108 can be connected to a node to which the second electrode 209 is connected, instead of the node E. The drive transistor 106 controls a drive current flowing through the functional element 200, in accordance with a charge amount stored in the capacitor 108. In this configuration, the functional element 200 functioning as a light-emitting element emits light at luminance corresponding to a data level of the data signal.
The pixel circuit PX described with reference to
In the above-described pixel circuit PX, for example, the selection transistor 105, the reset transistor 102, and the selection transistor 107 may be switch transistors. These switch transistors may correspond to the above-described transistor 20. In the above-described pixel circuit PX, for example, the amplifier transistor 104 and the drive transistor 106 differ from the switch transistors in that the amplifier transistor 104 and the drive transistor 106 output potentials correlated with potentials input to their gates, and these transistors can correspond to the transistor 10. The capacitor 103 and the capacitor 108 have a common function in that the capacitor 103 and the capacitor 108 hold a charge amount corresponding to a signal level of a pixel. It is desirable that the reset transistor 102 and the selection transistor 107 directly connected to the capacitor 103 and the capacitor 108, respectively, correspond to the transistor 10. The amplifier transistor 104 and the drive transistor 106 directly connected to the capacitor 103 and the capacitor 108, respectively can correspond to the transistor 20.
The transistor 10 includes the semiconductor layer 11, a gate electrode 12, a source electrode 13, a drain electrode 14, and a gate insulating film 15 that are disposed above the substrate 1. The gate electrode 12, the source electrode 13, and the drain electrode 14 overlap the semiconductor layer 11. The gate electrode 12 is insulated with the gate insulating film 15 from the semiconductor layer 11, and the source electrode 13 and the drain electrode 14 is in contact with the semiconductor layer 11. In the transistor the gate electrode 12 is disposed on a channel of the semiconductor layer 11, and the gate insulating film 15 is disposed between the semiconductor layer 11 and the gate electrode 12. In the transistor 10, the source electrode 13 is disposed on a source of the semiconductor layer 11, and the drain electrode 14 is disposed on a drain of the semiconductor layer 11.
The transistor 20 includes the semiconductor layer 21, a gate electrode 22, a source electrode 23, a drain electrode 24, and a gate insulating film 25 that are disposed above the substrate 1. The gate electrode 22, the source electrode 23, and the drain electrode 24 overlap the semiconductor layer 21. The gate electrode 22 is insulated with the gate insulating film 25 from the semiconductor layer 21, and the source electrode 23 and the drain electrode 24 is in contact with the semiconductor layer 21. In the transistor 20, the gate electrode 22 is disposed above the semiconductor layer 21, and the gate insulating film 25 is disposed between the semiconductor layer 21 and the gate electrode 22. In the transistor 20, the source electrode 23 is disposed on a source of the semiconductor layer 21, and the drain electrode 24 is disposed on a drain of the semiconductor layer 21.
Among the elements of Groups 12 to 16 that are included in the semiconductor layer 11, an element with the highest concentration in the semiconductor layer 11 will be described as an element S1. Among the elements of Groups 12 to 16 that are included in the semiconductor layer 21, an element with the highest concentration in the semiconductor layer 21 will be described as an element S2. In the present exemplary embodiment, the element S1 differs from the element S2.
The semiconductor layers 11 and 21 may be Group IV semiconductors, such as silicon (S1), germanium (Ge), fullerene, and carbon nanotube. In this case, the elements S1 and S2 in the semiconductor layers 11 and 21 may be elements of Group 14. The semiconductor layers 11 and 21 may be Group II-VI compound semiconductors, such as zinc selenide (ZnSe), cadmium sulfide (CdS), and zinc oxide (ZnO). In this case, the elements S1 and S2 in the semiconductor layers 11 and 21 may be elements of Group 12 or 16. The semiconductor layers 11 and 21 may be oxide semiconductors, such as indium gallium zinc oxide (InGaZnO) and indium tin zinc oxide (InSnZnO). In this case, the elements S1 and S2 in the semiconductor layers 11 and 21 may be oxygen (elements of Group 16) or elements of Groups 12 to 14. The concentration of oxygen in an oxide semiconductor is more than or equal to 50 atomic percentage (at %), less than or equal to 70 at %, less than or equal to 67 at %, or at 60 at %, for example. The semiconductor layers 11 and 21 may be Group III-V compound semiconductors, such as gallium arsenide (GaAs), indium phosphide (InP), and gallium nitride (GaN). In this case, the elements S1 and S2 in the semiconductor layers 11 and 21 may be elements of Group 13 or 15. The semiconductor layers 11 and 21 may be Group IV compound semiconductors, such as silicon carbide (SiC) and silicon germanium (SiGe). In this case, the elements S1 and S2 in the semiconductor layers 11 and 21 may be elements of Group 14. The semiconductor layers 11 and 21 may be organic semiconductors. In this case, the elements S1 and S2 in the semiconductor layers 11 and 21 can be carbon (elements of Group 14).
The semiconductor layers 11 and 21 are at least any of a monocrystalline layer, a polycrystalline layer, and a noncrystalline layer. The semiconductor layers 11 and 21 may be a multilayered member including a plurality of types of layers of a monocrystalline layer, a polycrystalline layer, and a noncrystalline layer. To achieve a large area of the semiconductor apparatus AP, the semiconductor layers 11 and 21 is desirably a thin-film transistor (TFT) that uses a polycrystalline layer or a noncrystalline layer.
The gate electrodes 12 and 22, the source electrodes 13 and 23, and the drain electrodes 14 and 24 each include at least one conductor layer. In a case where the gate electrodes 12 and 22 have a multilayered structure including a plurality of conductor layers, lowermost or uppermost conductor layers of the gate electrodes 12 and 22 are in contact with the gate insulating films 15 and 25. In a case where the source electrodes 13 and 23 and the drain electrodes 14 and 24 have a multilayered structure including a plurality of conductor layers, lowermost or uppermost conductor layers of the source electrodes 13 and 23 and the drain electrodes 14 and 24 are in contact with the semiconductor layers 11 and 21. In the below description of the conductor layers of the gate electrodes 12 and 22, the source electrodes 13 and 23, and the drain electrodes 14 are 24, the conductor layers may be conductor layers closest to the semiconductor layers 11 and 21.
A conductor member overlapping the semiconductor layer 11 and insulated from the semiconductor layer 11 may be disposed above the substrate 1 aside from the gate electrode 12. A conductor member 28 (to be described below) overlapping the semiconductor layer 21 and insulated from the semiconductor layer 21 may be disposed above the substrate 1 aside from the gate electrode 22. The conductor member 28 is able to be used as an auxiliary electrode, a wire, a light shielding member, or a height difference adjustment member for the transistor 20, or the like. While another conductor layer may exist between the conductor member 28 and the semiconductor layer 21, the other conductor layer needs not exist between the conductor member 28 and the semiconductor layer 21.
The conductor layer of the source electrode 13 and the conductor layer of the drain electrode 14 are each made of one or more types of metal elements or metalloid elements. Among the metal elements or metalloid elements included in the conductor layer of the source electrode 13 and the conductor layer of the drain electrode 14, an element with the highest concentration in the source electrode 13 or the drain electrode 14 will be described as an element M1.
The conductor layer of the gate electrode 22 is made of one or more types of metal elements or metalloid elements. Among the metal elements or metalloid elements included in the gate electrode 22, an element with the highest concentration in the gate electrode 22 will be described as an element M2.
The conductor layer of the gate electrode 12 is made of one or more types of metal elements or metalloid elements. Among the metal elements or metalloid elements included in the conductor layer of the gate electrode 12, an element with the highest concentration in the conductor layer of the gate electrode 12 will be described as an element M3.
The conductor layer of the source electrode 23 and the conductor layer of the drain electrode 24 are made of one or more types of metal elements or metalloid elements. Among the metal elements or metalloid elements included in the conductor layer of the source electrode 23 and the conductor layer of the drain electrode 24, an element with the highest concentration in the gate electrode 22 will be described as an element M4.
The element M3 that is a metal element or a metalloid element included in the gate electrode 12 may differ from the element S2 included in the semiconductor layer 21. The element M4 that is a metal element or a metalloid element included in the gate electrode 22 may differ from the element S1 included in the semiconductor layer 11.
The conductor layer of the conductor member 28 overlaps the semiconductor layer 21 and is insulated from the semiconductor layer 21. The conductor layer of the conductor member 28 is made of one or more types of metal elements or metalloid elements other than the gate electrode 22. Among the metal elements or metalloid elements included in the conductor layer of the conductor member 28, an element with the highest concentration in the conductor member 28 will be described as an element M5.
The element M1 that is a metal element or a metalloid element included in the source electrode 13 or the drain electrode 14 may differ from the element S2 included in the semiconductor layer 21.
The element M2 that is a metal element or a metalloid element included in the gate electrode 22 may differ from the element S1 included in the semiconductor layer 11. The element M3 that is a metal element or a metalloid element included in the gate electrode 12 may differ from the element S2 included in the semiconductor layer 21.
The element M4 that is a metal element or a metalloid element included in the source electrode 23 and the drain electrode 24 may differ from the element S1 included in the semiconductor layer 11.
The element M5 that is a metal element or a metalloid element included in the conductor member 28 may differ from the element S1 included in the semiconductor layer 11.
The difference in the main constituent elements between the gate electrode of either the transistor 10 or the transistor 20 and the semiconductor layer of the other one of the transistor 10 and the transistor 20 is advantageous in achieving the characteristics of the electrodes of the transistor 10 and 20.
For example, the elements M1 to M4 are elements of Groups 3 to 13, and can be elements of Groups 3 to 9. Typically, the elements M1 to M4 may be any of gold (Au), silver (Ag), copper (Cu), platinum (Pt), molybdenum (Mo), tungsten (W), tantalum (Ta), and titanium (Ti). In particular, the elements M1 to M4 are desirably any of Cu, Mo, W, and Ti.
In the present exemplary embodiment, the element M1 and the element M2 may be the same. Elements being the same means that atomic numbers of the elements are the same. Using the same element in the source electrode 13, the drain electrode 14, and the gate electrode 22 results in reduction in cost in designing, procurement, and manufacturing.
In the present exemplary embodiment, the element M1 and the element M5 may be the same. Elements being the same means that atomic numbers of the elements are the same. Using the same element in the source electrode 13, the drain electrode 14, and the conductor member 28 results in reduction in cost in designing, procurement, and manufacturing.
While, in
The T-type transistor 10 illustrated in
In the C-type transistor 10 illustrated in
In the C-type transistor 20 illustrated in
In the B-type transistor 10 illustrated in
In the S-type transistor 10 illustrated in
In a second exemplary embodiment, both the transistor 10 and the transistor 20 disposed above a single substrate, i.e., the substrate 1, are of T type. In this case, it is desirable that both the transistor 10 and the transistor 20 are of C type, and it is also desirable that both the transistor 10 and the transistor 20 are of S type. Alternatively, the type of the transistor 10 can be one of C type and S type, and the type of the transistor 20 can be the other one of C type and S type.
In a third exemplary embodiment, both the transistor 10 and the transistor 20 disposed above a single substrate, i.e., the substrate 1, are B-type transistors. In this case, it is desirable that both the transistor 10 and the transistor 20 are of C type, and it is also desirable that both the transistor 10 and the transistor 20 are of S type. Alternatively, the type of the transistor 10 can be one of C type and S type, and the type of the transistor 20 can be the other one of C type and S type.
In a fourth exemplary embodiment, both the transistor 10 and the transistor 20 disposed above a single substrate, i.e., the substrate 1, are C-type transistors. In this case, it is desirable that both the transistor 10 and the transistor 20 are of T type, and it is also desirable that both the transistor 10 and the transistor 20 are of B type. Alternatively, the type of the transistor 10 can be one of T type and B type, and the type of the transistor 20 can be the other one of T type and B type.
In a fifth exemplary embodiment, both the transistor 10 and the transistor 20 disposed above a single substrate, i.e., the substrate 1, are S-type transistor. In this case, it is desirable that both the transistor 10 and the transistor 20 are of T type, and it is also desirable that both the transistor 10 and the transistor 20 are of B type. Alternatively, the type of the transistor 10 can be one of T type and B type, and the type of the transistor 20 can be the other one of T type and B type.
Using the same type transistors as both the transistor 10 and the transistor 20 disposed above a single substrate, i.e., the substrate 1, as in the second to fifth exemplary embodiments, results in simplification of the configuration of the semiconductor apparatus AP, and cost reduction in designing and manufacturing of the semiconductor apparatus AP.
In a sixth exemplary embodiment, the element M2 included in the gate electrode 22 is the same as the element M4 included in the source electrode 23 and the drain electrode 24. Using the same element in the three electrodes of the transistor 20 results in cost reduction.
In a seventh exemplary embodiment, the element M3 included in the gate electrode 12 is the same as the element M1 included in the source electrode 13 and the drain electrode 14. Using the same element in the three electrodes of the transistor 10 results in cost reduction.
In an eight exemplary embodiment, the gate electrode 22 has a conductor layer including the element M4 which is the same as the element M1 included in the source electrode 13 and the drain electrode 14. The conductor layer of the gate electrode 22 can be contiguous to the conductor layer of the source electrode 13 or the conductor layer of the drain electrode 14. The conductor layer of the gate electrode 22 that includes the element M4 can be noncontiguous to the conductor layer of the source electrode 13 or the conductor layer of the drain electrode 14 that includes the element M1.
In a ninth exemplary embodiment, the conductor member 28 has a conductor layer including the element M5 which is the same as the element M1 included in the source electrode 13 and the drain electrode 14. The semiconductor layer 21 is disposed between the gate electrode 22 and the conductor member 28 (the conductor layer including the element M5). In the ninth exemplary embodiment, a conductor layer including the element M5 which is the same as the element M1 is the conductor member 28. The conductor layer of the conductor member 28 that includes the element M5 can be contiguous to the conductor layer of the source electrode 13 or the conductor layer of the drain electrode 14 that includes the element M1. The conductor layer of the conductor member 28 can be noncontiguous to the conductor layer of the source electrode 13 or the conductor layer of the drain electrode 14 that includes the element M1.
The potential of the conductor member 28 (the conductor layer including the element M5) can be the same as the potential of any of the gate electrode 12, the source electrode 13, the drain electrode 14, the gate electrode 22, the source electrode 23, and the drain electrode 24. In particular, the potential of the conductor member 28 (the conductor layer including the element M5) can be the same as the potential of the gate electrode 22. To achieve this, the gate electrode 22 and the conductor member 28 can be electrically connected with each other. The conductor layer of the gate electrode 22 that includes the element M2, and the conductor layer of the conductor member 28 that includes the element M5 can be in contact with each other, or both the conductor layers can be electrically connected via another conductor layer (for example, via). With the gate electrode 22 and the conductor member 28 disposed on both sides of the semiconductor layer 21, an electric field to be added to the semiconductor layer 21 is controlled. The potential of the conductor member 28 (the conductor layer including the element M5) can differ from any of the potentials of the gate electrode 12, the source electrode 13, the drain electrode 14, the gate electrode 22, the source electrode 23, and the drain electrode 24, or can be a floating potential.
The element M3 that is a metal element or a metalloid element included in the gate electrode 12 may differ from the element M2 that is a metal element or a metalloid element included in the gate electrode 22. The difference in the main metal elements or metalloid elements included in the gate electrodes 12 and 22 is advantageous in achieving the characteristics of the transistors 10 and 20.
Among the elements of Groups 12 to 16 that are included in the semiconductor layer 11, an element with the second highest concentration in the semiconductor layer 11 after the element S1 will be described as an element S3. In a case where the semiconductor layer 11 is a binary compound semiconductor, the semiconductor layer 11 is a compound of the element S1 and the element S3. Among the elements of Groups 12 to 16 that are included in the semiconductor layer 21, an element with the second highest concentration in the semiconductor layer 21 after the element S2 will be described as an element S4. When the semiconductor layer 21 is a binary compound semiconductor, the semiconductor layer 21 is a compound of the element S2 and the element S4. The element S3 included in the semiconductor layer 11 may differ from the element S4 included in the semiconductor layer 21.
In a case where the elements S1 and S2 are oxygen (O) in an oxide semiconductor, such as InGaZnO or InSnZnO, the elements S3 and S4 may be zinc (Zn). In an oxide semiconductor, such as InGaZnO or InSnZnO, the concentration of zinc may be 10 to 30 at % or 10 to 20 at %, or 16 at %, for example. In a case where the elements S1 and S2 are oxygen (O) in an oxide semiconductor, such as InGaZnO or InSnZnO, the elements S3 and S4 may be indium (In). The concentration of indium may be 5 to 20 at %, or 14 at %, for example. In an oxide semiconductor, such as InGaZnO or InSnZnO, the concentrations of gallium (Ga) and tin (Sn) may be lower than the concentration of zinc (Zn). In an oxide semiconductor, such as InGaZnO or InSnZnO, the concentrations of gallium (Ga) and tin (Sn) may be lower than the concentration of indium (In). In an oxide semiconductor, such as InGaZnO or InSnZnO, the concentrations of gallium (Ga) and tin (Sn) may be 5 to 20 at %, or 10 at %, for example. In InGaZnO, for example, In:Ga:Zn:O=16:10:14:60 is obtained.
In a tenth exemplary embodiment, a conductor layer including an element (for example, the element M2 or the element M5) which is the same as the element M1 included in the conductor layer of the source electrode 13 or the conductor layer of the drain electrode 14 may be of the same layer as the conductor layer of the source electrode 13 or the drain electrode 14. The conductor layers being the same layer means that the conductor layers are layers formed from a single film. Even if the conductor layers are the same layer, heights of the two layers from the substrate 1 may be different from each other due to a base height difference generated during film formation. In addition, in a case where the conductor layers are of the same layer, the two layers can have substantially the same thickness. Here, the two layers having substantially the same thickness means that the thickness of one layer falls within the range of 90 to 110 percent (%) of the thickness of the other layer.
Combinations of types of the transistors 10 and 20 will be described with reference to Table 1.
In Table 1, 32 patterns of combinations of types of the transistors 10 and 20 are listed. In Table 1, when the transistors 10 and 20 are of T type, “T” is described on a TB column, and when the transistors 10 and 20 are of B type, “B” is described on the TB column. When the transistors 10 are 20 are of C type, “C” is described on a CS column, and when the transistors 10 and 20 are of the S type, “S” is described on the CS column. In Table 1, when a component including the same element as the element M1 included in the source electrode 13 and the drain electrode 14 is the gate electrode 22, “G” is described on an M column. In addition, when a component including the same element as the element M1 included in the source electrode 13 and the drain electrode 14 is the conductor member 28 other than the gate electrode 22, “N” is described on the M column.
Nos. 01 to 04 and Nos. 09 to 12 correspond to the second exemplary embodiment. Nos. 21 to 24 and Nos. 29 to 32 correspond to the third exemplary embodiment. Nos. 01, 02, 05, and 06, and Nos. 17, 18, 21, and 22 correspond to the fourth exemplary embodiment. Nos. 11, 12, 15, and 16, and Nos. 27, 28, 31, and 32 correspond to the fifth exemplary embodiment. Odd-numbered examples in which “G” is described on the M column correspond to the eighth exemplary embodiment. Even-numbered examples in which “N” is described on the M column correspond to the ninth exemplary embodiment.
Such a structure of the transistor 20 illustrated in
A manufacturing method of the semiconductor apparatus AP will be described with reference to
In the first example illustrated in
In
In an eleventh exemplary embodiment, a distance D1 between the semiconductor layer 11 and the substrate 1 may differ from a distance D2 between the semiconductor layer 21 and the substrate 1. The difference between the distance D1 and the distance D2 in the transistors 10 and 20 implements more appropriate characteristics of the transistors 10 and 20 in comparison with a case where the distance D1 and the distance D2 are equal to each other. The influence is exerted on the semiconductor layers 11 and 21 from the substrate 1, and the influence is exerted on the semiconductor layers 11 and 21 from a member existing on the opposite side of the side facing the substrate 1 with respect to the semiconductor layers 11 and 21. The difference between the distance D1 and the distance D2 in the transistors 10 and 20 implements more appropriate characteristics of the transistors 10 and 20.
In a twelfth exemplary embodiment, a distance D3 between the substrate 1 and the gate electrode 12 may differ from a distance D4 between the substrate 1 and the gate electrode 22. More specifically, the influence on the gate electrodes 12 and 22 from the substrate 1, the influence on the gate electrodes 12 and 22 from a member existing on the opposite side of the side facing the substrate 1 with respect to the gate electrodes 12 and 22, and the characteristics of the transistors 10 and 20 can be optimized.
The distance D3 between the substrate 1 and the gate electrode 12 may differ from the distance D2 between the substrate 1 and the semiconductor layer 21. In addition, the distance D4 between the substrate 1 and the gate electrode 22 may differ from the distance D1 between the substrate 1 and the semiconductor layer 11.
In a thirteenth exemplary embodiment, a distance D5 between the semiconductor layer 11 and the gate electrode 12 may differ from a distance D6 between the semiconductor layer 21 and the gate electrode 22. The distance D5 between the semiconductor layer 11 and the gate electrode 12 corresponds to the thickness of the gate insulating film 15, and the distance D6 between the semiconductor layer 21 and the gate electrode 22 corresponds to the thickness of the gate insulating film 25. The difference between the distance D5 and the distance D6 in the transistors 10 and 20 implements more appropriate characteristics of the transistors 10 and 20 more appropriate in comparison with a case where the distance D5 and the distance D6 are equal to each other.
In a case where a positional relationship between the substrate 1, the semiconductor layers 11 and 21, and the gate electrodes 12 and 22 varies in the transistors 10 and 20 as in the eleventh to thirteenth exemplary embodiments, unevenness is easily generated between the transistor 10 and the transistor 20. If conductor layers of the same layer are contiguous to each other between the transistor 10 and the transistor 20, due to the unevenness between the transistor 10 and the transistor 20, unexpected disconnection might occur between the conductor layers. It is thus desirable that the conductor layers of the same layer are noncontiguous to each other between the transistor 10 and the transistor 20. To electrically connect the noncontiguous conductor layers of the same layer, the conductor layers may be connected via another conductor layer. For example, in a case of electrically connecting the source electrode 13 (and the drain electrode 14) and the gate electrode 22 in the same layer and in a noncontiguous way, the electrodes may be connected via a conductor layer included in at least one of the gate electrode 12 and the source electrode 23 (the drain electrode 24).
In a fourteenth exemplary embodiment, the element S1 included in the semiconductor layer 11 may be an element of Group 14, and the element S2 included in the semiconductor layer 21 may be an element of Group 12, 13, 15, or 16. For example, the element S1 included in the semiconductor layer 11 may be silicone (S1), and the element S2 included in the semiconductor layer 21 may be oxygen (O). The semiconductor layer 11 may be a polycrystalline layer or a noncrystalline layer, and the semiconductor layer 21 may be an oxide semiconductor layer. The semiconductor layer 11 may be a polycrystal silicon layer. In the semiconductor layer 21, the element S4 may be indium (In). Using indium (In) as the element S4 results in increase in the mobility of the semiconductor layer 21. The semiconductor layer 21 may include gallium (Ga). The semiconductor layer 21 may include tin (Sn). In a case where the semiconductor layer 21 includes tin (Sn), the mobility of the semiconductor layer 21 is increased.
The substrate 1 may be an insulator substrate made of glass, resin, or the like, but can be a semiconductor substrate made of silicon or the like, or can be a conductor substrate made of metal or the like. In a case where the substrate 1 is a resin substrate, a base member in which a resin film made of polyimide or the like is formed on a base material, such as glass. is prepared, and the transistors 10 and 20 are formed on the resin film of the base member. After that, the base material and the resin film is separated using laser or the like, to use the resin film as the substrate 1 (resin substrate). The resin substrate may be a flexible substrate. In a case where the substrate 1 is a semiconductor substrate, at least either the semiconductor layer 11 or 21 may be a monocrystal semiconductor layer epitaxially grown on the substrate 1 being a monocrystal semiconductor, in accordance with a crystalline structure of the substrate 1. Alternatively, in a case where the substrate 1 is a semiconductor substrate, at least either the semiconductor layers 11 or 21 may have a structure (Semiconductor On Insulator (SOI) structure) of being formed via an insulator layer on the substrate 1 which is a monocrystal semiconductor. In a case where the substrate 1 is a conductor substrate, an insulator layer may be disposed between the semiconductor layer 11 or 21 and the substrate 1. The transistor 10 may be a P-type transistor or may be an N-type transistor. The transistor 10 desirably forms a CMOS circuit together with the transistor 30, and it is desirable that the transistor 10 is a P-type transistor and the transistor 30 is an N-type transistor. The transistor 10 may be an N-type transistor and the transistor 30 may be a P-type transistor. Among the elements of Groups 12 to 16 that are included in a semiconductor layer 31 of the transistor 30, an element with the highest concentration in the semiconductor layer 31 will be described as an element S5. The element S5 may be the same as the element S1 included in the semiconductor layer 11. Among the elements of Groups 12 to 16 that are included in the semiconductor layer 31 of the transistor 30, an element with the second highest concentration in the semiconductor layer 31 after the element S5 will be described as an element S6. The element S6 may differ from the element S3 included in the semiconductor layer 11. For example, the element S1 and the element S5 may be silicon (S1), the element S3 may be boron (B), and the element S6 may be phosphorus (P).
In a case where the transistor 10 is an N-type transistor and the transistor 30 is a P-type transistor, the element S3 may be phosphorus (P) and the element S6 may be boron (B). In a case where the semiconductor layer 11 of the transistor 10 and the semiconductor layer 31 of the transistor 30 are polycrystal semiconductor layers, the carrier mobility is increased, which is desirable to realize high speed switching. In a case where the semiconductor layer 11 of the transistor 10 and the semiconductor layer 31 of the transistor 30 are polycrystal semiconductor layers, carrier mobility is increased and thus a gate voltage is lowered, which is desirable to realize reduction in power consumption in comparison with a case of a noncrystalline semiconductor.
The transistor 20 may be a P-type transistor or may be an N-type transistor. Because an electron mobility is generally higher than a hole mobility, it is desirable that the transistor 20 is an N-type transistor. It is also desirable that the transistor 20 is a switch transistor. If the transistor 20 is an N-type switch transistor, high-speed switching is executable. In a case where the semiconductor layer 21 of the transistor 20 is an oxide semiconductor, a bandgap is widened and thus leak current of the switch transistor is reduced by a wide bandgap, which is desirable to realize reduction in leak current of the switch transistor.
The substrate 1 may have various sizes, but it is desirable that a diagonal length is more than or equal to 1 centimeter (cm), and it is also desirable that the diagonal length is more than or equal to 2.5 cm. In a case where the diagonal length is less than 2.5 cm, the semiconductor layer 11 of the transistor 10 may be a monocrystalline layer. For example, the transistor 10 may be formed on the substrate 1 made of monocrystal silicon, and the transistor 20 as a thin-film transistor may be formed on the substrate 1. The diagonal length of the substrate 1 may be more than or equal to 5 cm. In a case where the diagonal length of the substrate 1 is more than or equal to 5 cm, it is desirable that the transistor 10 is a thin-film transistor, and the semiconductor layer 11 may be a polycrystalline layer or a noncrystalline layer. In a case where the semiconductor layer 11 is a polycrystalline layer or a noncrystalline layer, even when the diagonal length of the substrate 1 is more than or equal to 5 cm, uniformity sufficient for the characteristics of the transistor 10 is ensured. In a case where the diagonal length of the substrate 1 is less than 75 cm, the semiconductor layer 11 of the transistor 10 is desirably a polycrystalline layer. In a case where the semiconductor layer 11 of the transistor 10 is a polycrystalline layer, the diagonal length of the substrate 1 may be more than or equal to 20 cm, may be more than or equal to 25 cm, and may be more than or equal to 30 cm. In a case where the diagonal length of the substrate 1 is more than or equal to 20 cm, it is desirable that the transistor 10 in which a polycrystalline layer is used as the semiconductor layer 11 is disposed in the pixel circuit PX. In a case where a polycrystalline layer with a high charge mobility is used for the amplifier transistor 104 and the drive transistor 106 of the pixel circuit PX, even in the substrate 1 with a large diagonal length, power consumption in the power line PL connecting to the pixel circuit PX is reduced. In a case where the transistor 10 is disposed in the pixel circuit PX, from the viewpoint of image quality improvement, it is desirable that the diagonal length of the substrate 1 is less than 50 cm. In a case where the diagonal length of the substrate 1 is less than 50 cm, uniformity sufficient for the characteristics of the transistor 10 is ensured. In a case where the diagonal length of the substrate 1 is more than or equal to 75 cm, it is desirable that the semiconductor layer 11 of the transistor 10 is a noncrystalline layer. Whichever diagonal length the substrate 1 has, it is desirable that the semiconductor layer 21 of the transistor 20 is an oxide semiconductor layer.
While the diagonal length of the substrate 1 has been described, the same applies to the diagonal length of the pixel region 2, and the diagonal length of the substrate 1 may be read as the diagonal length of the pixel region 2. For example, it is desirable that the diagonal length of the pixel region 2 is more than or equal to 1 cm, it is also desirable that the diagonal length of the pixel region 2 is more than or equal to 2.5 cm, it is also desirable that the diagonal length of the pixel region 2 is more than or equal to 5 cm, and the diagonal length of the pixel region 2 may be more than or equal to 20 cm, more than or equal to 25 cm, more than or equal to 30 cm, or may be less than 75 cm.
A fifteenth exemplary embodiment is an exemplary embodiment obtained by combining the eleventh exemplary embodiment and the fourteenth exemplary embodiment, and it is desirable that the distance D1 between the semiconductor layer 11 and the substrate 1 is smaller than the distance D2 between the semiconductor layer 21 and the substrate 1. In a case where the semiconductor layer 11 is a polycrystalline layer, crystallinity control is important. In a case where the semiconductor layer 11 is disposed more closely to the substrate 1 than the semiconductor layer 21, the flatness of the semiconductor layer 11 is improved, which improves the uniformity of crystallinity. In addition, in a case where the semiconductor layer 11 is formed earlier than the semiconductor layer 21, the influence of heat treatment for forming the semiconductor layer 11 is prevented from being exerted on the semiconductor layer 21. That is, before the semiconductor layer 21 is formed, appropriate heat treatment is able to be performed on the semiconductor layer 11. Thus, the crystallinity control of the semiconductor layer 11 is easier.
A sixteenth exemplary embodiment is an exemplary embodiment obtained by combining the twelfth exemplary embodiment and the fourteenth exemplary embodiment, and it is desirable that the distance D3 between the substrate 1 and the gate electrode 12 is smaller than the distance D4 between the substrate 1 and the gate electrode 22.
A seventeenth exemplary embodiment is an exemplary embodiment obtained by combining the twelfth exemplary embodiment and the fifteenth exemplary embodiment, and it is desirable that the distance D5 between the semiconductor layer 11 and the gate electrode 12 is smaller than the distance D6 between the semiconductor layer 21 and the gate electrode 22. The distance D5 between the semiconductor layer 11 and the gate electrode 12 corresponds to the thickness of the gate insulating film 15, and the distance D6 between the semiconductor layer 21 and the gate electrode 22 corresponds to the thickness of the gate insulating film 25. For example, the distance D5 may be 200 to 400 nanometers (nm) and the distance D6 may be 50 to 200 nm. Thinning the gate insulating film 15 improves the response characteristics of the transistor 10, which realizes good drive force. In addition, thickening the gate insulating film 25 further reduces leak current of the transistor 20.
An eighteenth exemplary embodiment is related to a capacitor C disposed on the substrate 1. While the capacitor C is able to be applied to the capacitors 103 and 108 illustrated in
The lower gate electrode 221 is disposed on a side with the substrate 1 with respect to the semiconductor layer 21, and the lower gate electrode 221 is between the semiconductor layer 21 and the substrate 1. The lower gate electrode 221 corresponds to the gate electrode 22 in the B-type transistor 20 illustrated in
The upper gate electrode 222 is disposed on a side opposite to the side with the substrate 1 with respect to the semiconductor layer 21, and the semiconductor layer 21 is between the upper gate electrode 222 and the substrate 1. The upper gate electrode 222 corresponds to the gate electrode 22 in the T-type transistor 20 illustrated in
The lower gate electrode 221 may overlap either the source electrode 23 or the drain electrode 24. Thus, the lower gate electrode 221 forms a capacitor Ce together with the source electrode 23 or the drain electrode 24. The upper gate electrode 222 may overlap either the source electrode 23 or the drain electrode 24. Thus, the lower gate electrode 221 forms a capacitor Ch together with the source electrode 23 or the drain electrode 24. In this manner, each of the capacitors Ce and Ch is an MIM-type capacitor in which a dielectric layer is between a conductor layer and another conductor layer.
Especially in a case where both of the lower gate electrode 221 and the upper gate electrode 222 are disposed, the potential of the lower gate electrode 221 can be the same as the potential of the upper gate electrode 222. To achieve this, the lower gate electrode 221 and the upper gate electrode 222 can be electrically connected with each other. A conductor layer of the lower gate electrode 221 and a conductor layer of the upper gate electrode 222 can be in contact with each other, or both conductor layers can be electrically connected with each other via another conductor layer (for example, via).
It is desirable that the element M2 in at least one of the conductor layer of the lower gate electrode 221 and the conductor layer the upper gate electrode 222 is the same as the element M1 in at least one of the conductor layer of the source electrode 13 and conductor layer of the drain electrode 14. In addition, it is also desirable that either the conductor layer of the lower gate electrode 221 or the conductor layer the upper gate electrode 222 that includes the element M2 is of the same layer as at least one of the conductor layer of the source electrode 13 and the conductor layer of the drain electrode 14 that includes the element M1.
A nineteenth exemplary embodiment is also related to the capacitor C disposed on the substrate 1. While the capacitor C is applicable to the capacitors 103 and 108 illustrated in
The lower capacitor electrode 281 overlaps at least any of the lower gate electrode 221, the source electrode 23, the drain electrode 24, the upper gate electrode 222, and the upper capacitor electrode 282. The lower capacitor electrode 281 is disposed between an electrode overlapping the lower capacitor electrode 281 and the substrate 1.
The lower capacitor electrode 281, and at least any of electrodes overlapping the lower capacitor electrode 281 form an MIM-type capacitor in which a dielectric layer is between a conductor layer and another conductor layer. In this example, the dielectric layer of the capacitor is the interlayer insulating film 26. For example, the lower capacitor electrode 281 forms a capacitor Cf together with the lower gate electrode 221. For example, the lower capacitor electrode 281 forms a capacitor Ci together with the source electrode 23 or the drain electrode 24. For example, the lower capacitor electrode 281 forms a capacitor Cj together with the upper gate electrode 222. For example, the lower capacitor electrode 281 forms a capacitor Ca together with the upper capacitor electrode 282.
The upper capacitor electrode 282 overlaps at least any of the lower capacitor electrode 281, the lower gate electrode 221, the source electrode 23, the drain electrode 24, and the upper gate electrode 222. An electrode overlapping the upper capacitor electrode 282 is between the upper capacitor electrode 282 and the substrate 1.
The upper capacitor electrode 282 and at least any of electrodes overlapping the upper capacitor electrode 282 form an MIM-type capacitor in which a dielectric layer is between a conductor layer and another conductor layer. In this example, the dielectric layer of the capacitor is the interlayer insulating film 26. For example, the upper capacitor electrode 282 forms the capacitor Ca together with the lower capacitor electrode 281. For example, the upper capacitor electrode 282 forms a capacitor Cb together with the lower gate electrode 221. For example, the upper capacitor electrode 282 forms a capacitor Cd together with the source electrode 23 or the drain electrode 24. For example, the upper capacitor electrode 282 forms a capacitor Cg together with the upper gate electrode 222.
In the example illustrated in
It is desirable that the element M5 in at least one of the conductor layer of the lower capacitor electrode 281 and the conductor layer of the upper capacitor electrode 282 is the same as the element M1 in at least one of the conductor layer of the source electrode 13 and the conductor layer of the drain electrode 14. In addition, it is desirable that either the conductor layer of the lower capacitor electrode 281 or the conductor layer of the upper capacitor electrode 282 that includes the element M5 is of the same layer as at least one of the conductor layer of the source electrode 13 and the conductor layer of the drain electrode 14 that includes the element M1.
In the eighteenth and nineteenth exemplary embodiments, at least one of two electrodes forming the capacitor C is the gate electrode 22 or the conductor member 28 (capacitor electrode) in no contact with the semiconductor layer 21. The other one of the two electrodes forming the capacitor C is the gate electrode 22 or the conductor member 28 (capacitor electrode) in no contact with the semiconductor layer 21, or the source electrode 13 or the drain electrode 14 in contact with the semiconductor layer 21. Then, out of the two electrodes forming the capacitor C, an electrode (the gate electrode 22 or the conductor member 28 (capacitor electrode)) in no contact with the semiconductor layer 21 is insulated with a dielectric layer (the interlayer insulating film 26) from the other electrode of the two electrodes forming the capacitor C.
The capacitors 103 and 108 illustrated in
In the examples illustrated in
In the example illustrated in
In the example illustrated in
In the example illustrated in
Also in
The control apparatus CTRL is connected to the display apparatus DSPL. In a case where the display apparatus DSPL includes a drive circuit for driving a pixel circuit in the peripheral region 3, the control apparatus CTRL can supply power and signals to the drive circuit. In a case where the display apparatus DSPL does not include a drive circuit for driving a pixel circuit in the peripheral region 3, the control apparatus CTRL includes a drive circuit for driving a pixel circuit.
The control apparatus CTRL is connected to the imaging apparatus IS. The control apparatus CTRL controls an image capturing mode of the imaging apparatus IS, and process a signal output from the imaging apparatus IS. The imaging apparatus IS may be an image sensor, or may be an infrared sensor or a ranging sensor.
The equipment EQP may include an optical member OPT disposed above the display apparatus DSPL that is the semiconductor apparatus AP. The optical member OPT is a lens, a cover, or a filter. In a case where the semiconductor apparatus AP is the display apparatus DSPL of a top emission type, the semiconductor layer 21 may be disposed between the substrate 1 of the semiconductor apparatus AP and the optical member OPT. In a case where the semiconductor apparatus AP is the display apparatus DSPL of a bottom emission type, the substrate 1 may be disposed between the semiconductor layer 21 of the semiconductor apparatus AP and the optical member OPT.
The equipment EQP may include the imaging apparatus IS and the display apparatus DSPL. An image captured by the imaging apparatus IS may be displayed on a display apparatus DSPL.
The display apparatus DSPL may be able to switch a frame rate at which the display apparatus DSPL performs display, between a low frame rate and a high frame rate higher than the low frame rate. For example, the low frame rate is less than or equal to frames per second (fps), or is less than or equal to 5 fps, or is 1 fps, for example. For example, the high frame rate is more than or equal to 100 fps, or is more than or equal to 200 fps, or is 240 fps, for example. The display apparatus DSPL may be able to switch a refresh rate at which the display apparatus DSPL performs display, between a low refresh rate and a high refresh rate higher than the low refresh rate. For example, the low refresh rate is less than or equal to 10 hertz (Hz), or is less than or equal to 5 Hz, or is 1 Hz, for example. For example, the high refresh rate is less than or equal to 100 Hz, or is more than or equal to 200 Hz, or is 240 Hz, for example. Both the frame rate unit (fps) and the refresh rate unit (Hz) can be represented as “frames per second” or “times per second”. The display apparatus DSPL may able to switch a frame rate at which the display apparatus DSPL performs display, to a medium frame rate between the low frame rate and the high frame rate. For example, the medium frame rate is 20 to 80 fps. The display apparatus DSPL may able to switch a refresh rate at which the display apparatus DSPL performs display, to a medium refresh rate between the low refresh rate and the high refresh rate. For example, the medium refresh rate is 20 to 80 Hz. Since an oxide semiconductor layer has a small leak current, in a case where an oxide semiconductor layer is used in the selection transistor 107, charge leakage from the capacitor 108 is suppressed, whereby driving at the low frame rate is easily performed. In addition, since a polycrystal semiconductor layer has a higher mobility than that of a noncrystalline semiconductor layer, in a case where a polycrystal semiconductor layer is used in the selection transistor 107, selection speed is increased, whereby driving at the high frame rate and refresh rate is easily performed. In addition, since a polycrystal semiconductor layer has a higher mobility than that of a noncrystalline semiconductor layer, in a case where a polycrystal semiconductor layer is used in the drive transistor 106, lowering of a gate voltage is realized, whereby driving with low power consumption is easily performed.
The imaging apparatus IS may perform image capturing at the above-described medium frame rate between the low frame rate and the high frame rate. The imaging apparatus IS may perform image capturing at the above-described medium frame rate between the low refresh rate and the high refresh rate. For example, the imaging apparatus IS may perform image capturing at a frame rate of 20 to 80 fps. The image capturing here is not limited to storing images, and also includes image capturing for only performing temporal display, such as live view. It is desirable that a frame rate of the display apparatus DSPL that is to be set when an image captured by the imaging apparatus IS at the medium frame rate is to be displayed is the medium frame rate or the high frame rate. It is desirable that a refresh rate of the display apparatus DSPL that is to be set when an image captured by the imaging apparatus IS at the medium frame rate is to be displayed is the medium refresh rate or the high refresh rate. For example, it is desirable that a refresh rate of the display apparatus DSPL that is to be set when an image captured by the imaging apparatus IS at the frame rate of 30 frames per second is to be displayed is 60 frames per second or 120 frames per second.
The equipment EQP can be electronic equipment, such as a smartphone, a tablet terminal, a lap-top personal computer, a digital camera, or a wearable terminal. The equipment EQP can include a battery, such as a lithium ion battery, a solid-state battery, or a fuel battery. Since power to be consumed by the imaging apparatus IS and the display apparatus DSPL is able to be decreased, long driving time using the battery is realized.
The exemplary embodiments described above can be appropriately changed without departing from the technical idea. For example, a plurality of exemplary embodiments can be combined. In addition, part of the configurations described in at least one exemplary embodiment can be deleted or replaced. In addition, a new configuration can be added to at least one exemplary embodiment.
The disclosure of this specification is not limited to the matters explicitly described in this specification, and includes all matters identifiable from this specification and the drawings accompanying this specification. The disclosure of this specification includes a complement set of individual concepts described in this specification. More specifically, for example, if “A is larger than B” is described in this specification, even if the description of “A is not larger than B” is omitted, this specification can be said to disclose that “A is not larger than B”. This is because, in a case where “A is larger than B” is described, a case where “A is not larger than B” is considered.
The present invention is not limited to the above-described exemplary embodiments, and various changes and modifications can be made without departing from the spirit and the scope of the present invention. Accordingly, to publicize the scope of the present invention, the following claims are appended.
According to the present invention, a technique advantageous in reducing cost of a semiconductor apparatus can be provided.
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-036296 | Mar 2021 | JP | national |
| 2021-109341 | Jun 2021 | JP | national |
This application is a Continuation of International Patent Application No. PCT/JP2022/008828, filed Mar. 2, 2022, which claims the benefit of Japanese Patent Applications No. 2021-036296, filed Mar. 8, 2021, and No. 2021-109341, filed Jun. 30, 2021, all of which are hereby incorporated by reference herein in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2022/008828 | Mar 2022 | US |
| Child | 18461990 | US |
