SEMICONDUCTOR ASSEMBLY WITH SEMICONDUCTOR SWITCHING DEVICE AND CURRENT SENSE UNIT

Abstract

A semiconductor assembly includes a semiconductor switching device, a conductive load base structure, and a current sense unit. The semiconductor switching device includes a drain structure and one or more array units, wherein each array unit includes a load pad and a plurality of transistor cells electrically connected in parallel between the load pad of the array unit and the drain structure. The current sense unit is electrically connected between a first one of the load pads and the load base structure.

Description

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority to European Patent Application No. 22151383 filed on Jan. 13, 2022, the content of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

Examples of the present disclosure relate to a semiconductor assembly with a semiconductor switching device and a current sense unit. In particular, the present disclosure relates to power modules having a plurality of semiconductor switching devices electrically connected in parallel.

BACKGROUND

Fast overcurrent detection is critical to limit power losses and prevent destruction of power semiconductor switches. A maximum delay between the occurrence of an overload condition and the termination of the overcurrent condition must not exceed a few microseconds.

Typical current sensing power MOSFETs (metal oxide semiconductor field effect transistors) use a mirror principle based on the fact that individual transistor cells of a power MOSFET are well matched. Therefore, a current mirror ratio between transistor cells of a power section and transistor cells of a sense section is inverted to the on-resistance ratio between the power section and the sense section. The total load current can then be determined by measuring the on-state current through the sense section and multiplying the measured sense current by the current mirror ratio.

For this purpose, the source of the sense section is connected to a separate sense pin. Then, when the current sensing power MOSFET is turned on, the current flow splits inversely with respect to the two resistances. In typical current-sensing power MOSFETs, the current mirror ratio between the transistor cells in the power section (source cells) and the transistor cells in the sense section (mirror cells) is on the order of, e.g., 1000:1 or even higher. The sense current can be determined by measuring a voltage across a sense resistor connecting the sense pin and the source. The resistance of the sense resistor affects the current mirror ratio.

There is a need for semiconductor assemblies with easy-to-implement and accurate load current sensing.

SUMMARY

An implementation of the present disclosure relates to a semiconductor assembly that includes a semiconductor switching device, a conductive load base structure and a current sense unit. The semiconductor switching device includes a drain structure and one or more array units, wherein each array unit includes a load pad and a plurality of transistor cells electrically connected in parallel between the load pad of the array unit and the drain structure. The current sense unit is electrically connected between a first one of the load pads and the load base structure.

Another implementation of the present disclosure relates to a semiconductor assembly that includes a semiconductor switching device and a current sense unit. The semiconductor switching device includes a drain structure and one or more array units, wherein each array unit includes a load pad and a plurality of transistor cells electrically connected in parallel between the load pad of the array unit and the drain structure. A current sense unit is electrically connected to a first one of the load pads. For a sense current I_SNS flowing between the first load pad and the current sense unit and a sense inductivity L_SNS effective for the sense current I_SNS, L_SNS*dI_SNS/dt is at least 1.5% of L_LD*dI_LD/dt of a total load current I_LD flowing between the semiconductor switching device and a load and a load inductivity L_LD effective for the total load current I_LD.

Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and on viewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the implementations and are incorporated in and constitute a part of this application. The drawings illustrate implementations of a semiconductor assembly and together with the description serve to explain principles of the implementations. Further implementations are described in the following detailed description and the claims.

FIGS. 1A and 1B illustrate a schematic plan view and a schematic cross-sectional view of a portion of a semiconductor assembly having a current sense unit electrically connected between a load pad of a semiconductor switching device and a conductive load base structure according to an implementation.

FIG. 2 illustrates a schematic block diagram of a portion of a semiconductor assembly according to an implementation related to a current sense unit based on a resistive shunt.

FIG. 3 illustrates a schematic block diagram of a portion of a semiconductor assembly according to an implementation related to a current sense unit based on a magnetic field sensor.

FIG. 4 illustrates a schematic plan view of a semiconductor assembly having a current sense unit electrically connected between two load pads of a semiconductor switching device according to an implementation.

FIG. 5 illustrates a schematic plan view of a semiconductor assembly having a current sense unit electrically connected between a portion of a divided load pad and a conductive load base structure according to an implementation.

FIG. 6 illustrates a schematic plan view of a semiconductor assembly having a current sense unit electrically connected between two load pads of a semiconductor switching device according to an implementation related to additional pad connections.

FIG. 7 illustrates a schematic plan view of a semiconductor assembly having a current sense unit electrically connected between a portion of a divided load pad and another load pad.

FIG. 8 illustrates a schematic plan view of a semiconductor assembly with semiconductor switching devices with and without connection to a current sense unit according to a further implementation.

FIG. 9 illustrates a schematic plan view of a semiconductor assembly with each of a plurality of semiconductor switching devices connected to a current sense unit according to a further implementation.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and in which are shown by way of illustrations specific implementations in which a semiconductor assembly, in particular an IGBT (insulated gate bipolar transistor) power module, may be practiced. It is to be understood that other implementations may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one implementation can be used on or in conjunction with other implementations to yield yet a further implementation. It is intended that the present disclosure includes such modifications and variations. The examples are described using specific language, which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. Corresponding elements are designated by the same reference signs in the different drawings if not stated otherwise.

The terms “having”, “containing”, “including”, “comprising” and the like are open, and the terms indicate the presence of stated structures, elements or features but do not preclude the presence of additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

The term “electrically connected” describes a permanent low-resistive connection between electrically connected elements, for example a direct, ohmic contact between the concerned elements or a low-resistive connection via a metal and/or heavily doped semiconductor material. An ohmic contact is a non-rectifying electrical junction with a linear or almost linear current-voltage characteristic. The terms “electrically coupled” and “signal-connected” include that one or more intervening element(s) adapted for signal and/or power transmission may be connected between the electrically coupled elements, for example, elements that are controllable to temporarily provide a low-resistive connection in a first state and a high-resistive electric decoupling in a second state.

Ranges given for physical dimensions include the boundary values. For example, a range for a parameter y from a to b reads as a≤y≤b. The same holds for ranges with one boundary value like “at most” and “at least”.

Main constituents of a layer or a structure from a chemical compound or alloy are such elements which atoms form the chemical compound or alloy. For example, copper and aluminum are main constituents of a copper aluminum alloy.

The term “on” is not to be construed as meaning “directly on”. Rather, if one element is positioned “on” another element (e.g., a layer is “on” another layer or “on” a substrate), a further component (e.g., a further layer) may be positioned between the two elements (e.g., a further layer may be positioned between a layer and a substrate if the layer is “on” the substrate).

As regards structures and doped regions formed in a substrate, a second region is “below” a first region, if a minimum distance between the second region and a first substrate main surface at the front side of the substrate is greater than a maximum distance between the first region and the first substrate main surface. The second region is “directly below” the first region, where the vertical projections of the first and second regions into the first substrate main surface overlap. The vertical projection is a projection orthogonal to the first substrate main surface.

A safe operating area (SOA) defines voltage and current conditions over which a semiconductor device can be expected to operate without self-damage. The SOA is given by published maximum values for device parameters like maximum continuous load current, maximum gate voltage and others.

The term “power semiconductor device” refers to semiconductor devices with high voltage blocking capability of at least 30V, e.g., 100V, 600V, 3.3 kV or more and with a nominal on-state current or forward current of at least 1 A, e.g., e.g., 10 A or more.

A semiconductor die includes the semiconducting portions of a semiconductor device and further structures typically formed at wafer level. For example, the semiconductor die may include a front side metallization at a front side and a back side metallization at a side opposite to the front side. The front side metallization may include one or more metal pads. A load current may flow from the metal pads through the semiconductor die to the back side metallization or from the back side metallization to the metal pads.

A semiconductor device includes at least one semiconductor die and at least one further structure typically formed after separation of the semiconductor die from a wafer composite. For example, a semiconductor device may include a semiconductor die, terminals, and bond wires connecting the terminals with the metal pads on the semiconductor die.

An implementation of the present disclosure relates to a semiconductor assembly that may include a semiconductor switching device, a conductive load base structure and a current sense unit. The semiconductor switching device may include a drain structure and one or more array units, wherein each array unit includes a load pad and a plurality of transistor cells electrically connected in parallel between the load pad of the array unit and the drain structure. The current sense unit is electrically connected between a first one of the load pads and the load base structure.

The semiconductor assembly may include several power components, e.g., power semiconductor devices such as semiconductor switches, diodes, sensors, protection circuits, and/or control circuits. For example, the semiconductor assembly may be a power module including a power electronic substrate and semiconductor devices provided as bare semiconductor dies attached to the power electronic substrate, e.g., by soldering or sintering. The power electronic substrate may be a PCB (printed circuit board) or a DBC (direct bonded copper) substrate. The power module may include the electronic components of a bridge rectifier, a half bridge, an H-bridge, a full bridge (poly-phase bridge), a PFC (power factor correction) circuit, a PIM (power integrated module) or an IPM (intelligent power module), by way of example.

The semiconductor switching device may be a silicon MOSFET, a silicon IGBT, e.g., a reverse-conducting IGBT (RC-IGBT), or a semiconductor switch from a wide band gap material, e.g., a SiC MOSFET (silicon carbide MOSFET) or a GaN HEMT (gallium nitride high electron mobility transistor).

In particular for silicon and silicon carbide switching devices, the drain structure may include a horizontal drift layer of a conductivity type corresponding to the channel type of the transistor cells. The drift layer may be comparatively lightly doped. For transistor cells with electron channel (n-channel), the drift layer is n conductive and for transistor cells with hole channel (p-channel) the drift layer is p conductive. The semiconductor switching device may further include a metal rear side electrode. For MOSFETs, a heavily doped contact layer of the conductivity type of the drift layer electrically connects the drain structure with the rear side electrode. For IGBTs, a heavily doped contact layer with a conductivity type opposite to that of the drift layer or with zones of both conductivity types electrically connects the drain structure with the rear side electrode. The drain structure may include a more heavily doped layer of the conductivity type of the drift layer between the drift layer and the contact layer.

The number of transistor cells is a function of the nominal output current of the semiconductor switching device. The transistor cells can be grouped in several array units, e.g., to enable control signals arriving at each of the transistor cells within limited delay time. The array units have a same vertical configuration and include the same type of transistor cells. In particular, the transistor cells of all array units are matched and have the same lateral dimensions, the same center-to-center distances to neighboring transistor cells and the same electrical target parameters. The gate electrodes of the transistor cells of all array units may be electrically connected with each other.

The number of array units is a function of the nominal output current of the semiconductor switching device and may be in a range from 1 to about 20.

The load pads are formed at a front side of the semiconductor device. Vertical and lateral dimensions of each load pad and internal configuration of each load pad are such that each load pad forms a suitable wire bond base for wire bonding. The semiconductor device may include two or more load pads, e.g., four, six, eight or more. The load pads are laterally separated from each other. In particular, the first load pad is laterally separated from all second load pads. The second load pads may lack or may have a conductive connection formed, e.g., by a metal structure at the front side of the semiconductor device.

The lateral cross-sectional area of each load pad may be sufficiently large for providing a suitable base for a bond wire connection that carries a current of at least 100 mA, of at least 500 mA, or even several Ampere. In each array unit, the transistor cells are formed directly below the load pad of the array unit, wherein a density of the transistor cells may be approximately the same in all array units.

In particular, the first load pad and all second load pads have the same vertical configuration. The first load pad is used as sense pad. The current tapped from the first load pad represents the sense current.

The load base structure can be or include a metal structure formed on the surface of the power electronic substrate, e.g., a flat copper plate formed on a resin substrate.

The current sense unit may measure the sense current by measuring a voltage drop caused by the sense current across a low-ohmic shunt, by measuring a voltage induced by the magnetic field around a conductor through which the sense current flows and/or by using current compensation.

The sense current is a portion of the load current tapped from an arbitrary one of the load pads and diverted through the current sense unit. The lateral area of the load pad corresponds to the lateral area and the total channel width of the corresponding array unit such that the sense current can be tailored by the size of the first load pad, wherein the sense current tapped from the first load pad may be in the same order of magnitude as the total load current or one magnitude lower than the total load current.

In particular, the sense current is comparatively high and can be at least 1% at least 5%, at least 10% or 100% of the total load current in case of a semiconductor switching device with one single load pad

Similar to typical current sensing power MOSFETs, the present implementation uses a mirror principle based on the fact that the on-state resistances of the individual transistor cells in a power MOSFET are well matched so that a load/sense current ratio is equal to the ratio of the on-state resistance of one of the array units and the other array units. Then the total load current IL can be determined by multiplying the measured sense current IS by the load/sense current ratio.

A typical current sensing power MOFET includes a sense pin (“mirror pin”) connected to the sources of the sense transistor cells. A sense resistor is connected between the sense pin and a load pin connected to the sources of the load transistor cells. The sense current is determined by measuring a voltage drop across the sense resistor. Since a high sense resistance affects the current mirror ratio, a low sense resistance is typically selected so that the sense current in the on-state produces only a comparatively small voltage drop across the sense resistor. On the other hand, the load/sense current ratio between the load transistor cells and the sense transistor cells is on the order of 1000:1 so the sense current is low.

Therefore, even a short-circuit current generates only a low voltage across the sense resistor and it is difficult to distinguish between actual critical overload conditions and non-critical voltage transients caused, for example, by stray capacitance charging or coupling from noisy circuit environment.

Input filter can suppress voltage transients but also delay the detection of actual critical overload conditions. Active circuits to match the potentials at the sources of the load transistor cells and at the sources of the sense transistor cells require complex and expensive additional circuitry. Furthermore, the sense pad requires additional area on the front side of the semiconductor device, wherein the additional area required for the sense pad may be significantly larger than the area of the sense transistor cells.

On the other hand, a much higher fraction of the total load current is tapped as sense current in the semiconductor assembly according to the implementations. The sense current may be greater than 100 mA, e.g., greater than 500 mA or greater than 1 A. The comparatively high sense current produces a comparatively high voltage drop even if a small sense resistance is used. True overcurrent events can be more easily distinguished from non-critical transient current spikes. Accordingly, the L*dI/dt of the sense current is much closer to the L*dI/dt of the total load current than in such current sensing power MOSFTs, where the sense current is typically less than 1/1000 of the load current. The dynamic response of the sense current can more reliably reflect the dynamic response of the total load current.

The evaluation of overcurrent events is more reliable against noise. No additional sensor pad or sensor pin is required on the semiconductor device, which is configured only to tap the sense current. That is, no additional chip design is required to implement the sensing option. The same semiconductor device can be used with or without the sense option. Applications based on current sensing (e.g., overcurrent detection) can be implemented with little additional effort and complexity.

According to an implementation, the transistor cells may be formed directly between the load pad and the drain structure in each array unit.

In particular, the transistor cells of each array unit may be formed completely within the contour of the load pad of the concerned array unit, so that all transistor cells of the same array unit are formed directly below the load pad of the array unit. In other words, the transistor cells of an array unit are formed within a vertical projection of the load pad of the array unit.

In implementations, when the semiconductor switching device is in a nominal on-state, a current density of a current flowing through the first load pad is similar to a current density of a current flowing through at least one of the second load pads. Similar means, for example, that the current density in the first load pad is between 50% and 150% of the current density in the at least one second load pad, preferably between 75% and 125% of the current density in the at least one second load pad, and more preferred between 85% and 115% of the current density in the at least one second load pad. Variations of the current density between different loads pads may be due to local variations of electric and magnetic fields and/or variable resistances along a current flow path due to manufacturing tolerances, for example.

According to an implementation, the current sense unit may include a resistive shunt electrically connected between the first load pad and the load base structure or between the first load pad and one of the second load pads.

The resistance of the resistive shunt can be greater than 1 mΩ, and less than 50 mΩ, e.g., in a range from 1 mΩ to 20 mΩ. A typical voltage drop across the resistive shunt in the on-state of the semiconductor device may be in a range of 10 mV to 40 mV at typical operating currents. In the event of an overcurrent event or a short circuit, the voltage drop can increase by a factor between 2 and 10.

The resistive shunt may include a metal line at a thickness of 1 μm to 20 μm on a surface of a semiconductor die of the current sense unit. The metal line may contain or consist of aluminum Al or copper Cu. A width of a metal line from copper may be about 150 μm for an expected overcurrent of 10 A. The length of the metal line may be about 1 mm, wherein the metal line can be straight or can form a meander line.

According to an implementation, the current sense unit may include a magnetic field sensor configured to sense a magnetic field caused by a current flowing between the first load pad and the load base structure or between the first load pad and one of the second load pads.

The magnetic field sensor may include a magnetic Hall Effect sensor or a sensor based on a magneto resistance effect, e.g., a GMR (giant magnetoresistance) sensor or a TMR (tunnel magnetoresistance) sensor, by way of example.

According to an implementation, the semiconductor assembly may further include one or more load connection structures, wherein each load connection structure electrically connects the load base structure and one or more second ones of the load pads.

In particular, each load connection structure may include one or more bond wires, each of them with at least one bond foot formed directly on at least one second load pad and with at least one bond foot formed directly on the load base structure.

According to an implementation, at least one of the load connection structures may electrically connect the load base structure and two of the second load pads.

In particular, each load connection structure may include one or more bond wires with at least one bond foot formed directly on each of the second load pads connected to the load connection structure and with at least one bond foot formed directly on the load base structure.

According to an implementation, the semiconductor assembly may further include a gate pad and gate connection lines. The gate pad is laterally separated from the load pads. The gate connection lines may be electrically connected with the gate pad and are formed in pad gaps between neighboring ones of the load pads.

The gate connection lines distribute the gate signal evenly among the transistor cells and avoid large differences in propagation times. The gate connection lines divide a front side of the switching device semiconductor die into array units of approximately the same size. The load pad formed in one of the array units can be used as sense pad without redesigning of the metallization layout.

In other words, each one of the plurality of load pads of the semiconductor switching device can be selected to be used as the first load pad. Whether or not a specific one of the plurality of load pads is used as first load pad as discussed herein is defined by the wiring of the respective load pad. In particular, the current that runs through the first load pad and that is used for sensing the load current still contributes to the total load current through the semiconductor switching device. Additionally, the first load pad and the second load pads may be substantially equal, for example they may have a similar geometry and area. In such case, the current running through each of the load pads is determined by the current density in the semiconductor switching device.

In a case where the nominal current through each one of such essentially identical load pads (first and second load pads) may reach too high levels to be used for sensing the load current, which may be the case for some applications, then the area of one of the load pads may be reduced, for example by splitting the load pad into sub-load pads having a reduced size. As an example, the load pad may be split in half, resulting in two sub-load pads having about 50% of the area of the original load pad. The area ratio of the resulting sub-load pads may vary, such that the resulting sub-load pads have different areas. For example, the load pad may be split such that the area ratio of the resulting sub-load pads is 70% to 30%, or 20% to 80%, or the like. Furthermore, the load pad may be split into more than two sub-load pads, which can be useful to reach a predefined area and a predefined shape of the sub-load pad. The sub-load pad or sub-load pads that are not selected to be used as the first load pad can still be used as one of the second load pads, such that the whole surface area of the chip is used. The areas of each of the sub-load pads that are obtained through such splitting are, preferably, still large enough to be connected by using the same interconnect technology as used for the other second load pads, for example using the same diameter of a wire bond or the same clip technology. Also here, the respective functionality of each sub-load pad is defined by its wiring to be either the first load pad or second load pad.

In particular, semiconductor switching devices with gate pad and gate connection lines formed in pad gaps between adjacent load pads can be used without modification for the present implementations.

In implementations, the gate connection lines are running along and next to at least two sides of the first load pad, preferably along and next to at least three sides of the first load pad, and more preferably along and next to all sides of the first load pad. Here, “next to” means, for example, that the gate connection lines are directly adjacent to the respective side of the first load pad. A “side” of a load pad may be understood as a section of a lateral edge of the load pad that extends in an essentially straight line. For example, the first load pad may have an essentially rectangular shape, and the gate connection lines run along and next to two of the four sides of the rectangle formed by the first load pad. The two sides with adjacent gate connection lines can be joined (e.g., forming an “L”) or can be arranged on opposite sides of the rectangular shape. Here, “essentially rectangular” means, for example, that the rectangle may have rounded corners, wherein the curvature radii of different corners may be different to each other. When the gate connection lines run along all sides of the first load pad, the gate connection lines enclose the first load pad.

According to an implementation, a first terminal of the current sense unit may be directly connected to the first load pad and a second terminal of the current sense unit may be directly connected to the load base structure.

According to another implementation, a first terminal of the current sense unit may be directly connected to the first load pad and a second terminal of the current sense unit may be directly connected to one of the second load pads.

In this way, the parasitic inductance effective for the sense current can be better matched with the parasitic inductance effective for the load current and the dynamic response of the sense current is better matched with the dynamic response of the load current.

According to an implementation, the current sense unit may include an overcurrent detection circuit configured to evaluate a current flowing through the current sense unit between the first load pad and the load base structure or between the first load pad and one of the second load pads.

By tapping a comparatively high sense current at one of the load pads, the overcurrent detection circuit works reliably even in noisy circuits.

According to an implementation, a first sense connection structure between the first load pad and the current sense unit has a first inductance, a second sense connection structure between the current sense unit and the load base structure or between the current sense unit and one of the second load pads has a second inductance, a load connection structure between one of the second load pads and the load base structure has a third inductance, and a difference between the third inductance and the sum of the first and second inductances is less than 50% of the sum of the first, the second and the third inductances.

With the comparatively low difference between the parasitic inductances effective for the load transistor cells and the sense transistor cells, the sense current rather precisely images the dynamic response of the load current. A true overload condition can be distinguished with high reliability from non-critical transients.

For example, the first and second sense connection structures and the load connection structures include bond wires of the same material and cross-sectional area. Then, the first sense connection structure between the first load pad and the current sense unit has a first length, the second sense connection structure between the current sense unit and the load base structure or between the current sense unit and one of the second load pads has a second length, the load connection structure between one of the second load pads and the load base structure has a third length, and a difference between the third length and the sum of the first and second lengths is less than 50% of the sum of the first, the second and the third lengths.

In particular, a shortest distance between the first load pad and the current sense unit can be smaller than a shortest distance between the first load pad and the load base structure.

According to an implementation, the semiconductor assembly may include at least two of the semiconductor switching devices wherein the current sense unit is electrically connected between the load base structure and the first load pad of one of the semiconductor switching devices.

For example, the semiconductor assembly may include fewer current sense units than semiconductor switching devices, and at least one of the semiconductor switching devices is not connected to a current sense unit. In particular, the semiconductor assembly may include one single current sense unit, and all but one the semiconductor switching devices are without connection to a current sense unit.

According to another implementation, the semiconductor assembly may include at least two of the semiconductor switching devices and at least two of the current sense units, wherein a first one of the current sense units is electrically connected between the load base structure and the first load pad of a first one of the semiconductor switching devices, and wherein a second one of the current sense units is electrically connected between the load base structure and the first load pad of a second one of the semiconductor switching devices.

In particular, the semiconductor assembly may include the same number of semiconductor switching devices as current sense units, each of the current sense units being electrically connected between the load base structure and a first load pad of one of the semiconductor switching devices.

Another implementation of the present disclosure relates to a semiconductor assembly that may include a semiconductor switching device and a current sense unit. The semiconductor switching device may include a drain structure and one or more array units, wherein each array unit includes a load pad and a plurality of transistor cells electrically connected in parallel between the load pad of the array unit and the drain structure. The current sense unit is electrically connected to a first one of the load pads. L_SNS*dI_SNS/dt of a sense current I_SNS flowing between the first load pad and the current sense unit and of a sense inductivity L_SNS effective for the sense current I_SNS is at least 1.5% of L_LD*dI_LD/dt of a total load current I_LD flowing between the semiconductor switching device and a load and of a load inductivity L_LD effective for the total load current I_LD.

With the comparatively low difference between the parasitic inductances effective for the load transistor cells and the sense transistor cells, the sense current rather precisely images the dynamic response of the load current. A true overload condition can be distinguished with high reliability from non-critical transients.

Another implementation of the present disclosure relates to a semiconductor assembly that may include a semiconductor switching device and a current sense unit. The semiconductor switching device may include a drain structure and one or more array units, wherein each array unit includes a load pad and a plurality of transistor cells electrically connected in parallel between the load pad of the array unit and the drain structure. The current sense unit is electrically connected to a first one of the load pads. In a nominal on-state of the semiconductor switching device, a sense current I_SNS flowing between the first load pad and the current sense unit may be in a range from 0.5 A to 20 A, e.g., in a range from 1 A to 10 A.

The nominal on-state of the semiconductor switching device is to be understood as an operational mode of the semiconductor switching device within the SOA, wherein the load current does not exceed an allowable maximum nominal load current defined for the switching device, e.g., in a data sheet. The nominal load current may be, e.g., the maximum continuous collector current of an IGBT or the maximum continuous drain current of an MOSFET, by way of example. The nominal on-state does not include the operation of the semiconductor switching device in a short-circuit mode or under any other overcurrent conditions for which a load current greater than the nominal load current is allowed only for a short time or for periodic intervals.

The current sense unit may be configured to reliably handle overcurrent events or short circuit events where the current level may be a multiple of the nominal current, e.g., twice, three times or up to five times of the nominal current.

In particular, the current sense unit may be configured to reliably handle short-time sense currents up to 20 A, e.g., up to 30 A or even more and a continuous sense current up to 10 A or up to 20 A.

The high sense current may reliably prevent interpretation of transients as would-be overcurrent conditions.

According to an implementation, the semiconductor assembly may be configured such that in the on-state of the semiconductor switching device, the sense current I_SNS is at least 1% of the total load current I_LD.

FIGS. 1A-1B illustrate a portion of a semiconductor assembly 400 that includes a semiconductor switching device 100, a load base structure 422 and a current sense unit 200.

The semiconductor switching device 100 may be present as semiconductor die, e.g., as bare die of a MOSFET or an IGBT, e.g., of a reverse blocking IGBT or of an RC-IGBT (reverse conducting IGBT), wherein the semiconductor die includes a semiconductor body 120 mainly formed from a single crystalline semiconductor material, for example silicon (Si), germanium (Ge), a silicon-germanium crystal (SiGe), silicon carbide (SiC), gallium nitride (GaN) or gallium arsenide (GaAs), by way of example.

The semiconductor body 120 has a first surface 101 on the front side. In a horizontal plane parallel to the first surface 101, the semiconductor body 120 may have a rectangular shape. A normal to the first surface 101 defines a vertical direction, and directions orthogonal to the vertical direction are lateral directions (horizontal directions). The semiconductor body 120 includes a drain structure 121 that may extend horizontally through the semiconductor body 120. The drain structure 121 may include a heavily doped contact layer 129 formed along a second surface on the backside of the semiconductor body 120.

A front side metallization on the first surface 101 includes one or more load pads 122, a gate pad 131 and gate connection lines 132 electrically connected with the gate pad 132. Pad gaps 199 laterally separate adjacent load pads 122 completely or at least partially from each other. The gate connection lines 132 are formed in the pad gaps 199. A gate runner 133 may form a closed frame or open frame around the one or more load pads 122. A backside metallization 140 is formed on the second surface on the backside of the semiconductor body 120. The backside metallization 140 and the contact layer 129 form a low-resistive ohmic contact.

The semiconductor switching device 100 includes a plurality of array units AU. Each array unit AU includes one of the load pads 122 and transistor cells TC. The load paths of the transistor cells TC are electrically connected between the load pad 122 of the respective array unit AU and the drain structure 121. In particular, the load pads 122 and the sources of the transistor cells TC form low-resistive ohmic contacts. The gate runners 133 and the gate connection lines 132 electrically connect the gates of the transistor cells TC with the gate pad 131.

The load pads 122 may include aluminum or copper as the only main constituent or as one of several main constituents. For example, the load pads 122 may include a copper alloy, e.g., a copper aluminum alloy (CuAl) with or without silicon (Si), or an aluminum alloy, e.g., AlSi or AlSiCu.

The switching assembly 400 further includes a module substrate 410. The module substrate 410 may be formed from a ceramic material or a resin. Laterally separated conductive structures may be formed on a mounting surface on a components side of the module substrate 410. The conductive structures include a collector plate 421 and a load base structure 422. The collector plate 421 and the load base structure 422 are thin, flat metallic plates, e.g., from copper or a copper alloy.

The semiconductor switching device 100 is soldered or sintered onto the collector plate 421. In the illustrated example, a solder layer 140 formed between the backside metallization 140 and the collector plate 421 connects the semiconductor switching device 100 and the module substrate 410.

A first sense connection structure 412-1 electrically connects a first load pad 122-1 and a current sense unit 200. The first load pad 122-1 is laterally separated from adjacent load pads 122, in particular from all directly neighboring second load pads 122-2. A second sense connection structure 412-2 electrically connects the current sense unit 200 and the load base structure 422. Load connection structures 411 electrically connect second load pads 122-2 and the load base structure 422. Each of the first sense connection structure 412-1, the second sense connection structure 412-2, and the load connection structures 411 may include one or more bond wires, metal clips or strip lines.

In an on-state of the semiconductor switching device 100, a sense current I_SNS flowing between the first load pad 122-1 and the current sense unit 200 may be, e.g., up to 10 A.

In FIG. 2 the current sense unit 200 includes a further semiconductor die and a resistive shunt 211 electrically connecting the first sense connection structure 412-1 and the second sense connection structure 412-2. The resistive shunt 211 may be a metal strip conductor formed on a surface of the further semiconductor die. The sense current I_SNS tapped from the first load pad 122-1 flows through the resistive shunt 211 and produces a voltage drop Vm across the resistive shunt 211. The first sense connection structure 412-1, the second sense connection structure 412-2, and the resistive shunt 211 are configured to carry a continuous sense current of up to 10 A and short overcurrents of at least twice of the continuous sense current.

The further semiconductor die may include an overcurrent detection circuit 220 that measures the voltage drop Vm across the resistive shunt 211, compares the measured voltage drop Vm with a predetermined threshold voltage and outputs an active overcurrent signal OC, when the measured voltage drop Vm exceeds the predetermined threshold voltage.

In FIG. 3 the current sense unit 200 includes a semiconductor die with a magnetic field sensor 212 adapted to sense the magnetic field strength of a magnetic field generated by the sense current I_SNS tapped from the first load pad 122-1. The semiconductor die includes an overcurrent detection circuit 220 compares a voltage VH induced by the magnetic field of the sense current I_SNS, compares the induced voltage VH with a predetermined threshold voltage and outputs an active overcurrent signal OC, when the induced voltage VH exceeds the predetermined threshold voltage. The first sense connection structure 412-1 and the second sense connection structure 412-2 are configured to carry a continuous sense current of up to 10 A. The magnetic field sensor 212 is configured to be sensitive for continuous sense currents up to 10 A and overcurrents of at least twice of the continuous sense current.

In FIG. 4, the second sense connection structure 412-2 is in direct contact with the current sense unit 220 and a second load pad 122-2. A load connection structure 411 electrically connects the load base structure 422 and the second load pad 122-2 to which the second sense connection structure 412-2 is connected.

The first and second sense connection structures 412-1, 412-2 and the load connection structures 411 include bond wires of the same material and cross-sectional area. Then, the first sense connection structure 412-1 has a first length a1, the second sense connection structure 412-2 has a second length a2, the load connection structures 411 between one of the second load pads and the load base structure 422 have a mean third length a3, and a difference between the mean third length a3 and the sum a1+a2 of the first and second lengths is less than 50% of the sum a1+a2+a3 of the first, the second and the mean third lengths. As a consequence, the difference between the inductance of one of the load connection structures 411 and the total inductance of the first and second sense connection structures 412-1, 412-2 is comparatively low.

In FIG. 5, an auxiliary gap 191 laterally divides the first load pad 122-1 into a first load pad portion 122-11 and a second load pad portion 122-12. A load connection structure 411 directly connects the first load pad portion 122-11 and the load base structure 422. A first sense connection structure 412-1 electrically connects the second load pad portion 122-12 and the current sense unit 200. A second sense connection structure 412-2 directly connects the current sense unit 200 and the load base structure 422. Dividing the first load pad 122-1 reduces the maximum sense current I_SNS and prevents the current sense unit 200 from being damaged by high current under overcurrent conditions.

In FIG. 6, inter pad connections 413 directly connect neighboring second load pads 122-2 that are not connected through load connection structures 411. The inter pad connections 413 can reduce parasitic inductances in semiconductor switching devices 100 with multiple load pads 122-2. Each inter pad connection 413 may include one or more bond wires, a suitably formed metal clip or one or more interruptions in the pad gaps 199. The inter pad connections 413 are without connection to the first load pad 122-1. In other words, only the first sense connection structure 412-1 is in direct contact with the exposed surface of the first load pad 122-1.

In FIG. 7, an auxiliary gap 191 laterally divides the first load pad 122-1 into a first load pad portion 122-11 and a second load pad portion 122-12. A load connection structure 411 directly connects the first load pad portion 122-11 and the load base structure 422. A first sense connection structure 412-1 electrically connects the second load pad portion 122-12 and the current sense unit 200. A second sense connection structure 412-2 directly connects the current sense unit 200 and a second load pad 122-2. A load connection structure 411 electrically connects the load base structure 422 and that second load pad 122-2 to which the second sense connection structure 412-2 is connected.

FIG. 8 shows two semiconductor switching devices 100 of the same type and one current sense unit 200 electrically connected between the load base structure 422 and the first load pad 122-1 of one of the semiconductor switching devices 100 of the semiconductor assembly 400. The semiconductor switching devices 100 electrically connected in parallel and are soldered or sintered onto the same collector plate 421.

The current sense unit 200 includes a semiconductor die soldered or sintered on a sense base structure 423. A first terminal 201 and a second terminal 202 are formed on a front side of the semiconductor die. The first terminal 201 and the second terminal 202 may be pads suitable as base for wire bonds. A resistive shunt 211 is electrically connected between the two terminals 201, 202.

An auxiliary gap 191 laterally divides the first load pad 122-1 into a first load pad portion 122-11 and a second load pad portion 122-12. A load connection structure 411 directly connects the first load pad portion 122-11 and the load base structure 422. A first sense connection structure 412-1 directly connects the second load pad portion 122-12 and the first terminal 201. A second sense connection structure 412-2 directly connects the second terminal 202 and the load base structure 422.

A shortest distance d1 between the second load pad portion 122-12 and the first terminal 201 is smaller than a shortest distance d2 between the second load pad portion 122-12 and the connections on the load base structure 422, in particular between the second load pad portion 122-12 and that bond food, that connects the direct load connection 411 of the first load pad portion 122-11 with the load base structure 422.

FIG. 9 shows a semiconductor assembly 400 that includes at least two semiconductor switching devices 100 and at least two current sense units 200. A first current sense units 200 is electrically connected between the load base structure 422 and the first load pad 122-1 of a first one of the semiconductor switching devices 100 a second current sense unit 200 is electrically connected between the load base structure 422 and the first load pad 122-1 of a second one of the semiconductor switching devices 100.

Claims

1. A semiconductor assembly, comprising: a semiconductor switching device comprising a drain structure and a plurality of array units, wherein each array unit of the plurality of array units comprises a respective load pad of a plurality of load pads and a respective plurality of transistor cells electrically connected in parallel between the respective load pad of the array unit and the drain structure;a conductive load base structure; anda current sense circuit electrically connected between a first load pad of the plurality of load pads and the conductive load base structure.

2. The semiconductor assembly according to claim 1, wherein, in each array unit of the plurality of array units, the respective plurality of transistor cells are formed directly between the respective load pad of the array unit and the drain structure.

3. The semiconductor assembly according to claim 1, wherein the current sense circuit comprises a resistive shunt electrically connected between the first load pad and the conductive load base structure or electrically connected between the first load pad and a second load pad of the plurality of load pads.

4. The semiconductor assembly according to claim 1, wherein the current sense circuit comprises a magnetic field sensor configured to sense a magnetic field produced by a current flowing between the first load pad and the conductive load base structure or a current flowing between the first load pad and a second load pad of the plurality of load pads.

5. The semiconductor assembly according to claim 1, further comprising: a first load connection structure, wherein the first load connection structure electrically connects the conductive load base structure and a second load pad of the plurality of load pads.

6. The semiconductor assembly according to claim 5, wherein the first load connection structure electrically connects the conductive load base structure, the second load pad, and a third load pad of the plurality of load pads.

7. The semiconductor assembly according to claim 1, further comprising: a gate pad, wherein the gate pad is laterally separated from the plurality of load pads; andgate connection lines electrically connected with the gate pad, wherein the gate connection lines are formed in pad gaps between neighboring load pads of the plurality of load pads.

8. The semiconductor assembly according to claim 1, wherein a first terminal of the current sense circuit is directly connected to the first load pad and a second terminal of the current sense circuit is directly connected to the conductive load base structure.

9. The semiconductor assembly according to claim 1, wherein a first terminal of the current sense circuit is directly connected to the first load pad and a second terminal of the current sense circuit is directly connected to a second load pad of the plurality of load pads.

10. The semiconductor assembly according to claim 1, wherein the current sense circuit comprises an overcurrent detection circuit configured to evaluate a current flowing through the current sense circuit between the first load pad and the conductive load base structure or a current flowing between the first load pad and a second load pad of the plurality of load pads.

11. The semiconductor assembly according to claim 1, further comprising: a first sense connection structure coupled between the first load pad and the current sense circuit, wherein the first sense connection structure has a first inductance;a second sense connection structure coupled between the current sense circuit and the conductive load base structure or coupled between the current sense circuit and a second load of the plurality of load pads, wherein the second sense connection structure has a second inductance; anda direct load connection structure coupled between the second load pad and the conductive load base structure, wherein the direct load connection structure has a third inductance,wherein a difference between the third inductance and the sum of the first inductance and the second inductances is less than 50% of the sum of the first inductance, the second inductance, and the third inductance.

12. The semiconductor assembly according to claim 1, wherein the semiconductor switching device is a first semiconductor switching device, andwherein the semiconductor assembly further comprises: a second semiconductor switching device comprising a second drain structure and a plurality of second array units,wherein each second array unit of the plurality of second array units comprises a respective second load pad of a plurality of second load pads and a respective plurality of second transistor cells electrically connected in parallel between the respective second load pad of the second array unit and the second drain structure.

13. The semiconductor assembly according to claim 12, further comprising: a second current sense circuit electrically connected between a second load pad of the plurality of second load pads and the conductive load base structure.

14. A semiconductor assembly, comprising: a semiconductor switching device comprising a drain structure and an array unit, wherein the array unit comprises a load pad and a plurality of transistor cells electrically connected in parallel between the load pad of the array unit and the drain structure; anda current sense circuit electrically connected to the load pad,wherein in a nominal on-state of the semiconductor switching device, a sense current flowing between the load pad and the current sense circuit is in a range from 0.5 A to 20 A.

15. The semiconductor assembly according to claim 14, wherein the semiconductor assembly is configured such that, in the on-state of the semiconductor switching device, the sense current is at least 1% of a total load current.

16. The semiconductor assembly according to claim 5, further comprising: a second load connection structure that electrically connects the conductive load base structure and a third load pad of the plurality of load pads.

17. The semiconductor assembly according to claim 6, further comprising: a second load connection structure that electrically connects the conductive load base structure and a fourth load pad of the plurality of load pads.

18. The semiconductor assembly according to claim 1, further comprising: a first sense connection structure coupled between the first load pad and the current sense circuit, wherein the first sense connection structure has a first inductance;a second sense connection structure coupled between the current sense circuit and the conductive load base structure or coupled between the current sense circuit and a second load of the plurality of load pads, wherein the second sense connection structure has a second inductance; anda direct load connection structure coupled between a third load pad of the plurality of load pads and the conductive load base structure, wherein the direct load connection structure has a third inductance,wherein a difference between the third inductance and the sum of the first inductance and the second inductances is less than 50% of the sum of the first inductance, the second inductance, and the third inductance.

19. A semiconductor assembly, comprising: a semiconductor switching device comprising a drain structure and an array unit,wherein the array unit comprises a load pad and a plurality of transistor cells electrically connected in parallel between the load pad and the drain structure;a conductive load base structure; anda current sense circuit electrically connected between the load pad and the conductive load base structure.

20. The semiconductor assembly according to claim 19, wherein the current sense circuit comprises a resistive shunt electrically connected between the first load pad and the conductive load base structure or electrically connected between the first load pad and a second load pad of the plurality of load pads, orwherein the current sense circuit comprises a magnetic field sensor configured to sense a magnetic field produced by a current flowing between the first load pad and the conductive load base structure or a current flowing between the first load pad and a second load pad of the plurality of load pads.