SEMICONDUCTOR CAPACITOR, ONE TIME PROGRAMMABLE MEMORY CELL AND FABRICATING METHOD AND OPERATING METHOD THEREOF

Abstract

A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source region and the drain region are disposed in the substrate at the sides of the gate, respectively. The capacitor dielectric layer is disposed on the source region. The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned salicide block layer. The conductive plug is disposed on the capacitor dielectric layer. The conductive plug is served as a first electrode of a capacitor and the source region is served as a second electrode of the capacitor. The one time programmable memory (OTP) cell is programmed by making the capacitor dielectric layer breakdown.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features and advantages of the present invention will be described and become more apparent from the detailed description of exemplary embodiments when read in conjunction with accompanying drawings.

FIG. 1A is a schematic top view illustrating a semiconductor capacitor according to a preferred embodiment of the present invention.

FIGS. 1B and 1C are top views illustrating a semiconductor capacitor according to another preferred embodiment of the present invention, respectively.

FIG. 2A is a cross-sectional view taken along line A-A′ in FIG. 1A.

FIGS. 2B to 2D are cross-sectional views illustrating other preferred embodiments of the semiconductor capacitor according to the present invention, respectively.

FIG. 3A is a schematic view of a one time programmable memory cell according to a preferred embodiment of the present invention.

FIGS. 3B and 3C are schematic circuit diagrams of the one time programmable memory cell according to the present invention.

FIGS. 4A to 4B are schematic views illustrating programming operation of an N type memory cell, respectively.

FIGS. 5A to 5B are schematic views illustrating programming operation of a P type memory cell, respectively.

FIGS. 6A to 6E are cross-sectional views illustrating a manufacturing process of a one programmable memory cell according to one preferred embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

The present invention provides a semiconductor capacitor, a one time programmable memory cell having the semiconductor capacitor and a fabricating method and an operating method thereof.

At first, a semiconductor capacitor according to the present invention will be described.

FIG. 1A is a schematic top view illustrating a semiconductor capacitor according to a preferred embodiment of the present invention. FIG. 2A is a cross-sectional view taken along line A-A′ in FIG. 1A. FIGS. 1B and 1C are top views illustrating a semiconductor capacitor according to another preferred embodiment of the present invention, respectively. The members in FIGS. 1B and 1C that are same with those in FIG. 1A will be designated by same reference numbers, respectively and their illustrations will be omitted.

Please refer to FIGS. 1A and 2A, a semiconductor capacitor according to the present invention is disposed on a substrate 100, for example. The substrate 100 is provided with an isolation structure 102 to define an active area. For example, the isolation structure 102 is a shallow trench isolation structure or a field oxide layer. The semiconductor capacitor is formed from a conductive plug 112 (first electrode), a capacitor dielectric layer 106 and a doped region 104 (second electrode). The conductive plug 112 (first electrode) and the doped region 104 (second electrode) are served as electrodes of the semiconductor capacitor.

For example, the substrate 100 is a silicon substrate. The capacitor dielectric layer 106 is, for example, a resistive protection oxide layer or a self-aligned silicide block layer commonly used in semiconductor manufacturing process. The material of the capacitor dielectric layer 106 is silicon oxide, silicon nitride or other dielectric material (e.g. high-k material).

The conductive plug 112 (first electrode) and the doped region 104 (second electrode) are disposed at the opposing sides of the capacitor dielectric layer 106. The doped region 104 (second electrode) is disposed in the substrate 100, for example. The capacitor dielectric layer 106 is, for example, disposed on the doped region 104 (second electrode), and can expose a portion of the doped region 104 (second electrode). The conductive plug 112 (first electrode) is disposed on the capacitor dielectric layer 106. As shown in FIG. 1A, the capacitor dielectric layer 106 only covers a portion of the doped region 104 (second electrode).

For example, a metal silicide layer 108 is disposed on the doped region 104 (second electrode) exposed from the capacitor dielectric layer 106. The material of the metal silicide layer 108 includes metal silicide of refractory metal, such as one silicide of nickel, cobalt, titanium, copper, molybdenum, tantalum, tungsten, erbium, zirconium, platinum and silicide of alloys thereof.

For example, an etch stop layer 110 is disposed on the capacitor dielectric layer 106 and the doped region 104 (second electrode). The material of the etch stop layer 110 is, for example, silicon nitride or silicon oxynitride. The conductive plug 112 (first electrode) extends through the etch stop layer 110 and contacts with the capacitor dielectric layer 106. The etch stop layer 110 plays a very important role in the manufacturing process of the conductive plug 112. The primary reason is that the etch stop layer 110 can give more stably etching process of forming plugs, it can make etching of the plugs to stop at the etch stop layer 110 by utilizing different etching selectivity of different materials. Finally, the etch stop layer 110 is be etched. In present invention, because a resistive protection oxide layer or a self-aligned silicide block layer is disposed under the etch stop layer 110, etching will stop at the resistive protection oxide layer or the self-aligned silicide block layer, the conductive plug 112 (first electrode) of the capacitor dielectric layer 106 is readily formed.

An interlayer insulating layer 116 is further disposed on the etch stop layer 110. The interlayer insulating layer 116 is, for example, phosphorosilicate glass borophosphorosilicate glass etc. The conductive plug 112 (first electrode) and the conductive plug 114 which is electrically connected to the metal silicide layer 108 are disposed in the interlayer insulating layer 116. The material of the conductive plug 112 (first electrode) and the conductive plug 114 includes conductive material such as metal material or doped polysilicon.

Seen from the top view of FIG. 1A, the shape of the conductive plug 112 (first electrode) is, for example, square. Of course, the shape of the conductive plug 112 (first electrode) can also be rectangle as shown in FIG. 1B, or other suitable shapes such as round or oval. Additionally, the first electrode of the semiconductor capacitor in the present invention is not only limited to one. As also shown in FIG. 1C, two or more conductive plugs 112a, 112b (first electrode) is provided.

FIGS. 2B to 2D are cross-sectional views illustrating other preferred embodiments of the semiconductor capacitor according to the present invention, respectively. In FIGS. 2B to 2D, members which are same with those in FIG. 1A are designated by same reference numbers, respectively, and their illustrations will be omitted.

Please refer to FIG. 2B, a semiconductor capacitor is disposed on a silicon on insulator (SOI) substrate 100a, for example. The silicon on insulator substrate 100a is formed from, for example, a substrate layer 101a, an insulating layer 101b and a silicon layer 101c.

The doped region 104 (second electrode) is, for example, disposed in the silicon layer 101c of the silicon on insulator substrate 100a. The capacitor dielectric layer 106 is, for example, disposed on the silicon layer 101c, and exposes a portion of the doped region 104 (second electrode). The conductive plug 112 (first electrode) is, for example, disposed on the capacitor dielectric layer 106.

The metal silicide layer 108 is disposed on the doped region 104 (second electrode) which is exposed on the capacitor dielectric layer 106, and the etch stop layer 110 is disposed on the capacitor dielectric layer 106 and the doped region 104 (second electrode). The interlayer insulating layer 116 is disposed on the etch stop layer 110, for example. The shape of the conductive plug 112 (first electrode) is, for example, square, rectangle or other suitable shapes such as round or oval. The number of the conductive plug 112 (first electrode) is not only limited to one, and can also be two or more.

In the semiconductor capacitors shown in FIGS. 2A and 2B, a resistive protection oxide layer or a self-aligned silicide block layer is served as the capacitor dielectric layer 106, and the conductive plug 112 and the doped region 104 are served as electrodes of a capacitor. The doped region 104 is a source/drain region of a transistor or is fabricated together with a source/drain region of a transistor in a same manufacturing process. The conductive plug 112 is fabricated together with plugs connected to a gate, source/drain region of a transistor in a same manufacturing process. Therefore, a capacitor is fabricated without varying the manufacturing process of common complementary metal oxide-semiconductor. No additional space is required, and the integration of semiconductor devices is elevated.

Please refer to FIG. 2C, a semiconductor capacitor is, for example, disposed on an insulating substrate 100b. The insulating substrate 100b is, for example, a glass substrate or a plastic substrate etc.

A doped semiconductor layer 104a (second electrode) is, for example, disposed on the insulating substrate 100b. The material of the doped semiconductor layer 104a is, for example, doped silicon or doped polysilicon etc. The doped semiconductor layer 104a and a gate layer of a transistor are fabricated in a same manufacturing process. That is, while patterning a gate of a MOS transistor, a doped semiconductor layer 104a (second electrode) of a capacitor is defined. Therefore, no other additional steps are required, when the capacitor of the present invention is fabricated. A capacitor dielectric layer 106 is, for example, disposed on the doped semiconductor layer 104a (second electrode), and exposes a portion of the doped semiconductor layer 104a (second electrode). The conductive plug 112 (first electrode) is, for example, disposed on the capacitor dielectric layer 106.

The metal silicide layer 108 is, for example, disposed on the doped semiconductor layer 104a (second electrode) exposed from the capacitor dielectric layer 106 and the etch stop layer 110 is disposed on the capacitor dielectric layer 106 and the doped semiconductor layer 104a (second electrode). The interlayer insulating layer 116 is disposed on the etch stop layer 110, for example. The shape of the conductive plug 112 (first electrode) is, for example, square, rectangle or other suitable shapes such as round or oval. The number of the conductive plug 112 (first electrode) is not only limited to one, and can also be two or more. Additionally, an insulating spacer 118 is, for example, disposed on a sidewall of the doped semiconductor layer 104a. The material of the insulating spacer 118 is, for example, silicon oxide or silicon nitride etc.

Please refer to FIG. 2D, a semiconductor capacitor is, for example, disposed on an isolation structure 102a of the substrate 100.

A doped semiconductor layer 104b (second electrode) is, for example, disposed on the isolation structure 102a. The material of the doped semiconductor layer 104b is, for example, doped silicon or doped polysilicon etc. Similarly, the doped semiconductor layer 104b and a gate layer of a transistor are fabricated in a same manufacturing process. That is, while patterning a gate of a MOS transistor, the doped semiconductor layer 104b (second electrode) of a capacitor is defined. Therefore, no other additional steps are required, when a capacitor of the present invention is fabricated. The capacitor dielectric layer 106 is, for example, disposed on the doped semiconductor layer 104b (second electrode), and exposes a portion of the doped semiconductor layer 104b (second electrode). The conductive plug 112 (first electrode) is, for example, disposed on the capacitor dielectric layer 106.

The metal silicide layer 108 is, for example, disposed on the doped semiconductor layer 104b (second electrode) exposed from the capacitor dielectric layer 106 and the etch stop layer 110 is disposed on the capacitor dielectric layer 106 and the doped semiconductor layer 104b (second electrode). The interlayer insulating layer 116 is, for example, disposed on the etch stop layer 110. The shape of the conductive plug 112 (first electrode) is, for example, square, rectangle or other suitable shapes such as round or oval. The number of the conductive plug 112 (first electrode) is not only limited to one, and can also be two or more. Additionally, the insulating spacers 118 are, for example, disposed on sidewalls of the doped semiconductor layer 104a. The material of the insulating spacers 118 is, for example, silicon oxide or silicon nitride etc.

In the semiconductor capacitors in FIGS. 2C to 2D, a resistive protection oxide layer or a self-aligned silicide block layer is served as the capacitor dielectric layer 106, and the conductive plug 112 and the doped semiconductor layer 104a (104b) are served as electrodes of a capacitor. The doped semiconductor layer 104a (104b) is fabricated together with a gate of a transistor in a same manufacturing process. The conductive plug 112 is fabricated together with plugs connected to a gate, source/drain region of a transistor in a same manufacturing process. Therefore, a capacitor is fabricated without varying the manufacturing process of common complementary metal oxide-semiconductor. No additional space is required, and the integration of semiconductor devices is elevated.

Next, a one time programmable memory cell of the present invention will be described. The one time programmable memory cell of the present invention includes the aforementioned semiconductor capacitor.

FIG. 3A is a schematic view of a one time programmable memory cell according to a preferred embodiment of the present invention. FIGS. 3B and 3C are schematic circuit diagrams of the one time programmable memory cell according to the present invention.

Please refer to FIG. 3A, the one time programmable memory cell of the present invention is disposed on a substrate 200. The one time programmable memory cell includes a gate dielectric layer 202, a gate 204, a source region 206, a drain region 208, spacers 210, a capacitor dielectric layer 212, a conductive plug 214 and an etch stop layer 216. The one time programmable memory cell of the present invention can be an N type channel memory cell, and can also be a P type channel memory cell.

The gate 204 is, for example, disposed on the substrate 200. The material of the gate 204 includes conductive material, such as metal or doped polysilicon. The gate dielectric layer 202 is, for example, disposed between the gate 204 and the substrate 200. The martial of the gate dielectric layer 202 includes silicon oxide or high-k material having dielectric constant higher than 4. The gate dielectric layer 202 can also be formed from one or more dielectric material layers. For example, the gate dielectric layer 202 is formed from a single silicon oxide layer or from a silicon oxide layer and a high-k material layer.

The spacers 210 are, for example, disposed on sidewalls of the gate 204. The material of the spacers 210 is, for example, silicon oxide or silicon nitride. The source region 206 and the drain region 208 are disposed in the substrate 200 on the sides of the gate 204, respectively.

The capacitor dielectric layer 212 is, for example, disposed on the source region 206, and the capacitor dielectric layer 212 is a resistive protection oxide layer or a self-aligned silicide block layer. The material of the capacitor dielectric layer 212 is, for example, silicon oxide or silicon nitride.

The conductive plug 214 is, for example, disposed on the capacitor dielectric layer 212. The conductive plug 214 is served as a first electrode of a capacitor, the source region 206 is served as a second electrode of the capacitor. The material of the conductive plug 214 includes conductive materials such as metal or doped polysilicon, etc. The etch stop layer 216 is, for example, disposed on the capacitor dielectric layer 212. The material of the etch stop layer 216 is, for example, silicon nitride or silicon oxynitride.

In the one time programmable memory cell according to the present invention, a resistive protection oxide layer or a self-aligned silicide block layer is served as the capacitor dielectric layer 212. The conductive plug 214 and the doped region 104 are served as electrodes of a capacitor. Therefore, a capacitor is fabricated without varying the manufacturing process of common complementary metal oxide-semiconductor. No additional space is required, and the integration of the semiconductor devices is elevated.

Please refer to the schematic circuit diagram in FIG. 3B, the one time programmable memory cell is formed from a transistor T and a capacitor C. A dielectric layer of the capacitor is damaged by controlling voltages applied on a gate G, a drain D, a source S and a substrate B of the transistor, to program the one time programmable memory cell of the present invention. When the dielectric layer of the capacitor has been damaged (breakdown), the capacitor C in transformed into a resistor R. Therefore, digital data “0” or “1” is recorded by detecting whether the dielectric layer of the capacitor has been damaged (breakdown) or not. Moreover, the dielectric layer cannot be recovered if damaged, so the memory cell can only be programmed one time.

Next, an operating method according to the present invention will be illustrated. FIGS. 4A to 4B are schematic views illustrating programming operation of an N type memory cell.

Please refer to FIG. 4A, the memory cell includes a P type substrate (or P type well), a gate, a gate dielectric layer, an N type source region and an N type drain region, a capacitor dielectric layer and a conductive plug.

When the memory cell is programmed, a voltage V1 is applied on the conductive plug, a voltage V2 is applied on the P type substrate (or P type well) and a voltage V3 is applied on the N type drain region, a voltage V4 is applied on the gate. The voltage V4 is such set to open a channel under the gate, the voltage V1 and the voltage V2, V3 are such set to make capacitor dielectric layer breakdown. For example, the voltage V1 is about 4 to 6 Volts, the voltage V2 is about 0 Volt, the voltage V3 is about 0 Volt, the voltage V4 is about 1 to 2 Volts.

Please refer to FIG. 4B, a memory cell includes a P type substrate, a deep N type well DNW, a P type well PW, a gate, an N type source region and an N type drain region, a capacitor dielectric layer and a conductive plug.

When the memory cell is programmed, the P type substrate and the DNW region are grounding, a voltage V5 is applied on the conductive plug, a voltage V6 is applied on the gate, a voltage V7 is applied on the N type drain region, a voltage V8 is applied on the P type well PW. The voltages V5, V7 and the voltage V8 are set to make the capacitor dielectric layer breakdown. For example, the voltage V5 is about 3.3 Volts, the voltage V6 is about 0 Volt, the voltage V7 is about −3.3 Volts, and the voltage V8 is about −3.3 Volts.

FIGS. 5A to 5B are schematic views illustrating programming operation of a P type memory cell.

Please refer to FIG. 5A, a memory cell includes an N type substrate (or N type well), a gate, a gate dielectric layer, a P type source region and a P type drain region, a capacitor dielectric layer and a conductive plug.

When the memory cell is programmed, a voltage V9 is applied on the conductive plug, a voltage V10 is applied on the N type substrate (or N type well) and a voltage V11 is applied on the P type drain region, a voltage V12 is applied on the gate. The voltages V9, V10 and V11 are set to make the capacitor dielectric layer breakdown. The voltage V12 is set to open a channel under the gate. For example, the voltage V9 is about −3.3 Volts, the voltage V10 is about 3.3 Volts, the voltage V11 is about 3.3 Volts, the voltage V12 is about 0 Volt.

Please refer to FIG. 5B, a memory cell includes an N type substrate (or N type well), a gate, a gate dielectric layer, a P type source region and P type drain region, a capacitor dielectric layer and a conductive plug.

When the memory cell is programmed, a voltage V13 is applied on the conductive plug, a voltage V14 is applied on the N type substrate (or N type well) and a voltage V15 is applied on the gate, a voltage V16 is applied on the P type drain region. The voltages V13, V14 and V16 are such set to make the capacitor dielectric layer breakdown. For example, the voltage V13 is about 0 Volt, the voltage V14 is about 4 to 6 Volts, the voltage V15 is about 3.3 Volts, and the voltage V16 is about 4 to 6 Volts.

In the operating method of one time programmable memory cells of the present invention, a dielectric layer of the capacitor is damaged by controlling voltages applied on a gate, a drain, a source and a substrate of the transistor, to program the one time programmable e memory cell of the present invention. Moreover, digital information “0” or “1” is recorded by detecting whether the dielectric layer of the capacitor is damaged or not. The contact area of conductive plug with the capacitor dielectric layer is relatively small, which can result in increased current destiny where the conductive plug contacts with the capacitor dielectric layer when the one time programmable memory cell of the present invention is programmed. This can readily make the capacitor dielectric layer breakdown and the operating voltages are reduced.

Next, a fabricating method of a one time programmable memory cells according to the present invention will be described.

FIGS. 6A to 6E are cross-sectional views illustrating a manufacturing process of a one programmable memory cell according to one preferred embodiment of the present invention.

Please refer to FIG. 6A, at first, a substrate 300 is provided. The substrate 300 includes a silicon substrate, such as an N type silicon substrate or a P type silicon substrate. Of course, the substrate 300 can also be silicon on insulator substrate.

The substrate 300 is provided with, for example, transistors 302 and 304. The transistors 302 and 304 are connected in series, for example.

The transistor 302 is formed with a capacitor dielectric layer 306, a gate 308, spacers 310 and source/drain regions 312, 314.

A capacitor dielectric layer 306 is positioned between the gate 308 and the substrate 300. The material of the capacitor dielectric layer includes a silicon oxide or high-k material having dielectric constant higher than 4. The capacitor dielectric layer 306 is formed from one or more dielectric material layers. The spacers 310 are, for example, disposed on sidewalls of the gate 308. The material of the spacers 310 is, for example, silicon oxide or silicon nitride. For example, the source/drain regions 312, 314 are disposed in the substrate on the sides of the gate 308. The material of the gate 308 is, for example, doped polysilicon.

For example, the transistor 304 is formed from the gate dielectric layer 316, the gate 318, the spacers 320 and the source/drain regions 314, 322.

A gate dielectric layer 316 is disposed between the gate 318 and the substrate 300. The material of the gate dielectric layer 316 includes silicon oxide or high-k material having dielectric constant higher than 4. The gate dielectric layer 316 is formed from one or more dielectric material layers. The spacers 320 are, for example, disposed on sidewalls of the gate 318. The material of the spacers 320 is, for example, silicon, oxide or silicon nitride. For example, the source/drain regions 314, 322 are disposed in the substrate 300 on the sidewalls of the gate 318. The material of the gate 120 is, for example, doped polysilicon. The transistor 302 and the transistor 304 share the source/drain region 314.

Forming the transistor 302 and the transistor 304 on the substrate 300 is achieved by using common complementary metal oxide-semiconductor manufacturing process. Thus it will not be described in detail.

Please refer to FIG. 6B, a dielectric layer 324 is formed on the substrate 300. The dielectric layer 324 is served as a resistive protection oxide layer or a self-aligned silicide block layer. The material of the dielectric layer 324 is, for example, silicon oxide or silicon nitride. Then, a mask layer 326 is formed on the substrate 300. The mask layer 326 covers the dielectric layer 324 of the source/drain region 314. The material of the mask layer 326 is, for example, photoresist material. For example, the mask layer 326 is formed by following steps. At first, a layer of photoresist material is applied on the substrate by spinning process. The photolithography process is performed and the mask layer 326 is formed. Of course, the material of the mask layer 326 can also be other materials.

Please refer to FIG. 6C, the mask layer 326 is served as a mask, and a portion of the dielectric layer 324 are removed, only leaving the dielectric layer 324a on the source/drain region 314. The process of removing the dielectric layer 324 includes wet-etching or dry-etching. The wet-etching can use hydrofluoric acid as etchant. Then, the mask layer 326 is removed.

Subsequently, a metal silicide layer 328 is formed on the gate 308, the gate 318, the source/drain region 312 and the source/drain region 322. The material of the metal silicide layer 328 includes metal silicide of refractory metal, for example one silicide of nickel, cobalt, titanium, copper, molybdenum, tantalum, tungsten, erbium, zirconium, platinum and alloys thereof. The fabricating method of the metal silicide layer 328 is, for example self-aligning metal silicide process. The process includes following steps: at first a metal layer (not shown) is formed on the substrate 300. The material of the metal layer includes refractory metal, such as one of nickel, cobalt, titanium, copper, molybdenum, tantalum, tungsten, erbium, zirconium, platinum and alloys thereof. The metal layer is formed by evaporation, sputtering, electric plating, chemical vapor deposition (CVD) or physical vapor deposition. Then, an annealing process is performed, so that silicon of the gates 308 and 318, the source/drain regions 312 and 322 reacts with the metal layer, to form a metal silicide layer 328. Then, unreacted metal layer is removed. Removing process of the unreacted metal layer is, for example, performing a selective wet etch process. The unreacted metal layer is removed by utilizing mixed solution of hydrochloric acid/hydrogen peroxide or mixed solution of sulfuric acid/hydrogen peroxide as etchant, only leaving the metal silicide layer 328 on surfaces of the gates 308 and 318, the source/drain regions 312 and 322.

Please refer to FIG. 6D, an etch stop layer 330 is formed on the substrate 300. The etch stop layer 330 is disposed on and entirely covers the transistors 302 and 304. The material of the etch stop layer 330 is, for example, silicon nitride, which is formed by chemical vapor disposition process. Then, an interlayer insulating layer 332 is formed on the etch stop layer 330. The material of the interlayer insulating layer 332 is, for example, phosphorosilicate glass or borophosphorosilicate glass.

Please refer to FIG. 6E, conductive plugs 334, 336 and 338 are formed in the insulating layers 332. The conductive plug 334 and the conductive plug 338 are electrically connected to the source/drain region 312 and the source/drain region 322. The conductive plug 336 extends through the etch stop layer 330 and is connected with a dielectric layer 324a. The conductive plug 336, the dielectric layer 324a and the source/drain region 314 form a capacitor. The conductive plugs 334, 336, 338 are formed by the steps as following: at first, the insulating layer 332 is patterned to form plug openings. When a portion of the insulating layer 332 is removed to form the plug openings, etching will stop at the etch stop layer 330. Then, the etch stop layer 330 exposed by the plug openings is removed to expose the metal silicide layer 328 on the source/drain regions 312 and 322, and the dielectric layer 324a on the source/drain region 314. Conductive material is filled in the plug openings to form the conductive plugs.

In the fabricating method of a one time programmable memory cell according to the present invention, a capacitor is directly formed from the conductive plug 336, the dielectric layer 324a and the source/drain region 314, so the capacitor is fabricated without varying common general complementary metal oxide-semiconductor manufacturing process. The capacitor is directly disposed on the source/drain region 314. No additional space is required, and the integration of semiconductor devices is elevated.

As mentioned above, in the semiconductor capacitor, one time programmable memory cell and fabricating method and operating method thereof according to the present invention, a resistive protection oxide layer or a self-aligned silicide block layer is served as a capacitor dielectric layer, and a conductive plug and a doped region are served as electrodes of the capacitor. Wherein the doped region is a source/drain region of a transistor or is fabricated together with a source/drain region of a transistor in a same manufacturing process. The conductive plug is fabricated together with plugs connected to a gate, a source/drain region of a transistor in a same manufacturing process. Therefore, the capacitor is directly disposed on the source/drain region 314. No additional space is required, and the integration of semiconductor devices is elevated.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.

Claims

1. A semiconductor capacitor, comprising: a capacitor dielectric layer which is a resistive protection oxide layer or a self-aligned silicide block layer; anda first electrode and a second electrode disposed at opposing sides of the capacitor dielectric layer.

2. The semiconductor capacitor according to claim 1, wherein the first electrode is a conductive plug.

3. The semiconductor capacitor according to claim 2, further comprising an etch stop layer disposed on the capacitor dielectric layer, wherein the first electrode extends through the etch stop layer and contacts with the capacitor dielectric layer.

4. The semiconductor capacitor according to claim 1, wherein the semiconductor capacitor is disposed on a substrate; the second electrode is a doped region disposed in the substrate;the capacitor dielectric layer is disposed on the doped region, and exposes a portion of the doped region; andthe first electrode is disposed on the capacitor dielectric layer.

5. The semiconductor capacitor according to claim 4, further comprising a metal silicide layer disposed on the doped region which is exposed on the capacitor dielectric layer; and a second conductive plug electrically connected to the metal silicide layer.

6. The semiconductor capacitor according to claim 4, wherein the first electrode is formed from one or more first conductive plugs and the shape of the first conductive plug comprises square, rectangle, round or other shapes.

7. The semiconductor capacitor according to claim 4, wherein the substrate comprises a silicon substrate or a silicon on insulator substrate; and the doped region is disposed in a silicon layer of the silicon on insulator substrate.

8. The semiconductor capacitor according to claim 1, wherein the semiconductor capacitor is disposed on an isolation structure of a substrate; the second electrode is a doped polysilicon layer disposed on the substrate;the capacitor dielectric layer is disposed on the doped polysilicon layer and exposes a portion of the doped polysilicon layer; andthe first electrode is disposed on the capacitor dielectric layer.

9. The semiconductor capacitor according to the claim 8, further comprising a metal silicide layer disposed on the doped polysilicon layer which is exposed on the capacitor dielectric layer; and a second conductive plug electrically connected to the metal silicide layer.

10. The semiconductor capacitor according to claim 1, wherein the semiconductor capacitor is disposed on an insulating substrate; the second electrode is a doped semiconductor layer disposed on the insulating substrate;the capacitor dielectric layer is disposed on the doped semiconductor layer, and exposes a portion of the doped semiconductor layer; andthe first electrode is disposed on the capacitor dielectric layer.

11. The semiconductor capacitor according to the claim 10, wherein the insulating substrate is a glass substrate.

12. A one time programmable memory cell, comprising: a gate dielectric layer disposed on a substrate;a gate disposed on the gate dielectric layer;a source region and a drain region disposed in the substrate at the sides of the gate, respectively; anda capacitor dielectric layer disposed on the source region, and the capacitor dielectric layer being a resistive protection oxide layer or a self-aligned silicide block layer; anda conductive plug disposed on the capacitor dielectric layer, wherein the conductive plug is served as a first electrode of a capacitor, the source region is served as a second electrode of the capacitor.

13. An operating method of a one time programmable memory cell, the one time programmable memory cell comprising a substrate of a first conductive type, a gate dielectric layer disposed on the substrate of the first conductive type, a gate disposed on the gate dielectric layer, a source region of a second conductive type and a drain region of the second conductive type disposed in the substrate of the first conductive type at the sides of the gate; a capacitor dielectric layer disposed on the source region of the second conductive type and a conductive plug disposed on the capacitor dielectric layer, wherein the capacitor dielectric layer is a resistive protection oxide layer or a self-aligned silicide block layer, the method comprises: programming the memory cell by making the capacitor dielectric layer breakdown.

14. The operating method of a one time programmable memory cell according to claim 13, wherein the first conductive type is P type, the second conductive type is N type, the step of programming the memory cell comprises: applying a first voltage on the conductive plug, applying a second voltage on the substrate of the first conductive type; applying a third voltage on the drain region of the second conductive type, applying a fourth voltage on the gate, wherein the first voltage, the second voltage and the third voltage are set to make the capacitor dielectric layer breakdown, the fourth voltage is set to open a channel under the gate.

15. The operating method of a one time programmable memory cell according to claim 13, wherein the substrate of the first conductive type comprises a well of a second conductive type and a well of the first conductive type being disposed on the well of the second conductive type, the first conductive type is P type, the second conductive type is N type, the step of programming the memory cell comprises: grounding the substrate of the first conductive type and the well of the second conductive type, applying a fifth voltage on the conductive plug, applying a sixth voltage on the gate, applying a seventh voltage on the drain region of the second conductive type, applying an eighth voltage on the well of the first conductive type, wherein the fifth, the seventh voltage and the eighth voltage are set to make the capacitor dielectric layer breakdown.

16. The operating method of a one time programmable memory cell according to claim 15, wherein the fifth voltage is about 3.3 Volts, the sixth voltage is about 0 Volt, the seventh voltage is about −3.3 Volts, the eighth voltage is about −3.3 Volts.

17. The operating method of a one time programmable memory cell according to claim 13, wherein the first conductive type is N type, the second conductive type is P type, the step of programming the memory cell comprises: applying a ninth voltage on the conductive plug, applying a tenth voltage on the substrate of the first conductive type and applying an eleventh voltage on the drain region of the second conductive type, applying a twelfth voltage on the gate, wherein the ninth, the tenth voltage and the eleventh voltage are set to make the capacitor dielectric layer breakdown, and the twelfth voltage is set to open a channel under the gate.

18. The operating method of a one time programmable memory cell according to claim 17, wherein the ninth voltage is about −3.3 Volts, the tenth voltage is about 3.3 Volts, the eleventh voltage is about 3.3 Volts, the twelfth voltage is about 0 Volt.

19. The operating method of a one time programmable memory cell according to claim 13, wherein the first conductive type is N type; the second conductive type is P type, the step of programming the memory cell comprises: applying a thirteenth voltage on the conductive plug, applying a fourteenth voltage on the substrate of the first conductive type, applying a fifteenth voltage on the gate, applying a sixteenth voltage on the drain region of the second conductive type, wherein the thirteenth voltage, the fourteenth voltage, and the sixteenth voltage are set to make the capacitor dielectric layer breakdown.

20. The operating method of a one time programmable memory cell according to claim 19, wherein the thirteenth voltage is about 0 Volt, the fourteenth voltage is about 4 to 6 Volts, the fifteenth voltage is about 3.3 Volts, the sixteenth voltage is about 4 to 6 Volts.

21. A fabricating method of a one time programmable memory cell comprising: providing a substrate provided with a transistor thereon, the transistor comprising a gate, a gate dielectric layer, a first source/drain region and a second source/drain region;forming a dielectric layer on the first source/drain region, that is a resistive protection oxide layer or a self-aligned silicide block layer;forming a metal silicide layer on the gate and the second source/drain region; andforming a first conductive plug on the dielectric layer, wherein the first conductive plug, the dielectric layer and the first source/drain region form a capacitor.

22. The fabricating method of a one time programmable memory cell according to claim 21, wherein the step of forming the dielectric layer on the first source/drain region comprises: forming the dielectric layer on a substrate;forming a mask layer covering the first source/drain region on the substrate;removing a portion of the dielectric layer by using the mask layer as mask; andremoving the mask layer.

23. The fabricating method of a one time programmable memory cell according to claim 22, further comprising forming an etch stop layer and an interlayer insulating layer on the substrate before the step of forming the first conductive plug on the dielectric layer.

24. The fabricating method of a one time programmable memory cell according to claim 22, wherein the process of forming the metal silicide layer on the gate and the second source/drain region comprises a self-aligning metal silicide manufacturing process.