Patent Application
20160021437
This application claims the benefit of the German Utility Model Application No. 20-2014-103-217.7, filed Jul. 13, 2014, and entitled “Integrierter Halbleiterbaustein, der mindestens drei unabhängige integrierte Systemkomponenten besitzt”, which is hereby incorporated by reference in its entirety.
1. Field of the Disclosure
The present application relates generally to computing devices and systems composed of semiconductor devices. More particularly, the present invention pertains basic semiconductor devices, such as multi-core microprocessors, massively parallel processor arrays, multiprocessor systems on a chip, multi-core and many-core systems on a chip, and multi-processor systems in a package, and also multi-processor computer systems, specifically parallel computers, as well as to related electromagnetical wireless intra-chip or on-chip interconnects and networks, and inter-chip or off-chip networks, as well as combinations of such electromagnetical wired and wireless interconnects and networks connecting the independent semiconductor components of such computing systems.
2. Description of the Related Art
The present application relates generally to computing devices and systems composed of semiconductor devices. More particularly, the present invention pertains basic semiconductor devices, such as multi-core microprocessors, massively parallel processor arrays, multiprocessor systems on a chip, multi-core and many-core systems on a chip, and multi-processor systems in a package, and also multi-processor computer systems, specifically parallel computers, as well as to related electromagnetical wireless intra-chip or on-chip interconnects and networks, and inter-chip or off-chip networks, as well as combinations of such electromagnetical wired and wireless interconnects and networks connecting the independent semiconductor components of such computing systems.
One approach to solve the interconnect bottleneck problem on the microscale is to replace the electrical or metal respectively wired interconnects and electrical networks on a chip with optical (wired) interconnects and optical networks on a chip.
Various system designs with optical interconnects are proposed for different reasons including for example (a) a hybrid network for multi-processor systems on chip comprising a mesh electrical network and an optical ring network to transfer short control messages for reducing the control delay in cache coherence protocols, (b) an optical ring waveguide to replace global pipelined electrical interconnects providing more uniform latency and throughput compared with the mesh network, (c) a hierarchical optical rings, where local rings are used for intra-node communication and global rings are to connect the nodes, (d) an optical torus network with related network protocols and floorplanning, (e) an optical ring network on a chip for both two-dimensional and three-dimensional system architectures, (f) physical layouts of different wavelength-routed on-chip optical networks, and (g) an architecture which uses optical interconnects for both intercore communication and off-stack communication to memory with the cores integrated as clusters, which are fully interconnected with a photonic crossbar, and distributed optical token-based arbitration scheme is proposed for channel allocation.
But because solving the interconnect bottleneck problem with optical interconnects does neither solve the fundamental bandwidth density challenge for the in-plane waveguided optical interconnect approach nor the wiring problem in general, an approach to solve the optical interconnect bottleneck problem and the wiring problem is to replace these wired interconnects and networks on the microscale as well as the interconnects and networks on the macroscale with electromagnetical wireless interconnects and networks, such as (free space) optical wireless interconnects and networks.
Various system designs with free-space optical (wireless) interconnects are proposed for different reasons including for example (h) an optical network on a chip based on free-space optical interconnects to reduce power consumption, (i) an intra-chip free-space optical interconnect with three-dimensional system architecture, and (j) an on-chip free-space optical network with wavelength switching. A single light beam is analogous to a single wire and similarly, an array of vertical cavity surface emitting lasers (VCSELs) can form essentially a multi-bit bus, which is called a lane sometimes. An interesting feature of using free-space optics is that signaling is not confined to fixed, prearranged waveguides and the optical path can change relatively easily.
A specific representative example of the direction of the technological development in this field is the approach to construct three-dimensional integrated chip stacks 100 as shown in
In one particular system design, digital data streams modulate an array of lasers. Each modulated light beam emitted by a laser can be collimated by a microlens, guided by a series of micro-mirrors, focused by another micro-lens, and then detected by a photodetector. The received electrical signals are finally converted to digital data. In another system design as shown in
By utilizing the beamsteering capability 150 of an optical phase array (OPA) of lasers, the number of lasers and photodetectors in each node can be constant, providing further flexibility and scalability.
In general, such electro-optical SiPs increase the speed of communication, because the optical links are running at multiples of the core clock speed, and reduce the latency and power consumption of the global signaling through free-space optical interconnect, while permitting the microprocessors to be implemented using standard CMOS technologies.
Another approach to solve the wiring problem on the macroscale and to overcome the barriers of power consumption, memory and storage bandwidth, and also reliability and resiliency, specifically in relation with large computing systems, such as data centers and supercomputers or high performance computing systems for example, is to depart from the arrangement of server racks in rows in favour of a circular arrangement.
As part of the initiative “Oak Ridge Leadership Computing Facility” (OCLF) of the U.S. Department of Energy a national laboratory designed a high performance computing system 200 called OCLF-5 shown in
As part of the research project “On the Feasibility of Completely Wireless Datacenters”, a datacenter with a novel rack design and a resulting network topology inspired by Cayley graphs is proposed that provide a dense interconnect and the opportunity to solve both the interconnect problem and the wiring problem on the macroscale. In this design even the computing nodes are circularly arranged within the server racks, and the wired network or interconnect is substituted with a wireless network by installing 60 GHz radio frequency transceiver devices and Y-switch devices into each computing node.
The exploration of the resulting design space shows that wireless datacenters and also other such large computing systems built with this methodology can potentially attain higher aggregate bandwidth, lower latency, and substantially higher fault tolerance than a conventional wired datacenter and also improve ease of construction and maintenance.
Electromagnetical (wireless) interconnects and networks, specifically optical interconnects and networks, have fundamental advantages compared to electrical and optical wired interconnects and networks, particularly in power consumption respectively energy efficiency, delay respectively latency, potential bandwidth, and fault tolerance respectively reliability and resiliency, and in addition offer a new set of opportunities. But while signaling issues have received a lot of attention, networking issues in the general-purpose domain remain under-explored. Furthermore, intra-chip or on-chip interconnects and networks pose different constraints and challenges from inter-chip or off-chip interconnects and networks. Therefore architecting intra-chip or on-chip interconnects and networks for future microprocessors and computers as well as architecting inter-chip or off-chip interconnects and networks for future single computer systems including single computing nodes of large computing system clusters require novel solutions and deserves more attention, as it is also the case with computing systems based on integrated semiconductor devices.
Observing the technological development in the area of multi-core and many-core processing systems, it becomes obvious that also the wiring problem will affect the computing systems on the microscale in the same way as it affected the computing systems on the macroscale already. However, an integration of the solutions for the interconnect bottleneck problem applied on the microscale and the wiring problem applied on the macroscale as discussed above is missing. Furthermore, no foundationally new possibilities are given.
Accordingly, the invention is a continuation of the past technological development on the microscale and the macroscale of computing devices and computing systems. As another approach to solve both the interconnect bottleneck problem and the wiring problem simultaneously on the microscale of integrated semiconductor devices and on the macroscale of single computing systems consisting of integrated semiconductor devices, such as for example a high performance computing system with a wireless interconnect on a chip or in a package, and a high performance computing system on a base board or a motherboard, the single integrated semiconductor devices of an integrated semiconductor component system or the single integrated semiconductor component systems are arranged with the same distance from a center point in a geometric space.
Related wireless interconnects and networks comprise at least one transmitter device and at least one receiver device, which are configured to work on one of the (a) radio wave band, (b) microwave band, (c) infrared radiation band, (d) light radiation band, (e) ultraviolet radiation band, or (f) roentgen radiation band. Maser and laser devices, but also projector devices are used as transmitter devices and various types of photodetectors are uses as receiver devices.
The ways of physical connection reflects the ways of network communication unicast (one-to-one), multicast (one-to-unique many or unique many-to-unique many), broadcasting (one-to-many), anycast (one-to-nearest), and all-to-all.
Furthermore, by using multiple transmitters and multiple receivers at a network node multipath propagation can be exploited, such as multiple-input and multiple-output (MIMO), including (a) single user MIMO or multi-antenna MIMO, (b) multi-user MIMO (MU-MIMO), (c) partial full multi-user MIMO or multi-user and multi-antenna MIMO, (d) full multi-user MIMO, cooperative MIMO (CO-MIMO) or network MIMO (Net-MIMO), and (e) cognitive MIMO, as well as MIMO enhancements.
To exploit the many possibilities it is highly advantageous to let the integrated semiconductor component system handle the communication management as well by using for example programmable digital radio, software-defined radio (SDR) and advanced variants, such as cognitive radio for example that are based on intelligent techniques and own functionalities.
But the intentions and directions behind the disclosed invention are many-folded going beyond common computing systems.
Several free-space optical interconnect system architectures provide all-to-all direct communication links between processor cores, regardless of their topological distance. In contrast, the independent integrated system components of the disclosed computing system are arranged with the same distance from a center point with respect to a geometric space, such as the Euclidian space, or described in other words they are arranged on a square or a circle in a two-dimensional plane or in on a cube, a cylinder, or a sphere in a three-dimensional space for example.
By directly using a specific topology the knowledge about the exact positions of system components are implicitly given by the chosen topology within tolerance of manufacturing, which can be used for further optimizations of the integrated semiconductor component system by incorporating the knowledge about the wave-lengths and run-lengths of the communication path and carrier into the working of the communicating components and also of the processing components.
In the case that an arrangement respectively a topology and the related positions respectively distances and angles are not exactly known in general, due to tolerances by the production process in particular, or/and can be moved or changed, then methods for calibrating the device can be applied, for example by sending a test signal.
The disclosed invention also comprises combinations of optical wired interconnects and networks with free-space electromagnetical wireless interconnects and networks, such as the combination of optical wired interconnects and networks to free-space optical wireless interconnects and networks, and means therefore.
The different interconnects and networks can also be used for the configuring of the senders and receivers of the integrated semiconductor component system, the time synchronization system (e.g., using optical clock distribution), so that no clock recovery circuit is needed, for sending a test signal back to the sender, and for providing other support.
Some embodiments of the disclosed system also provide a connection with external device, including mobile devices including smartphone, tablet computer, laptops, and connected vehicles, head-mounted displays, computer systems for example, by optical wired and electromagnetical wireless communication interfaces.
A further aspect behind the invention is to construct a high performance computing system as a model of a quantum computer and a real quantum computer. By changing from Euclidean space to Hilbert space, which generalizes the notion of Euclidean space, and applying the feature of multi-casting the quantum computer model should be able to simulate entanglement.
The invention may be implemented in numerous ways. In this conjunction, all the components or electronic units, which form the various parts of said integrated semiconductor component system and which are known to those skilled in the art in the field of computer engineering, will not be described in detail. Only said components necessary to the elaboration of preferred embodiments of an integrated semiconductor component system according to the invention will be described.
Other systems, methods, features, advantages, objects, and further areas of applicability together with a more complete understanding of the disclosure will be, or will become, apparent and appreciated to one with skill in the art upon examination of the following figures and detailed description, or may be learned by practice of the present invention. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure, and be protected by the following claims. Nothing in this section should be taken as a limitation on those claims. Further aspects and advantages are discussed below in conjunction with the embodiments. It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed, but are not intended to limit the scope of the disclosure.
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated herein and constitute a part of this application, illustrate embodiment(s) of the disclosure and together with the description serve to explain the principle of the disclosure. In the drawings:
By three-dimensional chip integration the single component layers 331 to 334 and 341 to 344 are horizontally connected with each other by the through-silicon via layers 302, 302, and 304, and superimposed on top of a package substrate by a flip-chip bonding layer 301 for example. The semiconductor component stacks 330, 340 are vertically connected with each other by the chip integration layer 305.
In this example, the stack of processors 330 also comprises transmitter modules 351 to 354 and receiver modules 361 to 364, which are directly integrated into the single integrated semiconductor component layers 331 to 334. In some variants of the embodiment the transmitter and receiver modules can be radio frequency transmitter devices and antennas, microwave transmitter and receiver modules, optical transmitter and receiver modules respectively optical transceiver devices. In the case of optical transmitter and receiver devices, and transceiver devices the component layers of the stack of processors 330 can also have micro-mirrors 371 to 374.
Although only the transmitter modules 351 to 354 and receiver modules 361 to 364 are illustrated in this example, it should be understood that within the scope of the various embodiments there can be additional or alternative transmitter and receiver components and devices of the same or a different type, such as transceiver devices working in same ranges of the electromagnetical spectrum.
By three-dimensional chip integration the single component layers 431 to 434 are horizontally connected with each other by the through-silicon via layers 402, 403, and 404, and the single component layers 441 to 444 are vertically connected with each other by the through-silicon via layers 408, 409, and 410. The component layers 431 to 434, 441 to 444, and 450 are superimposed on top of a package substrate by a flip-chip bonding layer 401 for example. The semiconductor component stacks 430, 440 are vertically connected with each other by the chip integration layer 407, the semiconductor component stack 430 and the optical interconnect stack 490 are vertically connected with each other by the chip integration layer 406, and the semiconductor layer 450 and the optical interconnect stack 490 are vertically connected with each other by the chip integration layer 405.
In this example, the semiconductor layer 440 also comprises transmitter modules 441 to 448 and a photo detector 451 configured as a receiver device, which are directly integrated into the single semiconductor layer 440. In the case of optical transmitter and receiver devices the semiconductor layer 440 can also have micro-mirrors 470, 471.
Although only the photo detector 451 is illustrated in this example, it should be understood that within the scope of the various embodiments there can be additional or alternative photo detector components and devices of the same or a different type, such as a grid of photo diodes, a charged-coupled device, or an active pixel sensor device, such as a CMOS imager device.
The numbering of the single integrated semiconductor components on CMOS substrate layers 421 to 424 and the single through-silicon via layers 402, 403, and 404 are not numbered in the
In this example, the integrated semiconductor component devices 510 to 580 also communicate through a free-space optical wireless interconnect that provides an all-to-all communication. As it is illustrated by the dotted arrows 501, the semiconductor component device 560 can directly sent data to and receive data from the semiconductor component devices 510, 520, 530, and 580, indirectly sent data to and receive data from the semiconductor component device 540 over one or more micro-mirrors of the semiconductor component device 510, and indirectly sent data to and receive data from the semiconductor component devices 550 and 570 over at least two micro-mirrors of semiconductor component devices 530 and 510.
In modifications of the embodiment shown in
In this example, the package substrate 601 has a hole 602 at the area of the free-space optical wireless interconnect, so that cylindrical stacks of the integrated semiconductor component system 600, as shown in
The free-space communication functions in the same way as described in relation with the third embodiment illustrated
A single socket means 820 comprises a socket with a slot 802 mounted on the circuit board 801 and an optical switching box device 851 with a transceiver device 831 of a free-space electromagnetical interconnect or network 830 and a connection to a waveguide 891 of an optical wired interconnect or network 890. The slot 802 and the key area 803 are shaped in a form-locking way, so that the integrated semiconductor component system 800 can be plugged into the socket 820 and provided with electric power and connectivity to the communication means of the circuit board 840.
The circuit board 840 comprises the free-space communication area 830, a ring with optical switching box devices 850, and the optical wired interconnect or network ring 890. The circuit board 840 is shaped as a ring.
An optical switching box device 851 connects the optical waveguide 891 of the optical wired interconnect or network ring 890 with the transceiver device 831 of the electromagnetical wireless interconnect or network 830. In this example, the optical switching box device 851 includes at least one Y-switch device that on the one side is connected with the transceiver device 831 and on the other side with one or more microresonator devices which are connected with the optical waveguide 891. The Y-switch device and the microresonator device are not shown in
In modifications of the embodiment shown in
In other modifications, the embedded system 810 could also be a common embedded computing system without any optical wired or wireless interconnect or network or/and also have a cooling system.
The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereunto by those skilled in the art without departing from the broader spirit and scope of the invention as set forth in the claims. In other words, although embodiments have been described with reference to a number of illustrative embodiments thereof, this disclosure is not limited to those. Accordingly, in various embodiments of the invention the various embodiments of the integrated semiconductor component system discussed and suggested in
| Number | Date | Country | Kind |
|---|---|---|---|
| 20-2014-103-217.7 | Jul 2014 | DE | national |
