Semiconductor device and a method of manufacturing the same

Abstract

A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of a non-volatile memory cell which the present inventors have studied;

FIG. 2 is an enlarged sectional view of a principal portion of the memory cell shown in FIG. 1;

FIG. 3 is a circuit diagram of a memory cell in a semiconductor device having a non-volatile memory according to an embodiment of the present invention;

FIG. 4 is a sectional view of a basic device configuration of the memory cell shown in FIG. 3;

FIG. 5 is an enlarged sectional view of a principal portion of the memory cell shown in FIG. 4;

FIG. 6 is an enlarged sectional view of a principal portion of the memory cell shown in FIG. 4;

FIG. 7 is a graph showing a threshold voltage distribution within a semiconductor chip in a comparative manner between before taking a measure against a disturb defect and after taking the measure;

FIG. 8 is a sectional view of principal portions during manufacture of the semiconductor device having the non-volatile memory embodying the present invention;

FIG. 9 is a sectional view of principal portions during manufacture of the semiconductor device which follows FIG. 8;

FIG. 10 is a sectional view of principal portions during manufacture of the semiconductor device which follows FIG. 9;

FIG. 11 is a sectional view of principal portions during manufacture of the semiconductor device which follows FIG. 10;

FIG. 12 is an enlarged sectional view of a memory region shown in FIG. 11;

FIG. 13 is an enlarged sectional view of a peripheral circuit region shown in FIG. 11;

FIG. 14 is an enlarged sectional view of a resistor region shown in FIG. 11;

FIG. 15 is a sectional view of principal portions during manufacture of the semiconductor device which follows FIG. 11;

FIG. 16 is a sectional view of principal portions during manufacture of the semiconductor device which follows FIG. 15;

FIG. 17 is a sectional view of principal portions during manufacture of the semiconductor device which follows FIG. 16;

FIG. 18 is an enlarged sectional view of a memory region shown in FIG. 17;

FIG. 19 is an enlarged sectional view of a peripheral circuit region shown in FIG. 17;

FIG. 20 is an enlarged sectional view of a resistor region shown in FIG. 17;

FIG. 21 is a sectional view of principal portions during manufacture of the semiconductor device which follows FIG. 17;

FIG. 22 is an enlarged sectional view of a memory region shown in FIG. 21;

FIG. 23 is an enlarged sectional view of a peripheral circuit region shown in FIG. 21;

FIG. 24 is an enlarged sectional view of a resistor region shown in FIG. 21; and

FIG. 25 is a sectional view of principal portions during manufacture of the semiconductor device which follows FIG. 21.

Claims

1. A semiconductor device comprising a plurality of non-volatile memory cells over a main surface of a semiconductor substrate, each of the non-volatile memory cells comprising: an insulating film for charge storage formed over the semiconductor substrate;a first gate electrode formed over the insulating film for charge storage and having first and second side faces, the first and second side faces being positioned on mutually opposite sides along the main surface of the semiconductor substrate;a first insulating film formed over the first side face of the first gate electrode;a second insulating film formed over a side face of the first insulating film;a first semiconductor region formed over the main surface of the semiconductor substrate self-alignmentwise for the first side face of the first gate electrode;a second semiconductor region formed over the main surface of the semiconductor substrate self-alignmentwise for a side face of the first insulating film so as to be electrically coupled to the first semiconductor region; anda first silicide layer formed over the second semiconductor region self-alignmentwise for a side face of the second insulating film,an end portion on the first gate electrode side of the first silicide layer being formed by the second insulating film at a position spaced away from a junction end between the first semiconductor region and the second semiconductor region.

2. A semiconductor device according to claim 1, wherein an active region defined by an isolation region is formed over the main surface of the semiconductor substrate,wherein the isolation region is formed by burying an insulating film for isolation into a trench formed in the main surface of the semiconductor substrate,wherein such a depression as allows a part of the semiconductor substrate present over a side face of the trench to be exposed is formed over an upper surface of the insulating film for isolation in adjacency to the active region, andwherein an insulating film is formed in the depression so as to cover a part of the semiconductor substrate present over the side face of the trench and exposed from the depression.

3. A semiconductor device according to claim 1, wherein each of the non-volatile memory cells further comprises: a gate insulating film formed over the main surface of the semiconductor substrate;a second gate electrode having a third side face and a fourth side face, the third side face being opposed to the second side face of the first gate electrode and provided over the gate insulating film at a position adjacent through the insulating film for charge storage to the second side face of the first gate, the fourth side face being positioned opposite to third side face along the main surface of the semiconductor substrate;a third insulating film formed over the fourth side face of the second gate electrode;a fourth insulating film formed over a side face of the third insulating film;a third semiconductor region formed over the main surface of the semiconductor substrate self-alignmentwise for the fourth side face of the second gate;a fourth semiconductor region formed over the main surface of the semiconductor substrate self-alignmentwise for a side face of the third insulating film so as to be electrically coupled to the third semiconductor region; anda second silicide layer formed over the fourth semiconductor region self-alignmentwise for a side face of the fourth insulating film,an end portion on the second gate electrode side of the second silicide layer being formed by the fourth insulating film at a position spaced away from a junction end between the third semiconductor region and the fourth semiconductor region.

4. A semiconductor device according to claim 1, wherein main surface of the semiconductor substrate with the second insulating film opposed thereto is depressed deeper than the main surface of the semiconductor substrate with the first gate electrode opposed thereto.

5. A semiconductor device according to claim 1, wherein the thickness of the second insulating film is in the range of 10 to 80 nm.

6. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming over a main surface of a semiconductor substrate an isolation region and an active region defined by the isolation region;(b) forming over the main surface of the semiconductor substrate an insulating film for charge storage of a non-volatile memory cell;(c) forming over the insulating film for charge storage a first gate electrode having a first side face and a second side face, the first and second side faces being positioned on mutually opposite sides along the main surface of the semiconductor substrate;(d) forming over the main surface of the semiconductor substrate a first semiconductor region self-alignmentwise for the first side face of the first gate electrode;(e) after the step (d), forming a first insulating film over the first side face of the first gate electrode;(f) after the step (e), forming over the main surface of the semiconductor substrate a second semiconductor region self-alignmentwise for a side face of the first insulating film so as to be electrically coupled to the first semiconductor region;(g) after the step (f), forming a second insulating film over the side face of the first insulating film; and(h) after the step (g), forming a first silicide layer over the second semiconductor region, the first silicide layer being formed self-alignmentwise for a side face of the second insulating film.

7. A method according to claim 6, wherein the second insulating film is formed in the same step as the step of forming a pattern of an insulating film which covers a silicide layer-free region over the main surface of the semiconductor substrate.

8. A method according to claim 6, wherein the step of forming the isolation region includes the steps of:forming a trench in the main surface of the semiconductor substrate; andburying an insulating film for isolation into the trench, andwherein the step (g) includes a step of:forming an insulating film in a depression formed in the portion adjacent to the active region over an upper surface of the insulating film for isolation in the main surface of the semiconductor substrate so as to cover a part of the semiconductor substrate over a side face of the trench exposed from the depression.

9. A method according to claim 6, further comprising, before the step (b), the steps of: forming a gate insulating film in a forming region of the nonvolatile memory cell over the main surface of the semiconductor substrate; andforming a second gate electrode over the gate insulating film and at a position adjacent to the second side face of the first gate electrode through the insulating film for charge storage, the second gate having a third side face opposed to the second side face of the first gate electrode and a fourth side face positioned opposite to the third side face along the main surface of the semiconductor substrate,wherein, in the step (d) of forming the first semiconductor region, a third semiconductor region is formed over the main surface of the semiconductor substrate self-alignmentwise for the fourth side face of the second gate electrode,wherein, in the step (e) of forming the first insulating film there is formed a third insulating film over the fourth side face of the second gate electrode,wherein, in the step (f) of forming the second semiconductor region there is formed a fourth semiconductor region over the main surface of the semiconductor substrate self-alignmentwise for a side face of the third insulating film so as to be electrically coupled to the third semiconductor region,wherein, in the step (g) of forming the second insulating film there is formed a fourth insulating film over the side face of the third insulating film, andwherein, in the step (h) of forming the first silicide layer there is formed a second silicide layer over the fourth semiconductor region self-alignmentwise for a side face of the fourth insulating film.

10. A method according to claim 6, wherein the thickness of the second insulating film is in the range of 10 to 80 nm.