Patent Application
20150279865
The present invention relates to a semiconductor device and a display device.
Liquid crystal panels in liquid crystal display devices have a plurality of switching elements or thin-film transistors (hereinafter, TFTs) that are arranged in a matrix (rows and columns) in order to control the operation of respective pixels. Conventionally, silicon semiconductors such as amorphous silicon were generally used as semiconductor films for TFTs. However, the usage of oxide semiconductors having high electron mobility as semiconductor films has been proposed recently. Patent Documents 1 to 3 disclose liquid crystal display devices adopting TFTs using these types of oxide semiconductors as switching elements. The usage of oxide semiconductors having high electron mobility can provide improvements such as size reduction of the TFTs compared to conventional products and improvement in the aperture ratio of the liquid crystal panel.
Patent Document 1: Japanese Patent Application Laid-Open Publication No. 2004-103957
Patent Document 2: Japanese Patent Application Laid-Open Publication No. 2006-165528
Patent Document 3: Japanese Patent Application Laid-Open Publication No. 2007-73705
The electrical characteristics of oxide semiconductors are susceptible to degradation when the oxide semiconductors come into contact with moisture. Therefore, there is a risk that the switching elements will not operate properly if moisture enters the TFTs using oxide semiconductors from outside, other films, and the like.
The object of the present invention is to provide a semiconductor device and a display device including the semiconductor device, in which the semiconductor device has a feature that suppresses foreign materials such as moisture from entering an oxide semiconductor film.
A semiconductor device according to the present invention has: a semiconductor film made of an oxide semiconductor film and having a channel region; a first insulating film formed on the semiconductor film so as to cover the channel region; and a first electrode electrically connected to the semiconductor film through an opening formed in the first insulating film in a location that does not overlap the channel region, the first electrode having an overlapping portion on the first insulating film such that the overlapping portion overlaps at least the semiconductor film. The semiconductor device has a semiconductor film that is formed of an oxide semiconductor film and that has: a channel region, a first insulating film formed on the semiconductor film so as to cover the channel region, and a first electrode that is electrically connected to the semiconductor film through an opening formed in the first insulating film in an area that does not overlap with the channel region, in which the first electrode on the first insulating film has an overlapping portion that overlaps at least the semiconductor film. In this manner, foreign materials such as moisture can be suppressed from entering the channel region of the semiconductor film by having the overlapping portion that overlaps the semiconductor film. As a result, this suppresses a change (degradation) in the electrical characteristics of the semiconductor film of the semiconductor device.
The semiconductor device may have: a substrate; a second electrode formed on the substrate so as to cover the second electrode; and a second insulating film formed on the substrate so as to cover the second electrode, wherein the semiconductor film is formed on the second insulating film, and wherein the first insulating film has a first interlayer insulating film that is formed so as to cover the channel region, and a resin insulating film formed on the first interlayer insulating film so as to cover the channel region.
The semiconductor device may have: a third electrode formed on the resin insulating film, wherein the first insulating film has a second interlayer insulating film formed on the resin insulating film so as to cover the third electrode and the channel region, and wherein the first electrode is formed on the second interlayer insulating film.
It is preferable that the semiconductor device have a protective film disposed between the semiconductor film and the first insulating film so as to cover the channel region. The protective film is excellent for suppressing foreign materials such as moisture and the like from entering the channel region of the semiconductor device.
It is preferable that the semiconductor device have a pair of fourth and fifth electrodes each having a contact portion in direct contact with a surface of the semiconductor film, the fourth and fifth electrodes facing each other across the channel region, wherein the protective film is formed so as to cover a portion of a surface of the semiconductor film that is not in contact with the contact portions. The channel region of the semiconductor film is more reliably protected from moisture and the like, because the protective film covers a portion of the surface of the semiconductor film that is not in contact with the contact portion. In addition, the semiconductor film including the channel region can be protected from moisture and the like even when the fourth electrode and the fifth electrode are being formed and the like.
The first electrode of the semiconductor device may be electrically connected to the fifth electrode.
The semiconductor film of the semiconductor device may be formed on the second insulating film so as to overlap the second electrode.
It is preferable that the semiconductor film of the semiconductor device have an oxide including at least one element selected from a group comprising indium (In), gallium (Ga), aluminum (Al), copper (Cu), zinc (Zn), and tin (Sn). If the semiconductor film of the semiconductor device has the above-mentioned configuration, the electron mobility of the semiconductor film is high even if the semiconductor film is amorphous, and the ON resistance of the switching element can be increased.
It is preferable that the semiconductor film of the semiconductor device be formed of indium gallium zinc oxide. If the semiconductor film of the semiconductor device is formed of indium gallium zinc oxide, then excellent characteristics of high mobility and low OFF current can be obtained.
It is preferable that the first interlayer insulating film of the semiconductor device be formed of silicon oxide. It is preferable that the first interlayer insulating film of the semiconductor device be formed of silicon oxide. Compared to silicon nitride, organic insulating material, and the like, silicon oxide is a material that is less likely to oxidize or reduce the semiconductor film and can suppress the electrical characteristics of the semiconductor film from changing (degrading).
It is preferable that the second interlayer insulating film of the semiconductor device be formed of silicon nitride.
The resin insulating film of the semiconductor device may be formed of an acrylic resin. Acrylic resin easily acquires moisture, and thus has a risk of causing the semiconductor film to oxidize due to the moisture, but because the overlapping portion is provided, the moisture is suppressed from moving towards the resin insulating film from outside or the like. As a result, even if the acrylic resin is used as the resin insulating film, the electrical characteristics of the semiconductor film are suppressed from changing (degrading).
The protective film of the semiconductor device may be formed of silicon oxide. Compared to silicon nitride, organic insulating material, and the like, silicon oxide is a material that is less likely to oxidize or reduce the semiconductor film and can suppress the electrical characteristics of the semiconductor film from changing (degrading), for example.
The second insulating film of the semiconductor device may have a multilayer structure having a bottom layer side insulating film formed of silicon nitride and a top layer side second insulating film formed of silicon oxide disposed between the bottom layer side second insulating film and the semiconductor film. Silicon oxide is a material that is less likely to oxidize or reduce the semiconductor film compared to silicon nitride, organic insulating material, and the like, for example. The electrical characteristics of the semiconductor film are suppressed from changing (degrading) by disposing the top layer side second insulating film formed of silicon oxide between the bottom layer side second insulating film and the semiconductor film.
A display device according to the present invention has: the semiconductor device; an opposite substrate facing the semiconductor device; and a liquid crystal layer disposed between the semiconductor device and the opposite substrate. If the display device has the configuration mentioned above, the electrical characteristics of the semiconductor film are suppressed from changing (degrading) and the display device has excellent operational reliability and the like.
The object of the present invention is to provide a semiconductor device that suppresses foreign materials such as moisture from entering a semiconductor film formed of an oxide semiconductor, and a display device including the semiconductor device.
Embodiment 1 of the present invention will be explained below with reference to
As shown in
The backlight device 12 is a device for supplying light to the liquid crystal panel 11 of the liquid crystal module LM and is attached to the rear surface (back side) side of the liquid crystal module LM (liquid crystal panel 11). The backlight device 12 mainly includes a chassis 12a having a substantially box shape that has an opening towards the front side (liquid crystal panel 11 side), a light source (not shown) housed in the chassis 12a, and an optical sheet (not shown) that is provided so as to cover the opening of the chassis 12a and that emits planar light by transmitting light from the light source. An LED, a cold cathode fluorescent lamp, or the like is used as the light source, for example. In addition, the optical sheet adjusts the light emitted from the light source into a uniform and planar light.
The backlight device 12 and the liquid crystal panel 11 that are attached to each other are housed and held by a pair of front and back exterior members (case) 16 and 17. The front exterior member 16 has a substantially frame shape when seen in a plan view from the front side and an opening 16a is provided in the central portion thereof. The display area AA of the liquid crystal panel 11 is exposed through this opening 16a such that the display area AA is seen by the user.
The flexible substrate 15 has a resin base material formed of a synthetic resin material (polyimide resin or the like, for example) that is insulating and flexible, and has a plurality of wiring patterns (not shown) formed on the resin base material. The flexible substrate 15 has a belt-shape as a whole and a control circuit substrate 14 is connected to an edge portion thereof. Furthermore, an edge portion of the liquid crystal panel 11 is connected to another edge portion of the flexible substrate 15. The input signal supplied from the control circuit substrate 14 side is transmitted to the liquid crystal panel 11 side by the flexible substrate 15. The flexible substrate 15 is housed within the liquid crystal display device 10 in a bent state such that the cross-section of the flexible substrate 15 is in a substantially U shape.
The driver 13 is formed of an LSI chip having a driving circuit therein, and the driver 13 is activated based on a signal supplied from the control circuit substrate 14, which is a signal supplying source. If the driver 13 is activated in this manner, the driver 13 processes the input signal supplied by the control circuit substrate 14 and generates an output signal. Then, the output signal is outputted towards the liquid crystal panel 11. The driver 13 is directly mounted onto the non-display area NAA of the rear surface side substrate (array substrate 11b mentioned later) of the liquid crystal panel 11 using a so-called COG (chip on glass) method.
The liquid crystal display device 10 of the present embodiment is used in various electronic devices such as a mobile information device (including electronic books, PDAs, and the like), mobile telephones (including smartphones), laptops (including tablet PCs and the like), digital photo frames, portable gaming devices, and electronic ink papers. The liquid crystal panel 11 used in the liquid crystal display device 10 of the present embodiment is usually categorized as small or medium small, and the screen size thereof ranges between several inches to around a dozen inches.
The liquid crystal panel 11 will be described here in detail. As shown in
The operation mode of the liquid crystal panel 11 of the present embodiment is commonly known as the FFS (fringe field switching) mode, which is a lateral electric field mode in which a pair of electrodes are provided on one substrate 11b and an electric field is applied to the liquid crystal molecules in a direction parallel (horizontal) to the substrate surface. Therefore, the array substrate (an example of a semiconductor device) 11b of the present embodiment has a pair of electrodes (pixel electrode and common electrode mentioned later) formed thereon.
The CF substrate 11a and the array substrate 11b both have substantially transparent glass substrates with high light-transmissive characteristics, and are formed of various films that are stacked on the glass substrate in a prescribed pattern. As shown in
In addition, alignment films (not shown) for aligning the liquid crystal molecules included in the liquid crystal layer 11c are respectively formed on the inner surface side of the two substrates 11a and 11b. Furthermore, polarizing plates (not shown) are bonded on the respective outer surfaces of the two substrates 11a and 11b.
The CF substrate 11a has respective colored portions (CF, not shown) of R (red), G (green), and B (blue) arranged in a matrix. The colored portions are respectively allotted to the pixels and overlap the respective pixel electrodes of the array substrate 11b (described later) in a plan view. Furthermore, the respective colored portions of the CF substrate 11a are separated by the grid shaped black matrix (not shown) having light-shielding characteristics. The black matrix overlaps the gate wiring lines and the source wiring lines on the array substrate 11b (mentioned later) in a plan view. The alignment film is formed on the respective colored portions and the black matrix. In addition, in the CF substrate 11a of the present embodiment, one display pixel (picture element) that is a display unit of the liquid crystal panel 11 is formed of a group of three colored portions: R (red), G (green), and B (blue).
Next, with reference to
The TFT 18 has a gate electrode (second electrode) 18a that extends from the gate wiring line 20, a semiconductor film 23 having a channel region 18b, a source electrode (fourth electrode) 18c extending from the source wiring line 21, and a drain electrode (fifth electrode) 18d. The source electrode 18c and the drain electrode 18d are disposed on the semiconductor film 23 while sandwiching the channel region 18b such that the source electrode 18c and the drain electrode 18d face each other with a gap therebetween. The source electrode 18c and the drain electrode 18d are both electrically connected to the semiconductor film 23.
A substrate 22 is formed of a glass substrate, a silicon substrate, or an insulating substrate having heat resistance such as a plastic substrate. It is preferable that a transparent substrate such as a glass substrate that transmits light be used as the substrate 22 for the liquid crystal display device 10 of the present embodiment. A glass substrate is used as the substrate 22 in the present embodiment.
Gate wiring lines 20 formed of a first metal film M1, a gate electrode 18a, and the like are formed on the surface of the substrate 22 facing inward (liquid crystal layer 11c side). Furthermore, a gate insulating film (second insulating film) 24 is formed on the substrate 22 such that the gate insulating film 24 covers the gate wiring lines 20 and the like formed of a first metal film M1. Furthermore, the semiconductor film 23 formed of an oxide semiconductor film, source wiring lines 21 formed of a second metal film M2, the source electrode 18c, the drain electrode 18d, and the like are formed on the gate insulating film 24. In addition, the first insulating film 28 is formed on the gate insulating film 24 so as to cover the semiconductor film 23, the source wiring lines 21, and the like.
In the present embodiment, the first insulating film 28 is formed of layers including a first interlayer insulating film 25, a resin insulating film 26, and a second interlayer insulating film 27. In the first insulating film 28, the first interlayer insulating film 25 is at the bottom (bottom layer), the second interlayer insulating film 27 is at the top (top layer), and the resin insulating film 26 is disposed between the first interlayer insulating film 25 and the second interlayer insulating film 27. The common electrode (third electrode) formed of a transparent conductive film is sandwiched by the resin insulating film 26 and the second interlayer insulating film. In addition, a pixel electrode (first electrode) 19 formed of a transparent conductive film is formed on the second interlayer insulating film 27 (first insulating film 28).
The first metal film M1 is formed of a layered film of titanium (Ti) and copper (Cu). The first metal film M1 is configured such that a film M1a formed of titanium (Ti) is disposed on the bottom layer side and a film M1b formed of copper (Cu) is disposed on the top layer side. The first metal film M1 is formed on the substrate 22 by sputtering or the like. Then, the gate wiring line 20 formed of the first metal film M1 having a prescribed pattern, the gate electrode 18a, and the like are formed on the substrate 22 by performing photolithography and wet etching the copper (Cu) film M1b, and by also performing dry etching, removal and washing of the resist, and the like to the titanium (Ti) film M1a.
The gate insulating film 24 is formed as a layered film having a bottom layer gate insulating film 24a formed of silicon nitride (SiNx) and a top layer gate insulating film 24b formed of silicon oxide (SiOx, x=2, for example). The gate insulating film 24 is formed using the CVD method or the like as appropriate.
The semiconductor film 23 is formed of a film of indium gallium zinc oxide, which is a type of oxide semiconductor. The indium gallium zinc oxide film that forms the semiconductor film 23 is amorphous or crystalline, and especially if the film is crystalline, then the film has a crystalline structure known as a c-axis aligned crystal. The semiconductor film 23 forms the channel region 18b and the like of the TFTs 18. Meanwhile, the semiconductor film 23 is not only used for TFTs that are for display, but also for the TFTs that are not for display (not shown) and the like disposed in the non-display area NAA. The semiconductor film 23 is formed with a prescribed pattern on the gate insulating film 24 by forming the indium gallium zinc oxide film by sputtering and then performing photolithography, wet etching, resist removal and washing, and the like on the indium gallium zinc oxide film.
The second metal film M2 is formed of a layered film of titanium (Ti) and copper (Cu). The second metal film M2 has a film M2a formed of titanium (Ti) disposed on the bottom layer side and a film M2b formed of copper (Cu) disposed on the top layer side. The second metal film M2 is formed on the gate insulating film 24 by sputtering or the like. In addition, the source wiring line 21 formed of the second metal film M2 having a prescribed pattern, the source electrode 18c, the drain electrode 18d, and the like are formed on the gate insulating film 24 by performing photolithography and wet etching to the copper (Cu) film M2b while performing dry etching, resist removal and washing, and the like to the titanium (Ti) film M2a. In addition, the channel region 18b of the semiconductor film 23 is exposed through the gap between the source electrode 18c and the drain electrode 18d.
The channel region 18b of the TFT 18 is mainly formed of a portion (region) of the semiconductor film 23 that is sandwiched between the source electrode 18c and the drain electrode 18d, and electrons can move between the source electrode 18c and the drain electrode 18d. As mentioned above, the semiconductor film 23 of the present embodiment is an indium gallium zinc oxide film and the electron mobility thereof, when compared to conventional amorphous silicon films and the like, is approximately twenty to fifty times higher. As a result, the TFTs 18 that use an indium gallium zinc oxide film (semiconductor film 23) can be reduced in size compared to conventional TFTs and the aperture ratio of the display region (pixel P) can be increased. The TFT 18 on the substrate 22 has the gate electrode 18a provided on the bottom layer, and the channel region 18b of the semiconductor film 23 stacked on the gate electrode 18a through the gate insulating film 24. In other words, the TFT 18 is a so-called inverse staggered type (bottom gate type).
As mentioned above, the first insulating film 28 is formed of three layers including the first interlayer insulating film 25, the resin insulating film 26, and the second interlayer insulating film 27. In addition, an opening (contact hole) 29 is formed in the first insulating film 28 to expose a portion of the drain electrode 18d. The opening 29 penetrates the first interlayer insulating film 25, the resin insulating film 26, and the second interlayer insulating film 27. The opening (contact hole) 29 is provided in a location that does not overlap the channel region 18b of the semiconductor film 23. The first insulating film 28 is formed on the gate insulating film 24 so as to cover the TFTs 18.
The first insulating film 25 is formed of silicon oxide (SiOx, x=2, for example) by using the plasma CVD method or the like so as to cover the source electrode 18c, the drain electrode 18d, the semiconductor film 23, and the like. The resin insulating film 26 is formed of an acrylic resin material that is an organic material (polymethyl methacrylate (PMMA) or the like, for example) and functions as a planarizing film. It is preferable that the acrylic resin material be photosensitive. The resin insulating film 26 is applied on the first interlayer insulating film 25 by spin coating, slit coating, or the like, for example. The second interlayer insulating film 27 that is formed of silicon nitride (SiNx) is formed on the resin insulating film 26 with the common electrode 30 through the plasma CVD method or the like so as to cover the common electrode 30.
The common electrode (third electrode) 30 is formed of a transparent conductive film such as ITO (indium tin oxide) and ZnO (zinc oxide). The common electrode 30 is formed on the resin insulating film 26 so as to cover a plurality of pixels P such that the plurality of pixels P share the common electrode 30. The common electrode P is formed so as to substantially cover the entire area of the display area AA of the array substrate 11b. The common electrode 30 has an opening 30a and the opening (contact hole) 29 that is provided in the first insulating film 28 is disposed inside the opening 30a. The transparent conductive film used for the common electrode 30 is formed on the second interlayer insulating film 27 (first insulating film 28) by sputtering, for example. Then, a common electrode 30 having a prescribed pattern is formed by performing photolithography, wet etching, resist removal and washing, and the like on the transparent conductive film. The common electrode 30 is sandwiched by the resin insulating film 26 and the second interlayer insulating film 27 and is formed inside the first insulating film 28.
The pixel electrode (first electrode) 19 is formed of a transparent conductive film such as ITO (indium tin oxide) and ZnO (zinc oxide) in a similar manner to the common electrode 30. The pixel electrode 19 is disposed so as to fit in the rectangular region (pixel P) surrounded by the gate wiring lines 20 and the source wiring lines 21 when the array substrate 11b is seen in a plan view. Furthermore, the pixel electrode 19 is mainly formed on the second interlayer insulating film 27 (first insulating film 28). When seeing the array substrate 11b in a plan view, the pixel electrode 19 has a rectangular main body 19a covering the pixel P region, an overlapping portion 19b that overlaps the TFT 18, and a connecting portion 19c that connects with the drain electrode 18d through the opening (contact hole) 29. The pixel electrode 19 is electrically connected to the semiconductor film 23 of the TFT 18 by being connected to the drain electrode 18d through the opening 29 of the connecting portion 19c.
The main body 19a has a plurality of slits 19d extending with a narrow shape along the alignment direction (Y axis direction) of the source wiring lines 21. Three slits 19d are provided in the present embodiment. The slits 19d are arranged on the main body 19a at even intervals.
The overlapping portion 19b is a portion of the pixel electrode 19 and is formed of a transparent conductive film such as ITO. When the array substrate 11b is seen in a plan view, the TFT 18 is inside the overlapping portion 19b. Thus, in a plan view, the overlapping portion 19b overlaps the semiconductor film 23 (channel region 18b) of the TFT 18 such that the semiconductor film 23 is inside the overlapping portion 19b. In this manner, foreign materials such as moisture are suppressed from entering the semiconductor film by having the overlapping portion 19b formed on the second interlayer insulating film 27 (first insulating film 28) such that the overlapping portion 19b overlaps the semiconductor film 23 of the TFT 18 in a plan view.
The pixel electrode 19 is formed by performing photolithography, wet etching, resist removal and washing, and the like on a transparent conductive film such as ITO formed by sputtering, for example.
The main body 19a and the overlapping portion 19b of the pixel electrode 19 face the common electrode 30 through the second interlayer insulating film 27. A common potential (reference potential) is applied to the common electrode 30 from a common wiring line (not shown). In addition, by controlling the potential applied to the pixel electrode 19 by the TFTs 18, a prescribed difference in potential is generated between the pixel electrode 19 and the common electrode 30.
If a prescribed difference in potential is generated between the pixel electrode 19 and the common electrode 30, then in the liquid crystal layer 11c between the array substrate 11b and the CF substrate 11a, the pixel electrode 19 having the slits 19d applies a fringe electric field (diagonal electric field) along a surface of the array substrate 11b and along a direction normal to the surface of the array substrate 11b. By controlling this electric field as appropriate, the alignment of the liquid crystal molecules within the liquid crystal layer 11c can be switched as appropriate.
As mentioned above, the array substrate (semiconductor device) 11b used in the liquid crystal display device 10 of the present embodiment is formed of an oxide semiconductor film, and includes the semiconductor film 23 having the channel region 18b, the first insulating film 28 formed so as to cover the channel region 18b of the semiconductor film 23 from above, and the pixel electrode (first electrode) 19 that is electrically connected to the semiconductor film 23 through the opening 29 formed in the first insulating film 28 at a location thereof that does not overlap the channel region 18b and that has an overlapping portion 19b on the first insulating film 28 at least overlapping the semiconductor film 23.
In this manner, in a plan view, by having the overlapping portion 19b that overlaps the semiconductor film 23, foreign material such as moisture can be suppressed from entering the channel region 18b of the semiconductor film 23. Conventionally, a pixel electrode is not formed in the upper area of the TFT 18 that does not transmit light. However, as in the present embodiment, by providing the overlapping portion 19b as a portion of the pixel electrode 19 on the first insulating film 28 (second interlayer insulating film 27) so as to overlap the semiconductor film 23 of the TFT 18 in a plan view, the moisture existing in the liquid crystal layer 11c and the like can be suppressed from permeating into the semiconductor film 23. In addition, when the second interlayer insulating film 27 is being formed, there are occasions in which fine air gaps or the like form in the second interlayer insulating film 27. Air gaps or the like forming in the second interlayer insulating film 27 makes it easier for moisture to move towards the bottom layer in particular. Furthermore, if air gaps or the like form in the second interlayer insulating film 27 at a position that overlaps the TFT 18, then this becomes a problem because moisture and the like are more likely to move towards the semiconductor film 23. However, as in the present embodiment, if the overlapping portion 19b is provided on the first insulating film 28 (second interlayer insulating film 27) so as to overlap the semiconductor film 23 of the TFT 18 in a plan view, the transparent conductive film forming the overlapping portion 19b will cover (in some cases bury) the air gaps or the like formed in the second interlayer insulating film 27. In other words, the overlapping portion 19b also has a function of repairing defective portions such as air gaps formed in the second interlayer insulating film 27.
Meanwhile, the array substrate 11b of the present embodiment has the substrate 22, the gate electrode (second electrode) 18a formed on the substrate 22, and the gate insulating film (second insulating film) 24 that is formed on the substrate 22 and that covers the gate electrode (second electrode) 18a. The semiconductor film 23 is formed on the gate insulating film 24. The first insulating film 28 is formed of the first interlayer insulating film 25 that covers the channel region 18b and the resin insulating film 26 that is formed on the first interlayer insulating film 25 and that covers the channel region 18b.
The array substrate 11b of the present embodiment has the common electrode (third electrode) 30 that is formed on the resin insulating film 26. The first insulating film 28 has the second interlayer insulating film 27 that is formed on the resin insulating film 26 and that covers the common electrode (third electrode) 30 and the channel region 18b. The pixel electrode (first electrode) 19 is formed on the second interlayer insulating film 27.
In addition, in the array substrate 11b of the present embodiment, the semiconductor film 23 is formed on the gate insulating film (second insulating film) 24 so as to overlap the gate electrode (second electrode) 18a. In particular, in the case of the present embodiment, the gate electrode 18a is configured to be larger than the semiconductor film 23 in a plan view. As a result, the semiconductor film 23 overlaps the gate electrode 18a in a plan view such that the semiconductor film 23 is within the gate electrode 18a.
In addition, it is preferable that the array substrate 11b of the present embodiment be formed of an oxide having at least one of an element in a group including indium (In), gallium (Ga), aluminum (Al), copper (Cu), zinc (Zn), and tin (Sn). If the semiconductor film 23 has this type of structure, even if the semiconductor film 23 is amorphous, the electron mobility is high, and the ON resistance of the switching element can be increased.
In addition, it is preferable that the semiconductor film 23 of the array substrate 11b in the present embodiment be formed of indium gallium zinc oxide. In particular, it is preferable that the semiconductor film 23 be an indium gallium zinc oxide film having the c-axis aligned crystal structure. If the semiconductor film 23 is formed of this type of indium gallium zinc oxide film, then excellent characteristics of high mobility and low OFF current can be obtained. The electrical characteristics of the semiconductor film 23 formed of an indium gallium zinc oxide and having the c-axis aligned crystal structure are particularly susceptible to changing (degrading) when foreign material such as moisture enters therein. As a countermeasure, if the array substrate 11b includes the pixel electrode 19 having the overlapping portion 19b as in the present embodiment, then the degradation of the electrical characteristics of the semiconductor film 23 can be effectively suppressed.
In addition, the first interlayer insulating film 25 of the array substrate 11b of the present embodiment is formed of silicon oxide. Compared to silicon nitride, organic insulating material, and the like, silicon oxide is a material that is less likely to oxidize or reduce the semiconductor film 23 and can suppress the change (degradation) of the electrical characteristics of the semiconductor film 23, for example.
In addition, the second interlayer insulating film 27 of the array substrate 11b in the present embodiment is formed of silicon nitride.
Also, the resin insulating film 26 of the array substrate 11b of the present embodiment is formed of an acrylic resin. Acrylic resin has characteristics of easily acquiring moisture, and thereby has a risk of causing oxidization or the like to the semiconductor film 23 with the moisture, but because the overlapping portion 19b is provided, moisture or the like moving to the resin insulating film 26 from outside (outer atmosphere and the liquid crystal layer 11c, for example) or the like is suppressed. As a result, even if an acrylic resin is used as the resin insulating film 26, the change (degradation) of the electrical characteristics of the semiconductor film 23 is suppressed.
In addition, the gate insulating film (second insulating film) 24 of the array substrate 11b of the present embodiment has a multilayer structure including the bottom layer side second insulating film 24a formed of silicon nitride and the top layer side second insulating film 24b that is formed of silicon oxide and that is disposed between the bottom layer side second insulating film 24a and the semiconductor film 23. Silicon oxide is a material that is less likely to oxidize or reduce the semiconductor film 23 compared to silicon nitride, organic insulating material, and the like, for example. By having this top layer side second insulating film 24b formed of silicon oxide disposed between the bottom layer side second insulating film 24a and the semiconductor film 23, the electrical characteristics of the semiconductor film 23 are suppressed from changing (degrading).
In addition, the liquid crystal display device 10 related to the present embodiment is formed of the array substrate 11b, the CF substrate (opposite substrate) 11a that is disposed so as to face the array substrate 11b, and the liquid crystal layer 11c disposed between the array substrate 11b and the CF substrate (opposite substrate). If the liquid crystal display device 10 of the present embodiment has the above-mentioned configuration, then the electrical characteristics of the semiconductor film 23 are suppressed from changing (degrading) and the liquid crystal display device confers excellent operational reliability and the like.
Next, Embodiment 2 of the present invention will be explained with reference to
The basic structure of the array substrate 111b of the present embodiment is similar to the structure in Embodiment 1. However, the array substrate 111b of the present embodiment is different from Embodiment 1 in that the array substrate 111b has a protective film (etch stop film) 31 disposed between a semiconductor film 23 and a first insulating film 28 (first interlayer insulating film 25) so as to cover a channel region 18b. The protective film 31 of the present embodiment mainly protects the channel region 18b of the semiconductor film 23. The edge portion of the source electrode 18c is disposed on the semiconductor film 23 such that the edge portion slightly rides up over the protective film 31. In addition, an edge portion of the drain electrode 18d disposed on the semiconductor film 23 is also slightly riding up over the protective film 31 in a similar manner.
The protective film 31 of the present embodiment is formed of silicon oxide (SiOx, in which x=2, for example). This protective film 31 is formed by performing photolithography, etching, resist removal and cleaning, and the like on the silicon oxide film formed by the plasma CVD method or the like. If the protective film 31 is formed on the array substrate 111b such that the protective film 31 covers the channel region 18b of the semiconductor film 23, then the channel region is protected from foreign material such as moisture during the production of the array substrate 111b (in particular, during the processing of a second metal film M2 of the source electrode 18c and the like). In addition, after the array substrate 111b is manufactured, even when the array substrate is mounted on the display device, if the protective film 31 is formed so as to cover the channel region 18b of the semiconductor film 23, then foreign materials such as moisture are suppressed from entering the channel region 18b of the semiconductor film 23 and the degradation of the semiconductor film 23 is suppressed.
Compared to silicon nitride, organic insulating material, and the like, silicon oxide is a material that is less likely to oxidize or reduce the semiconductor film 23, and can suppress the change (degradation) of the electrical characteristics of the semiconductor film 23.
In a similar manner to the array substrate 111b of the present embodiment, the degradation of the electrical characteristics of the semiconductor film 23 caused by foreign materials such as moisture entering can be further suppressed, because the overlapping portion 19b of the pixel electrode 19 overlaps the semiconductor film 23 in a plan view and the channel region 18b is protected by the protective film 31.
Next, Embodiment 3 of the present invention will be explained with reference to
In the case of the present embodiment, the protective film 31 is provided so as to cover a portion of the surface of the semiconductor film 23 that is not in contact with the source electrode 18c or the drain electrode 18d. For convenience of explanation, the portion of the source electrode 18c that contacts the semiconductor film 23 is referred to as a contact portion 18c1, and the portion of the drain electrode 18d that contacts the semiconductor film 23 is referred to as a contact portion 18d1. The protective film 31 has an opening 31a to make the contact portion 18c1 contact the semiconductor film 23 and has an opening 31b to make the contact portion 18d1 contact the semiconductor film 23. In the case of the present embodiment, the protective film 31 is formed so as to cover the entire gate insulating film 24 (excluding portions other than openings 31a and 31b). In a similar manner to Embodiment 2, the protective film 31 of the present embodiment is also formed by performing photolithography, etching, resist removal and cleaning, and the like to the silicon oxide formed by the plasma CVD method or the like.
A source electrode (fourth electrode) 18c and a drain electrode (fifth electrode) 18d forms a pair on the array substrate 211b of the present embodiment such that the electrodes 18c and 18d face each other with the channel region 18b therebetween. The electrodes 18c and 18d respectively have the contact portion 18c1 and 18d1 that come into direct contact with the surface of the semiconductor film 23. In addition, the protective film 31 formed on the array substrate 211b so as to cover a portion of the surface of the semiconductor film 23 other than the portion in contact with the contact portion 18c1 and 18d1. In this manner, the protective film 31 more reliably protects the semiconductor film 23 (in particular, channel region 18b) from moisture and the like by covering the surface of the semiconductor film 31 that do not contact the contact portions 18c1 and 18d1. In addition, even when the source electrode (fourth electrode) 18c and the drain electrode (fifth electrode) 18d are formed or the like, the semiconductor film 23 including the channel region 18b can be protected from moisture and the like.
If the overlapping portion 19b of the pixel electrode 19 overlaps the semiconductor film 23 that is protected by the protective film 31 in a plan view in a similar manner to the array substrate 211b of the present embodiment, the degradation of the electrical characteristics of the semiconductor film 23 caused by foreign material such as moisture entering can be further suppressed compared to Embodiment 1 and Working Example 2.
Next, Embodiment 4 of the present invention will be explained with reference to
In a similar manner to the array substrate 311b of the present embodiment, if the overlapping portion 19b of the pixel electrode 19 is provided so as to overlap the semiconductor film 123 of the TFT 118 that has the gate electrode 118a with a narrow width in a plan view, then, in a similar manner to Embodiment 1, the degradation of the electrical characteristics of the semiconductor film 123 due to foreign materials such as moisture entering can be suppressed.
Next, Embodiment 5 of the present invention will be explained below with reference to
Here, the degradation of the electrical characteristics of the semiconductor film 123 due to foreign material such as moisture entering is further suppressed compared to Embodiment 4 having the same TFT 118 structure, because the overlapping portion 19b of the pixel electrode 19 is provided so as to overlap the semiconductor film 123 in a plan view such that the channel region 118b is protected by the protective film 131 in a similar manner to the array substrate 411b of the present embodiment.
Next, Embodiment 6 of the present invention will be explained below with reference to
In the present embodiment, the protective film 131 is formed so as to cover a portion the surface of the semiconductor film 123 that is not in contact with the source electrode 118c or the drain electrode 118d. For convenience of explanation, the portion of the source electrode 118c that contacts the semiconductor film 123 is referred to as a contact portion 118c1, and the portion of the drain electrode 118d that contacts the semiconductor film 123 is referred to as a contact portion 118d1. The protective film 131 has an opening 131a to make the contact portion 118c1 contact the semiconductor film 123 and has an opening 131b to make the contact portion 118d1 contact the semiconductor film 123. In the case of the present embodiment, the protective film 131 is formed so as to cover the entire gate insulating film 24 (excluding portions other than openings 131a and 131b). In a similar manner to Embodiment 2 and the like, the protective film 131 of the present embodiment is also formed by performing photolithography, etching, resist removal and cleaning, and the like on the silicon oxide film formed by a plasma CVD method or the like.
In a similar manner to the array substrate 511b of the present embodiment, compared to Embodiments 4 and 5 sharing the same TFT 118 structure, the degradation of the electrical characteristics due to foreign material such as moisture entering is further suppressed, because the overlapping portion 19b of the pixel electrode 19 is provided so as to overlap the semiconductor film 123 of the protective film 131 in a plan view.
The present invention is not limited to the embodiments shown in the drawings and described above, and the following embodiments are also included in the technical scope of the present invention, for example.
(1) In the respective embodiments above, an example of an array substrate for an FFS mode liquid crystal display device was shown, but in other embodiments, as long as the objective of the present invention is not hindered, an array substrate for a liquid crystal display device using other operation modes such as an IPS (in-plane switching) mode liquid crystal display device or a VA (vertical alignment) mode liquid crystal display device may be used.
(2) In the respective embodiments above, the first insulating film had three layers including the first interlayer insulating film, the resin insulating film, and the second interlayer insulating film, but in other embodiments, as long as the objective of the present invention is not hindered, the first insulating film may be formed of one layer, two layers, or more than three layers.
(3) In addition, the first insulating film of the respective embodiments above has a common electrode (third electrode) between the resin insulating film and the second interlayer insulating film, but in other embodiments, the first insulating film may be configured such that an electrode such as a common electrode is not provided, depending on the operation mode and the like.
(4) In the respective embodiments above, the first interlayer insulating film is formed of silicon oxide (SiOx), but in other embodiments, silicon nitride (SiNx), silicon oxynitride (SiNxOy, x>y), silicon oxynitride (SiOxNy, y>x), and the like may be used.
(5) In the respective embodiments above, the second interlayer insulating film is formed of silicon nitride (SiNx), but in other embodiments, silicon oxide (SiOx), silicon oxynitride (SiNxOy, x>y), silicon oxynitride (SiOxNy, y>x), and the like may be used.
(6) In the respective embodiments above, the first metal film used for the gate wiring line, the gate electrode, and the like, and the second metal film used to form the source wiring line, the source electrode, the drain electrode, and the like were both layered structures having two layers (two types) of metal films, but in other embodiments, these metal films may be formed of one layer (one type), for example.
(7) In the respective embodiments above, the first metal film and the second metal film both have a bottom layer side that is a titanium (Ti) film, and a copper (Cu) film is formed on the titanium (Ti) film as the top layer side. In other embodiments, the bottom layer side may be formed of a metal film other than a titanium (Ti) film such as molybdenum (Mo), molybdenum nitride (MoN), titanium nitride (TiN), tungsten (W), niobium (Nb), tantalum (Ta), molybdenum titanium (MoTi), and molybdenum tungsten (MoW).
(8) In the respective embodiments above, the gate insulating film (second insulating film) had a two layer structure, but in other embodiments, the gate insulating film may have one layer or more than two layers. In addition, the gate insulating film may be formed of materials other than silicon nitride (SiNx) and silicon oxide (SiOx) such as silicon nitride (SiNx), silicon oxynitride (SiNxOy, x>y), silicon oxynitride (SiOxNy, y>x), and the like.
(9) In the respective embodiments above, a capacitance wiring line was not provided on the array substrate, but in other embodiments, a capacitance wiring line may be provided as necessary.
(10) In the respective embodiments above, the opening (contact hole) for connecting the pixel electrode to the drain electrode was provided in a location that is relatively far from the TFT, but in other embodiments, the opening may be provided in a location closer to the TFT than in the respective embodiments above.
(11) In the respective embodiments above, a transparent conductive film such as ITO was used as a material of the pixel electrode (first electrode), but in other embodiments (for reflective liquid crystal display devices, for example), a conductive film such as titanium, tungsten, nickel, gold, platinum, silver, aluminum, magnesium, calcium, lithium, and alloys of these may be used, for example.
(12) In the respective embodiments mentioned above, an array substrate used as a semiconductor device of a liquid crystal panel was shown as an example, but in other embodiments, the semiconductor device may be used in an organic EL device, inorganic EL device, electrophoretic device, or the like.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2012-221255 | Oct 2012 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2013/076483 | 9/30/2013 | WO | 00 |
