Patent Application
20220006264
The present disclosure relates to a semiconductor device and method of fabrication thereof relating to III-V compounds grown on silicon (Si).
The realization of semiconductor laser diodes on a Si platform will enable the fabrication of complex optoelectronic circuits, which will permit the creation of chip-to-chip, rack-to-rack and system-to-system optical communications. Although in the last 30 years great effort has been devoted to Si-based light generation and modulation technologies, lasers grown directly on Si substrates are still considered to be one of the greatest challenges to be realized among all Si photonics components and have massive potential for applications if successful. Due to the indirect band structure of Si and Ge, efficient radiative recombination processes for Ge and Si emitters are insignificant compared to non-radiative recombination. Direct bandgap III-V compounds have robust photonic properties for semiconductor emitters in a wide range of photonic applications. Direct epitaxial growth of III-V compound semiconductor materials, such as GaAs on Si substrates is one of the most promising candidates for the fabrication of electrically pumped lasing sources on a Si platform, because of its potential for the realization of photonic integrated circuits by combining the optoelectronic properties of III-V with Si very large scale integration (VLSI) microelectronic technology. The heteroepitaxial technology could also provide III-V compound semiconductor photonic circuits with large-area, low-cost and lightweight substrates with high mechanical strength and high thermal conductivity, which can accommodate associated electronic functions.
The most severe problem remaining to be solved in the monolithic integration of GaAs and other III-V compounds on Si substrate is the large material dissimilarity between III-V and Group IV materials, including lattice mismatch, thermal expansion coefficient differences, and polar versus nonpolar surfaces. These differences between III-V and Group IV materials tend to produce various types of defects—antiphase boundaries (APBs), threading dislocations (TDs), and microcracks—which all generate nonradiative recombination centers and dramatically undermine the promise of III-V materials. Reducing the defect density within the GaAs buffer layer on Si substrates is critical for successful integration of III-Vs-based photonic components with Si microelectronic circuits. Moreover, recent studies have shown that III-V nanosized crystals—quantum dots (QDs)—are a better alternative to quantum wells for building III-V lasing devices on a Si platform due to their unique advantages, such as lower threshold current density (Jth), temperature-insensitive operation above room temperature (RT), and lower sensitivity to defects.
We have shown in the patent, (U.S. Pat. No. 9,343,874 (B2)) that the use of an AlAs nucleation layer prior to the growth of the III-V layer on Si can enable a successful electrically pumped laser to be grown on Si. We have also shown in patent (U.S. Pat. No. 9,401,404 (B2)) that the use of Ge on Si as the substrate upon which the III-V layer is grown can enable a successful electrically pumped laser to be grown on Si.
Both approaches mentioned above have used offcut substrates, i.e. Si (001) or equivalent orientation wafers with an offcut of 4° to the [110] plane and Ge (001) wafers with an offcut of 6° to the [110] plane, in order to prevent the formation of antiphase domains (APDs) while growing polar III-V materials on non-polar group-IV substrates. Although this approach is successful in overcoming the APD problem, it has the disadvantage of not being readily compatible with standard microelectronics fabrication where wafers with nominally (001) silicon substrates are used. In general, the nominal silicon substrates, i.e., the so-called “exact” (001) silicon substrates with a miscut angle less than 0.5°, have been used in standard microelectronics fabrication. Recently, optically pumped microcavity lasers have been demonstrated on exact (001) Si substrates by nanopatterning the Si (Wan, Y., Li, Q., Liu, A. Y., Gossard, A. C., Bowers, J. E., Hu, E. L., Lau, K. M. Optically pumped 1.3 pm room temperature InAs quantum-dot microdisk lasers directly grown on (001) silicon. Optics Letters, 41, (2016)) and recently an electrically pumped laser has been demonstrated by growth on a GaP/Si (001) template (Liu et al, Electrically pumped continuous wave III-V quantum dot lasers epitaxially grown on exact GaP/Si (001)). Neither approach uses substrates that are standard for microelectronic fabrication and the electrically pumped laser threshold current density is over 800 A/cm2, which is a much higher value than is achieved in our previous work on offcut substrates (U.S. Pat. Nos. 9,343,874 and U.S. 9,401,404) The high threshold current density restricts the application of these lasers in practical optical interconnects. The present disclosure seeks to alleviate, at least partially, some or any of the above problems.
In this application, the electrically pumped silicon-based InAs/GaAs quantum-dot laser has been demonstrated by the use of direct grown GaAs on nominal (001) Si substrates. RT continuous wave (cw) lasing at ˜1.3 μm with threshold current density of 425 A/cm2 and output power of 43 mW at room temperature has been achieved. Under pulsed operation, we show significantly improved device performance including lasing operation at device temperatures exceeding 100° C. and output from a single facet exceeding 130 mW at room temperature by limiting self-heating.
Further features, characteristics, and aspect of the present disclosure are described in the following figures. These serve for easy understanding of the disclosure. In the figures:
Embodiments of the disclosure will now be described, by way of example only, with reference to the accompanying drawings in which:
In one exemplary embodiment of the present disclosure, as shown in
The nucleation layer is different from the III-V compound buffer layer. Although the nucleation layer (NL) and the buffer layer comprise the same material, they use different growth parameters, including but not limited to substrate temperature and gas flow rates during the manufacturing process. In one example, for the GaAs N, the wafer was cooled to a low temperature of 400-500° C. (measured by optical pyrometer) and the first GaAs layer of 20 nm thickness was deposited, then the wafer was reheated to conventional growth temperature of 600-700° C. to grow a high quality GaAs buffer layer of 380 nm thickness. The typical V/III ratio is in the range of 5-30.
Other growth conditions leading to the creation of a GaAs buffer layer with minimum defect density can be used.
The structural properties of the GaAs film layer grown on Si (001) by MOCVD is characterized by both AFM and TEM measurements.
This silicon-based QD laser has also been tested under pulsed operation, and lasing up to 120° C. was demonstrated with an output of over 130 mW at room temperature with limited self-heating as seen in
These results have demonstrated the use of direct grown GaAs on nominal (001) Si substrates for silicon-based 1.3-pm InAs/GaAs QDs lasers. RT cw lasing at ˜1.3 pm is achieved with threshold current density of 425 A/cm2. With limited self-heating, we show significantly improved device performance with lasing operation over 100° C. and output from a single facet exceeding 130 mW at room temperature under pulsed operation, values which are better than conventional values for 1.3-pm InAs/GaAs QD devices grown on Si substrates with a GaP nucleation layer.
Crystal growth. The compound semiconductor layers were grown by solid-source III-V molecular beam epitaxy (MBE). InAs/GaAs QD samples were grown on a GaAs coated silicon piece cut from standard on-axis Si (001) 300 mm substrates with an offcut angle about 0.15° towards the [110] direction. The oxide desorption was performed by thermally heating the GaAs/Si virtual substrate to a temperature of 610° C. in ultra-high vacuum exposed with a high molecular beam flux of arsenic for 8 minutes. The substrate was then cooled down to 590° C. for the growth of a 600-nm GaAs buffer and a 100 nm superlattice consisting of alternating layers of 1 nm Al0.4Ga0.6As and 1 nm GaAs. Five sets of 10-nm Ino.isGao.siAs/10-nm GaAs stained layer superlattices (five periods) followed by 350-nm GaAs were then deposited as dislocation filter layers. Thermal annealing was introduced after growth of the stained layer superlattices and prior to the 350-nm GaAs. Finally, a layer InAs/InGaAs dot-in-a-well (DWELL) laser structure, consisting of 1400 nm Si-doped Al0.4Ga0.6As bottom cladding layer, 50 nm undoped Al0.2Ga0.xAs spacer and 70 nm undoped GaAs bottom waveguide layers, five periods of InAs/Ino.isGao.siAs QWELLs, 70 nm undoped GaAs and 50 nm undoped Alo.iGao.sAs spacer top waveguide layers, 1400 nm Be-doped Al0.4Ga0.6As top cladding layer, and finally 300 nm heavily Be-doped GaAs top contact layer. Each period of InAs/Ino.ixGao.xiAs QWELLs consists of 2.7 MLs of InAs quantum dots sandwiched by 2 nm of Ino.isGao.siAs and 6 nm of Ino.i8Gao.82As. These DWELL lasers were grown at 510° C. The five periods of DWELLs were separated by 45-nm GaAs barriers grown at 580° C. for GaAs.
Device Fabrication'. The Si-based QD laser structure was fabricated into broad-area lasers with varying stripe widths of 25 pm and 50 pm following standard optical lithography and wet chemical etching techniques. The top mesa was etched to about 100 nm above the active region. The top n-contact layer was etched down to the highly n-doped GaAs buffer layer just below the n-type AlGaAs cladding layer. Ti/Pt/Au and Ni/GeAu/Ni/Au were deposited on top of the etch mesa and exposed highly n-doped GaAs buffer layer to form the p- and n-contacts, respectively. After thinning the silicon substrate to 120 pm, the laser bars were cleaved into the desired cavity lengths, which were then mounted on copper heatsinks and gold-wire bonded to enable testing. The final devices described here were 25 pm in width and 3 mm in length, and no facet coatings were applied.
Measurements'. The surface morphology was characterized by a Nanoscope Dimension 3100 SPM atomic force microscopy (AFM) system using a standard tapping mode. The structural properties were investigated by cross-section transmission electron microscopy (TEM) using a JEOL 201 OF field-emission microscope operating at 200 kV. Optical properties were measured by photoluminescence (PL) measurements excited from a 532 nm diode-pumped solid-state laser. Laser device characteristics were measured under both cw and pulsed conditions of Ips pulse-width and 1% duty-cycle.
Although the use of superlattice DFLs has been described above, their number and design may be varied according to the dislocation density at the MOCVD/MBE epitaxy interface layer.
In the earlier described embodiments of the disclosure, the layer that is grown on top of the NL epilayer is GaAs. However, any suitable III-V compound could be used, such as InP, GaSb, GaAs or mixtures of the elements in these compounds. GaN is excluded from the possible III-V compounds because it has a wurtzite crystal structure, so is generally not compatible with the epilayer, which is typically of the zinc blende crystal structure. In contrast, GaAs has a zinc blende crystal structure and a similar lattice constant to AlAs, so the AlAs nucleation layer (epilayer) has close crystallographic properties to GaAs and specifically mitigates the presence of defects at the interface; consequently, active photonic structures grown on top can have enhanced properties.
Optionally, the mean thickness of the NL is at least 2.5 nm. By providing that the mean thickness of the NL is at least 2.5 nm, the prevention of threading dislocations can be improved.
Optionally, the buffer layer of the III-V compound, other than GaP, formed directly on the NL has a mean thickness of at least 100 nm.
Optionally, the silicon substrate has an offcut angle of less than 0.5° towards the [110] direction. Optionally, the silicon substrate has a non-zero offcut angle towards the [110] direction.
The disclosure is not limited to a quantum dot laser on a Si substrate, but could be used for other general semiconductor structures, for example detectors, modulators or other III-V photonic devices on a Si substrate. III-V electronic devices, such as diodes and transistors could also be fabricated with the use of this disclosure. Applications include but are not limited to chip-to-chip optical inter-connects, solar cells, optical fibre communications (light emitters and detectors).
In a method embodying the present disclosure, the NL can be grown at a relatively low temperature, because it is relatively thin. This can be advantageous in lowering the quality of any interfacial defects. The NL can be grown at a temperature below 500° C. A suitable temperature range is from 300° C. to 500° C., and is exemplified in the description above at 400° C.
In the detailed method described above, the crystal growth is by both MOCVD and MBE, but it could also be done by any combination of these techniques or by chemical vapour deposition (CVD) or by other epitaxy techniques.
Semiconductor devices and fabrication methods have been described above with reference to various specific embodiments and examples. However, it is to be understood that the claims below are in no way limited to these specific embodiments and examples.
The foregoing description of some embodiments of the disclosure has been presented for purposes of illustration and description. The description is not intended to be exhaustive or to limit the disclosure to the precise form disclosed, and modifications and variations are possible in light of the above teachings. The specifically described embodiments explain the principles and practical applications to enable one ordinarily skilled in the art to utilize various embodiments and with various modifications as are suited to the particular use contemplated. Various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 1620826.6 | Dec 2016 | GB | national |
The present application is a continuation of U.S. application Ser. No. 16/467,626, filed Jun. 7, 2019 which is a National Phase of International Application Number PCT/GB2017/053686, filed Dec. 7, 2017, and claims priority to Great Britain Application Number 1620826.6, filed Dec. 7, 2016, the disclosure of which is hereby incorporated by reference herein in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16467626 | Jun 2019 | US |
| Child | 17374392 | US |
