Patent Application
20220140748
The present invention relates to a semiconductor device, for example, to a semiconductor device which can be suitably utilized for the inverter device used in motor control.
A full-bridge inverter device is known as an inverter device that converts single DC power into AC power. The inverter device converts direct current into alternating current and controls the motor and is used in a wide range of fields such as in-vehicle, industrial and consumer fields. Japanese Unexamined Patent Application Publication No. 2016-146386 (Patent Document 1) discloses a technique for suppressing ringing of switching waveforms in a full-bridge inverter circuit.
The full-bridge inverter circuit includes four switch elements, as shown in FIG. 1 of Patent Document 1. The full-bridge inverter circuit alternately conducts switch elements arranged diagonally, and controls the width of the ON pulse to a variable, to control the output voltage. By using the full-bridge inverter circuit, the power supply device can be made smaller and lighter, and noise reduction and power conversion efficiency can be improved. However, the switch elements are not switched instantaneously. Therefore, power loss in the switching time (hereinafter, referred to as switching loss) occurs.
The switching loss is obtained by (power loss generated per pulse)*(switching frequency). The switching loss increases in proportion to the switching frequency. In recent years, since the switching frequency tends to increase, the switching loss also tends to increase. Therefore, in order to prevent a decrease in power conversion efficiency while increasing the switching frequency, a reduction in switching loss generated for each pulse is required.
Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.
According to an embodiment, semiconductor device includes a first input terminal and a second input terminal, a series circuit comprising a plurality of switch elements coupled between the first and second input terminals, further, a series circuit comprising a diode and an inductor and coupled in parallel to each of the plurality of switch elements.
According to the one embodiment, it is possible to reduce the switching loss of the switching elements in the inverter device.
Hereinafter, a semiconductor device according to an embodiment will be described in detail by referring to the drawings. In the specification and the drawings, the same or corresponding form elements are denoted by the same reference numerals, and a repetitive description thereof is omitted. In the drawings, for convenience of description, the configuration may be omitted or simplified. Also, at least some of the embodiments may be arbitrarily combined with each other.
In first embodiment, the inverter device including an inverter circuit will be described. In particular, the inverter device including a full-bridge inverter circuit will be described.
Before describing of the present embodiment, a typical full-bridge inverter device 100 will be explained with reference to
The switch element Q11 and the switch element Q12 are coupled in series. The switch element Q11 and the switch element Q12 coupled in series are coupled in parallel to the DC power source E The switch element Q11 is disposed on the high side (positive potential side), the switch element Q12 is disposed on the low side (negative potential side). A diode D11 is coupled in anti-parallel with the switch element Q11, and a diode D12 is coupled in anti-parallel with the switch element Q12.
Similarly, the switch element Q13 and the switch element Q14 are coupled in series. The switch element Q13 and the switch element Q14 coupled in series are coupled in parallel to the DC power source E. The switch element Q13 is disposed on the high side (positive potential side), and the switch element Q14 is disposed on the low side (negative potential side). A diode D13 is coupled in anti-parallel with the switch element Q13, and a diode D14 is coupled in anti-parallel with the switch element Q14.
A load 102 is electrically coupled between a node A, which is a joint of the switch element Q11 and the switch element Q12, and a node B, which is a joint of the switch element Q13 and the switch element Q14. For example, the load 102 is an inductor, hereinafter referred to as an inductor 102.
Next, the operation of a typical full-bridge inverter device will be described. The full-bridge inverter circuit 101 alternately conducts the switch elements Q11, Q14 and the switch elements Q12, Q13 which are arranged diagonally, and variably controls the ON pulse width thereof to control the output voltage. In
Here, as an example, the operation of generating a negative voltage component of the AC voltage will be described.
In the first operation mode, the current flows in an order of the power source E, the switch element Q13, the node B, the inductor 102, the node A, the switch element Q12 and the power source E. Consequently, the negative polarity energy is stored in the inductor 102.
In the second operation mode following the first operation mode, the current does not flow in the path of the first operation mode. However, the current flowing through the inductor 102 tries to keep continuity. That is, the inductor 102 attempts to continue flowing current from the node B to the node A. In this case, the current flows through the diode D11 coupled in anti-parallel with the switch element Q11. Therefore, when both the switch elements Q12 and Q14 are turned off, a current flows from the switch element Q13 which is turned on to the diode D11 in an order of the node B, the inductor 102 and the node A. Thus, in the second operation mode, commutation of the current occurs.
The third operation mode following the second operation mode is the same operation as the first operation mode. Therefore, the description is omitted.
In the fourth operation mode following the third operation mode, the current does not flow in the path of the third operation mode. However, the current flowing through the inductor 102 tries to keep continuity. That is, the inductor 102 attempts to continue flowing current from the node B to the node A. In this case, since a current does not flow from the switch element Q13 which is turned off to the node B, a current flows through the diode D14 which is coupled in anti-parallel with the switch element Q14. Therefore, when both the switch elements Q11 and Q13 are turned off, a current flows from the switch element Q12 to the node A in an order of the diode D14, the node B and the inductor 102. Thus, in the fourth operation mode, commutation of the current occurs.
Among the above operations, the first and third operation modes are referred to as a conduction mode, and the second and fourth operation modes are referred to as a commutation mode. The full-bridge inverter circuit 101 alternately repeats the conduction mode and commutation mode to produce an AC voltage.
The full-bridge inverter circuit 10 has an input terminal IN1 (first input terminal), an input terminal IN2 (second input terminal), an output terminal OUT1 (first output terminal) and an output terminal OUT2 (second output terminal). A DC power source E is coupled between the input terminal IN1 and IN2. Furthermore, the full-bridge inverter circuit 10 includes switch elements Q1-Q4, diodes D1-D4 and inductors L1-L4.
The switch elements Q1 and Q2 are coupled in series. A series circuit (first series circuit) including the switch elements Q1 and Q2 is coupled between the input terminals IN1 and IN2. That is, the series circuit including the switch device Q1 and Q2 is coupled in parallel to the DC power source E. The switch element Q1 is disposed on the high side (positive potential side), the switch element Q2 is disposed on the low side (negative potential side).
The switch elements Q3 and Q4 are coupled in series. A series circuit (second series circuit) including the switch elements Q3 and Q4 is coupled between the input terminals IN1 and IN2. That is, the series circuit including the switch device Q3 and Q4 is coupled in parallel to the DC power source E. The switch element Q3 is disposed on the high side (positive potential side), the switch element Q4 is disposed on the low side (negative potential side).
The joint of the switch elements Q1 and Q2 is electrically coupled to the output terminal OUT1. The joint of the switch elements Q3 and Q4 is electrically coupled to the output terminal OUT2. Between the output terminals OUT1 and OUT2, a load is coupled. Hereinafter, examples in which the inductor Lload is coupled as the load will be described.
A series circuit including a diode and an inductor is coupled in parallel to each of switch elements Q1 to Q4. Specifically, the series circuit (third series circuit) including the diode D1 and the inductor L1 is coupled in parallel to the switch element Q1. The series circuit (fourth series circuit) including the diode D2 and the inductor L2 is coupled in parallel to the switch element Q2. The series circuit (fifth series circuit) including the diode D3 and the inductor L3 is coupled in parallel to the switch element Q3. The series circuit (sixth series circuit) including the diode D4 and the inductor L4 is coupled in parallel to the switch element Q4.
The diodes D1 to D4 are respectively coupled to the switch elements Q1 to Q4 so that the forward current of the diode D1 to D4 flow in a direction opposite to a direction of the current flowing when the switch elements Q1 to Q4 are turned on, respectively. One end of each of the inductors L1 to L4 is coupled to the cathode of each diodes D1 to D4.
The switch elements Q1 to Q4 include, for example, field-effect transistors (FETs), MOSFET and IGBT (Insulated Gate Bipolar Transistor), and the like, but are not limited thereto.
The operation of the inverter device 1 of first embodiment will be described. The full-bridge inverter circuit 10 according to first embodiment, similarly to a typical full-bridge inverter circuit, the switch elements Q1 and Q4 disposed diagonally, and the switch elements Q2 and Q3 are alternately conducted. The switch elements Q1 to Q4 are turned on or off by the PWM drive signals output from the switch drive controller 11. It is repeated alternately the conduction mode and the commutation mode according to the PWM drive signals, so that an AC voltage is generated between the output terminals OUT1 and OUT2. In
Referring to
The first operation mode according to first embodiment shown in the
The second operation mode according to first embodiment shown in the
The third operation mode according to first embodiment shown in
Here, the switching loss with a transition from the second operation mode to the third operation mode, i.e., a transition from the commutation mode to the conduction mode will be described.
The fourth operation mode according to first embodiment shown in
Here, the switching loss with a transition from the third operation mode to the fourth operation mode, i.e., a transition from the conduction mode to the commutation mode will be described. When an inductor is inserted into a path through which current flows, such as present embodiment, the impedance is increased when transiting from the conduction mode to the commutation mode. However, in present embodiment, since the series circuit including the diode D4 and the inductor L4 is coupled in parallel to the switch element Q4, immediately after the series circuit transitions from the third operation mode to the fourth operation mode, a current flows first through the switch element Q4. Therefore, the voltage applied across the switch element Q4 does not increase greatly. As a result, the switching loss when the switch element Q3 is turned off can be as large as the switching loss when the switch element of the typical full-bridge inverter circuit 101 shown in
As described above, according to present embodiment, the switching loss with the transition from the commutation mode to the conduction mode, i.e., when the switch element Q2 is turned from off to on, is reduced. On the other hand, the switching loss with the transition from the conduction mode to the commutation mode, i.e., when the switch element Q3 is turned from on to off, is comparable to the typical full-bridge inverter circuit. Therefore, according to present embodiment, overall, switching loss generated per pulse is reduced. The switching loss is proportional to the number of switching times. Therefore, for the inverter device with a higher switching frequency, it is expected to have a high switching loss reduction effect. Therefore, the full-bridge inverter circuit 10 according to present embodiment is suitable for the inverter device with a higher switching frequency.
Incidentally, as described above, in order to reduce the switching loss of the full-bridge inverter circuit 10, it is necessary to appropriately determine the value of the inductor L.
In present embodiment, the full-bridge inverter circuit are explained. However, it is similarly applicable to the half-bridge inverter circuit. That is, by providing a series circuit made of a diode and an inductor coupled in parallel to the switch elements of the half-bridge inverter circuit, it is possible to reduce the switching loss of the half-bridge inverter circuit.
Next, an inverter device including a HERIC inverter circuit (HERIC inverter device) will be described.
Before describing the present embodiment, a typical HERIC inverter device will be explained with reference to
The HERIC inverter circuit 201 includes a full-bridge inverter circuit 22 and a bidirectional circuit 203. The full-bridge inverter circuit 22 includes switch elements Q2 to Q24 and diodes D21 to D24. The configuration of the full-bridge inverter circuit 22 is the same as the configuration of the full-bridge inverter circuit 101 shown in
The bidirectional circuit 203 includes switch elements Q25 and Q26. The switch elements Q25 and Q26 are coupled in series between nodes A and B. The switch element Q25 is coupled so as to flow or interrupt a current flowing from the node A to the node B. The switch element Q26 is coupled so as to flow or interrupt a current flowing from the node B to the node A. The diode D205 is coupled in anti-parallel to the switch element Q25. The diode D206 is coupled in anti-parallel to the switch element Q26.
One end of the inductor L21 is coupled to the node A. One end of the inductor L22 is coupled to the node B. The capacitor C is coupled between the other end of the inductor L21 and the other end of the inductor L22.
A DC power source E is coupled between the input terminals IN1 and IN2 of HERIC inverter device 200. Further, a load (not shown) is coupled between the output terminals OUT1 and OUT2 of HERIC inverter device 200 coupled between the other end of the inductor L21 and the other end of the inductor L22.
Referring to
In first period, the switch elements Q21 and Q24 are controlled by the PWM drive signal. In the first period, the switch elements Q22, Q23, and Q25 are turned off, and the switch element Q26 is turned on. In the first period, while the switch elements Q21 and Q24 are turned on, the current flows in an order of the power source E, the switch element 21, node A, the inductor L21, load, the inductor L22, node B, the switch element Q24 and the power source E. While the switch elements Q21 and Q24 are turned off, the nodes A and B are in the vicinity of the intermediate potential of the power source E. Therefore, the diodes D21 to D24 are all reverse biased and no current flows. Thus, the path of current in the full-bridge circuit 22 is interrupted. Therefore, in the first period, as shown in
In the first period, when the switch elements Q21 and Q24 are turned from off to on, as shown in
In second period, as shown in
In the second period, when the switch elements Q22 and Q23 are turned from off to on, as in the operation of the first period, the reverse recovery current flows in the diode D206. Thus, the current flowing through the switch elements Q22 and Q23 is increased, as a result, the switching loss is increased.
The HERIC inverter circuit 21 includes a full-bridge inverter circuit 22 and the bidirectional circuit 23. The configuration of the full-bridge inverter circuit 22 may be similar to that shown in
The bidirectional circuit 23 shown in
Next, the operation of HERIC inverter device according to second embodiment will be described with reference to
In first period, the switch elements Q21 and Q24 are controlled by the PWM drive signals. In first period, the current path flowing while the switch elements Q21 and Q24 are turned on, and the current path flowing while the switch elements Q21 and Q24 are turned off are the same as the typical HERIC inverter device 200 as described above, the description thereof will be omitted.
Also, in the HERIC inverter device 20 of present embodiment, when the switch elements Q21 and Q24 are turned from off to on, a reverse recovery current flows in the diode D25, as shown in
In the second period, the switching loss when the switch elements Q22 and Q23 are turned from off to on can also be suppressed as well as the switching loss in the first period.
As described above, in order to improve the switching loss of the HERIC inverter circuit 21, the values of the inductors L25 and L26 need to be appropriately obtained.
Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment described above, and it is needless to say that various modifications can be made without departing from the gist thereof.
