Patent Application
20240324227
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-045519, filed Mar. 22, 2023, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor device and a manufacturing method thereof.
A semiconductor device such as a NAND-type flash memory having a three-dimensional structure in which a plurality of insulating layers and a plurality of metal layers are stacked is proposed. In the semiconductor device, improvement in characteristics such as writing and erasing is desired.
Embodiments provide a semiconductor device capable of improving characteristics such as writing and erasing.
In general, according to one embodiment, a semiconductor device includes a stack including a conductor layer and an insulator layer alternately stacked, a block insulating layer provided along a side surface of the stack, a channel layer, a charge storage layer provided between the block insulating layer and the channel layer, and a tunnel layer provided between the charge storage layer and the channel layer, where the charge storage layer includes a first charge storage layer containing Si, N and at least one of Al, Mo, Nb, Hf, Zr, Ti, B, or P, a second charge storage layer containing Si and N, in which Si is contained at a second concentration higher than a first concentration that is a concentration of Si in the first charge storage layer, and provided between the first charge storage layer and the tunnel layer, and a dielectric layer containing O and provided between the first charge storage layer and the second charge storage layer.
Hereinafter, the present embodiment will be described with reference to the drawings. In order to facilitate understanding of the description, the same elements are designated by the same reference numerals as much as possible in each drawing, and duplicate description is omitted.
The semiconductor device 10 according to the embodiment of the present disclosure may be used as a semiconductor storage device and is also referred to as a semiconductor storage device 10 in the following description. In order to facilitate understanding of the description, the same elements are designated by the same reference numerals as much as possible in each drawing, and duplicate description is omitted. In addition, in the following description, each drawing may show an X-axis, a Y-axis, and a Z-axis. The X-axis, the Y-axis, and the Z-axis form a three-dimensional right-handed orthogonal coordinate. Hereinafter, the arrow direction of the X-axis may be referred to as the X-axis front, and the direction opposite to the arrow may be referred to as the X-axis rear. The same applies to the other axes. The Z-axis front and the Z-axis rear may be referred to as “upper side” to “upper” and “lower side” to “lower”, respectively. In addition, the Z-axis direction may also be referred to as a “stacking direction”. In addition, a plane orthogonal to each of the X-axis, the Y-axis, or the Z-axis may be referred to as a YZ plane, a ZX plane, or an XY plane, respectively. Meanwhile, these directions and the like are used for convenience to describe the relative positional relationship. Therefore, these directions do not define an absolute positional relationship.
As shown in
The memory controller 1 controls writing of data to the semiconductor device 10 according to a write request from the host. Further, the memory controller 1 controls reading of data from the semiconductor device 10 according to a read request from the host.
Between the memory controller 1 and the semiconductor device 10, each signal of a chip enable signal/CE, a ready busy signal/RB, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal/WE, read enable signals RE and/RE, a write protect signal/WP, a data signal DQ<7:0>, data strobe signals DOS and/DQS are communicated.
The chip enable signal/CE is a signal for enabling the semiconductor device 10. The ready busy signal/RB is a signal for indicating whether the semiconductor device 10 is in a ready state or a busy state. The “ready state” is a state in which an external command is received. The “busy state” is a state in which an external command is not received. The command latch enable signal CLE is a signal indicating that the signal DQ<7:0> is a command. The address latch enable signal ALE is a signal indicating that the signal DQ<7:0> is an address. The write enable signal/WE is a signal for taking the received signal into the semiconductor device 10 and is asserted each time the memory controller 1 receives a command, an address, and data. The memory controller 1 instructs the semiconductor device 10 to take the signal DQ<7:0> while the signal/WE is at an “L (Low)” level.
The read enable signals RE and/RE are signals for the memory controller 1 to read data from the semiconductor device 10. The read enable signals RE and/RE are used, for example, to control the operation timing of the semiconductor device 10 when outputting the signal DQ<7:0>. The write protect signal/WP is a signal for instructing the semiconductor device 10 to perform data write and erasing protection. The signal DQ<7:0> is an entity of data communicated between the semiconductor device 10 and the memory controller 1, and include commands, addresses, and data. The data strobe signals DQS and/DQS are signals for controlling the input/output timing of the signal DQ<7:0>.
The memory controller 1 includes a RAM 11, a processor 12, a host interface 13, an ECC circuit 14, and a memory interface 15. The RAM 11, the processor 12, the host interface 13, the ECC circuit 14, and the memory interface 15 are connected to each other via an internal bus 16.
The host interface 13 outputs the request received from the host, user data (write data), and the like to the internal bus 16. Further, the host interface 13 transmits the user data read from the semiconductor device 10, the response from the processor 12, and the like to the host.
The memory interface 15 controls a process of writing user data and the like to the semiconductor device 10 and a process of reading the user data from the semiconductor device 10 based on the instruction of the processor 12.
The processor 12 controls the memory controller 1 in an integrated manner. The processor 12 is, for example, a CPU, an MPU, or the like. When receiving a request from the host via the host interface 13, the processor 12 controls in response to the request. For example, the processor 12 instructs the memory interface 15 to write the user data and parity to the semiconductor device 10 according to the request from the host. Further, the processor 12 instructs the memory interface 15 to read the user data and the parity from the semiconductor device 10 according to the request from the host.
The processor 12 determines a storage area (a memory area) on the semiconductor device 10 with respect to the user data stored in the RAM 11. The user data is stored in the RAM 11 via the internal bus 16. The processor 12 performs determination of the memory area with respect to data in page units (page data), which is the unit of writing. The user data, which is stored on one page of the semiconductor device 10, is hereinafter also referred to as “unit data”. The unit data is generally encoded by adding a correction code and is stored in the semiconductor device 10 as a codeword. The encoding is not essential in the present embodiment. The memory controller 1 may store the unit data in the semiconductor device 10 without encoding, and
The processor 12 determines the memory area of the semiconductor device 10 to be written for each unit data. A physical address is assigned to the memory areas of the semiconductor device 10. The processor 12 manages the memory area to which unit data is written using physical addresses. The processor 12 specifies the determined memory area (physical address) and instructs the memory interface 15 to write user data to the semiconductor device 10. The processor 12 manages correspondence between logical addresses of user data (logical addresses managed by the host) and physical addresses. When receiving a read request including a logical address from the host, the processor 12 identifies the physical address corresponding to the logical address, specifies the physical address, and instructs the memory interface 15 to read user data.
The ECC circuit 14 encodes the user data stored in the RAM 11 to generate a codeword. Further, the ECC circuit 14 decodes the codeword read from the semiconductor device 10.
The RAM 11 temporarily stores user data, which is received from host, until the user data is stored in the semiconductor device 10, or temporarily stores data, which is read from the semiconductor device 10, until the read data is transmitted to the host. The RAM 11 is a general-purpose memory such as an SRAM or a DRAM.
When a write request is received from the host, the memory system in
When a read request is received from the host, the memory system in
As shown in
The memory cell array 21 is a portion for storing data. The memory cell array 21 is configured to have a plurality of memory cell transistors associated with a plurality of bit lines and a plurality of word lines.
The input/output circuit 22 communicates the signal DQ<7:0>, and the data strobe signals DOS, /DQS with the memory controller 1. Further, the input/output circuit 22 transfers a command and an address in the signal DQ<7:0> to the register 24. Further, the input/output circuit 22 communicates write data and read data with the sense amplifier 28.
The logic control circuit 23 receives control signals such as the chip enable signal/CE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal/WE, the read enable signals RE and/RE, and the write protect signal/WP from the memory controller 1. Further, the logic control circuit 23 transfers the ready busy signal/RB to the memory controller 1 to transmit the state of the semiconductor device 10 to the outside.
The register 24 temporarily latches various data. For example, the register 24 latches commands for instructing a write operation, a read operation, an erasing operation, and the like. This command is input from the memory controller 1 to the input/output circuit 22, and then transferred from the input/output circuit 22 to the register 24 and latched. The register 24 also latches the address corresponding to the above command. This address is input from the memory controller 1 to the input/output circuit 22, and then transferred from the input/output circuit 22 to the register 24 and latched. Further, the register 24 also latches the status information indicating the operation state of the semiconductor device 10. The status information is updated by the sequencer 25 each time according to the operation state of the memory cell array 21 and the like. The status information is output from the input/output circuit 22 to the memory controller 1 as a state signal in response to the request from the memory controller 1.
The sequencer 25 controls the operation of each portion including the memory cell array 21 based on the control signals input from the memory controller 1 to the input/output circuit 22 and the logic control circuit 23.
The voltage generation circuit 26 is a portion that generates the voltage required for each of the data write operation, read operation, and erasing operation in the memory cell array 21. This voltage includes, for example, a voltage applied to a plurality of word lines and a plurality of bit lines of the memory cell array 21, respectively. The operation of the voltage generation circuit 26 is controlled by the sequencer 25.
The row decoder 27 is a circuit including a group of switches for applying a voltage to each of a plurality of word lines of the memory cell array 21. The row decoder 27 receives a block address and a row address from the register 24, selects a block based on the block address, and selects a word line based on the row address. The row decoder 27 switches the open/closed state of the group of switches so that the voltage from the voltage generation circuit 26 is applied to the selected word line. The operation of the row decoder 27 is controlled by the sequencer 25.
The sense amplifier 28 is a circuit for adjusting the voltage applied to the bit line of the memory cell array 21 or reading the voltage of the bit line and converting the read voltage into data. At the time of reading the data, the sense amplifier 28 acquires the data read from the memory cell transistor of the memory cell array 21 to the bit line, and transfers the acquired read data to the input/output circuit 22. When writing data, the sense amplifier 28 transfers the data written via the bit line to the memory cell transistor. The operation of the sense amplifier 28 is controlled by the sequencer 25.
The input/output pad group 30 is a portion provided with a plurality of terminals (pads) for communicating each signal between the memory controller 1 and the input/output circuit 22. Each terminal is individually provided corresponding to each of the signal DQ<7:0> and the data strobe signals DQS and/DQS.
The logic control pad group 31 is a portion provided with a plurality of terminals for communicating each signal between the memory controller 1 and the logic control circuit 23. Each terminal is individually provided corresponding to the chip enable signal/CE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal/WE, the read enable signals RE and/RE, the write protect signal/WP, and the ready busy signal/RB.
The power input terminal group 32 is a portion provided with a plurality of terminals for receiving each necessary voltage to be applied for the operation of the semiconductor device 10. The voltage applied to each terminal includes power supply voltages Vcc, VccQ, Vpp, and a ground voltage Vss. The power supply voltage Vcc is a circuit power supply voltage supplied from the outside as an operation power supply, and is, for example, a voltage of about 3.3 V. The power supply voltage VccQ is, for example, a voltage of 1.2V. The power supply voltage VccQ is a voltage used when communicating signals between the memory controller 1 and the semiconductor device 10. The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, and for example, is a voltage of 12 V.
Next, the electrical circuit configuration of the memory cell array 21 will be described. As shown in
The plurality of string units SU0 to SU3 configure one block as a whole. In
Hereinafter, the string units SU0 to SU3 will also be referred to as a “string unit SU” without distinguishing each of the string units SU0 to SU3. In addition, the memory cell transistors MT0 to MT7 will also be referred to as a “memory cell transistor MT” without distinguishing each of the memory cell transistors MT0 to MT7.
The memory cell array 21 has N-bit lines BL0 to BL (N−1). It should be noted that “N” is a positive integer. Each string unit SU has N NAND strings SR, which are the same number as the number N of the bit lines BL0 to BL (N−1). The memory cell transistors MT0 to MT7 provided in the NAND string SR are disposed in series between the source of the select transistor STD and the drain of the select transistor STS. The drain of the select transistor STD is connected to any of the plurality of bit lines BL0 to BL (N−1). The source of the select transistor STS is connected to a source line SL. In the following description, the bit lines BL0 to BL (N−1) will also be referred to as a “bit line BL” without being distinguished from each other.
Each memory cell transistor MT is configured as a transistor having a charge storage layer in a gate portion. The amount of charge stored in the charge storage layer corresponds to the data latched in the memory cell transistor MT. The memory cell transistor MT may be, for example, a charge trap type using a silicon nitride film or the like as the charge storage layer, or a floating gate type using a silicon film or the like as the charge storage layer.
Gates of the plurality of select transistors STD provided in the string unit SU0 are all connected to the select gate line SGD0. A voltage for switching the on and off of each select transistor STD is applied to the select gate line SGD0. The string units SU1 to SU3 are also connected to the select gate lines SGD1 to SGD3 in the same manner.
The gates of the plurality of select transistors STS provided in the string unit SU0 are all connected to the select gate line SGS0. A voltage for switching the on and off of each select transistor STS is applied to the select gate line SGS0. The string units SU1 to SU3 are also connected to the select gate lines SGS1 to SGS3 in the same manner. The select gate line may be shared in the string units SU0 to SU3 configuring one block, and the gates of the select transistors STS of each of the string units SU0 to SU3 may be connected to the common select gate line.
Each of gates of the memory cell transistors MT0 to MT7 is connected to the word lines WL0 to WL7. The word lines WL0 to WL7 are applied with a voltage for the purpose of switching the on and off of the memory cell transistors MT0 to MT7, changing the amount of charge stored in each charge storage layer of the memory cell transistors MT0 to MT7, and the like.
Writing and reading of data in the semiconductor device 10 are collectively performed for a plurality of memory cell transistors MT connected to any word line WL in any string unit SU for each unit referred to as a “page”. On the other hand, the data erasure in the semiconductor device 10 is collectively performed on all the memory cell transistors MT provided in the block. As a specific method for performing writing, reading, and erasing of such data, it is possible to adopt various known methods, and thus a detailed description thereof will be omitted.
Next, the structure of the semiconductor device 10, particularly the structure in the vicinity of the memory cell array 21 will be specifically described. As shown in
The substrate 40 is a plate-like member having a flat surface on the Z-axis direction side. The substrate 40 is, for example, a silicon wafer. The insulator layer 41 and the semiconductor layer 42 are formed on the upper surface of the substrate 40 as multi-layer films by, for example, chemical vapor deposition (CVD) film formation. For example, an element separation region 40i is provided on the surface of the substrate (semiconductor substrate) 40. The element separation region 40i is, for example, an insulating region including silicon oxide, and is a portion that defines a source region and a drain region of the transistor Tr.
The insulator layer 41 is formed of an insulating material such as silicon oxide. A peripheral circuit including, for example, a transistor Tr and a wiring LN or the like is formed in a bottom portion in contact with the substrate 40 of the insulator layer 41. The peripheral circuit configures a sense amplifier 28, a row decoder 27, and the like shown in
The semiconductor layer 42 is a layer that functions as a source line SL in
The semiconductor layer 42 may be formed of a semiconductor material such as silicon as a whole, but may be formed of a stacked structure of at least two layers including a semiconductor layer 42a and a conductive layer 42b as shown in
The stack 50 is provided on the upper surface of the semiconductor layer 42. The stack 50 has a structure in which a plurality of insulator layers 51 and a plurality of conductor layers 52 are alternately stacked in the Z-axis direction. The insulator layer 51 and the conductor layer 52 are formed as multi-layer films on the upper surface of the semiconductor layer 42 by, for example, a film forming method using a CVD method.
The conductor layer 52 is a layer having a conductivity and is formed of a material including, for example, tungsten. Each of the conductor layers 52 is used as a word line WL0 to WL7, a select gate line SGS1, a select gate line SGD1, or the like in
A plurality of memory holes MH are formed in the stack 50 to penetrate in the Z-axis direction. A memory pillar 60 is formed inside each memory hole MH. Each memory pillar 60 is formed in a region from the insulator layer 51 located at the uppermost position in the Z-axis direction to the semiconductor layer 42. Each memory pillar 60 corresponds to the NAND string SR shown in
As shown in
The body 60a has a core portion 62 and a semiconductor portion 64. The semiconductor portion 64 includes a semiconductor material and is formed of, for example, a material including amorphous silicon or a material including polysilicon. The semiconductor portion 64 is a portion that forms a channel of a memory cell transistor MT or the like, and functions as a semiconductor channel of the present embodiment. Therefore, in the present embodiment, the semiconductor portion 64 is also referred to as a channel layer 64. The core portion 62 is provided inside the semiconductor portion 64. The core portion 62 is formed of an insulating material such as silicon oxide, for example. The body 60a may have a structure in which the entire body 60a is the semiconductor portion 64 and in which the inner core portion 62 is not provided.
The stacked film 60b is a multi-layer film formed at a position to cover the outer periphery of the body 60a. The stacked film 60b has, for example, a tunnel insulating film 66 (in the present embodiment, also referred to as a “tunnel layer”) and a charge storage layer 68. The tunnel insulating film 66 is a film provided at the position of the outer periphery of the body 60a. The tunnel insulating film 66 includes, for example, a silicon oxide, a silicon oxide and a silicon nitride, or a silicon oxynitride. The tunnel insulating film 66 is a potential barrier between the body 60a and the charge storage layer 68. For example, when the electron is injected from the body 60a into the charge storage layer 68 (write operation), the electron passes through the potential barrier of the tunnel insulating film 66 (tunneling). In addition, when the positive holes are injected from the body 60a to the charge storage layer 68 (erasing operation), the positive holes pass through the potential barrier of the tunnel insulating film 66.
The charge storage layer 68 is a film covering the outside of the tunnel insulating film 66. The charge storage layer 68 contains, for example, silicon nitride. The charge storage layer 68 has trap sites that trap charges in the film. The portion of the charge storage layer 68 interposed between the conductor layer 52 and the body 60a configures the charge storage layer storing charges, that is, the portion configures the storage region of the memory cell transistor MT. The threshold voltage of the memory cell transistor MT changes depending on the presence or absence of the charge in the charge storage layer 68 or the amount of the charge. In the present embodiment, the charge storage layer 68 includes a first charge storage layer 68a, a dielectric layer 68b, and a second charge storage layer 68c. The first charge storage layer 68a, the dielectric layer 68b, and the second charge storage layer 68c of the present embodiment will be described in detail later.
As shown in
A cover insulating film 54 (second block insulating film 54 (in the present embodiment, also referred to as a “block insulating layer”)) is provided between the insulator layer 51 and the charge storage layer 68. The cover insulating film 54 may be formed of, for example, a material containing silicon oxide. It is possible that the cover insulating film 54 protects the charge storage layer 68 from being etched in a replacement step of replacing the sacrificial layer (sacrificial layer 55 to be described later) with the conductor layer 52.
A portion of the memory pillar 60 located inside each of the conductor layers 52 functions as a transistor. That is, in each memory pillar 60, a plurality of transistors are electrically connected in series along the longitudinal direction. Each of the conductor layers 52 is connected to the gate of each transistor via the stacked film 60b. The semiconductor portion 64 (channel layer 64) inside the transistor functions as a channel of the transistor.
A part of each transistor arranged in series along the longitudinal direction of the memory pillar 60 functions as a plurality of memory cell transistors MT shown in
As shown in
The stack 50 is divided into a plurality of pieces by the slit ST. The slit ST is a linear groove extending along the Y direction in
The upper portion of the stack 50 is divided by the slit SHE. The slit SHE is a shallow groove extending in the Y direction. The slit SHE is formed to a depth at which only the conductor layer 52 provided as the select gate line SGD is divided among the plurality of conductor layers 52.
The stacked film 60b is removed from the lower end portion of the memory pillar 60. Accordingly, the lower end portion of the semiconductor portion 64 is connected to the semiconductor layer 42. With such a structure, the semiconductor layer 42 functioning as the source line SL and the channel of each transistor are electrically connected.
The semiconductor device 10 according to the present embodiment includes a stack 50, a block insulating layer (second block insulating film) 54, a channel layer (semiconductor portion) 64, a tunnel layer (tunnel insulating film) 66, and a charge storage layer 68. The stack 50 includes a conductor layer 52 and an insulator layer 51 that are alternately stacked. The block insulating layer 54 is provided along the side surface of the stack 50. The charge storage layer 68 is provided between the block insulating layer 54 and the channel layer 64. The tunnel layer 66 is provided between the charge storage layer 68 and the channel layer 64. That is, the block insulating layer 54, the charge storage layer 68, the tunnel layer 66, and the channel layer 64 are provided in this order along a direction from the conductor layer 52 toward the core portion 62. The charge storage layer 68 includes a first charge storage layer 68a, a dielectric layer 68b, and a second charge storage layer 68c. The second charge storage layer 68c is provided between the first charge storage layer 68a and the tunnel layer 66. The dielectric layer 68b is provided between the first charge storage layer 68a and the second charge storage layer 68c. Therefore, the first charge storage layer 68a, the dielectric layer 68b, and the second charge storage layer 68c are provided in this order.
The first charge storage layer 68a contains at least one additive element (hereinafter, also referred to as an additive) of Al, Mo, Nb, Hf, Zr, Ti, B, or P, Si, and N. That is, the first charge storage layer 68a contains SiN as a main component and at least one element of Al, Mo, Nb, Hf, Zr, Ti, B, or P as an additive. For example, the concentration of the additive is 5% or less in the first charge storage layer 68a. For example, the concentration of the additive is 1% or less in the first charge storage layer 68a. The dielectric layer 68b contains at least one of silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or aluminum oxide (AlOx). AlOx includes, for example, Al2O3. The second charge storage layer 68c contains Si and N, in which Si is contained at a second concentration higher than a first concentration that is a concentration of Si in the first charge storage layer 68a. The semiconductor device 10 according to the embodiment of the present disclosure has such a configuration, and thus it is possible to improve write characteristics and charge storage characteristics as described below. Therefore, it is possible to improve the reliability when the semiconductor device 10 is used as a memory, for example.
In the present embodiment, the first charge storage layer 68a may contain an oxynitride of at least one of Al, Mo, Nb, Hf, Zr, Ti, B, or P as an additive.
The concentration of the additive contained in the first charge storage layer 68a may be, for example, 1×1019 atoms/cm2 or more and 5×1020 atoms/cm2 or less. By including the additive of 1×1019 atoms/cm2 or more, it is possible to effectively implement the deepening of the trap level of the first charge storage layer 68a by the additive. In addition, t is preferable that the amount of the additive is 5×1020 atoms/cm2 or less since it is possible to reduce the influence of damage due to the additive to the region containing Si and N of the first charge storage layer 68a.
The dielectric layer 68b may contain AlOx such as Al2O3, and in this case, the concentration of AlOx is preferably 1×1014 atoms/cm2 or more and 1×1015 atoms/cm2 or less. By forming the dielectric layer 68b containing AlOx, it is possible to increase the dielectric constant, for example, as compared with a case where the dielectric layer 68b is formed of SiON or SiOCN. Therefore, it is considered that it is possible to improve the write characteristics, for example, since it is possible to strengthen the tunnel field in the dielectric layer 68b.
The second charge storage layer 68c preferably has an N/Si ratio of 1.1 or more and 1.2 or less, which is a ratio of N to Si contained. That is, for example, it is preferable that the second charge storage layer 68c is formed, when the N/Si ratio is close to stoichiometry and is close to 1.33 in the first charge storage layer 68a, the second charge storage layer 68c has the second concentration, which is the Si concentration, is higher than the first concentration, which is the Si concentration of the first charge storage layer 68a, and the concentration (second concentration) has the N/Si ratio of 1.1 or more and 1.2 or less. The second charge storage layer 68c has the N/Si ratio of 1.1 or more and 1.2 or less, and thus it is possible to implement the effect such as reducing the charge leakage caused by the residual of the hole between the regions where the conductor layer 52 is formed during the erasing operation to be described later.
Hereinafter, the operation and effect of the semiconductor device 10 according to the embodiment of the present disclosure will be described with reference to the semiconductor device 200 of the comparative example.
On the other hand, the dielectric layer 268b is provided, so that the relative volume of the first charge storage layer 268a and the second charge storage layer 268c may be reduced, and the write characteristics may deteriorate. In addition, since the equivalent oxide thickness (EOT) of the portion in which the dielectric layer 268b is provided increases, deterioration of the write characteristics may occur even when the magnitude of the electric field applied to the charge storage layer 268 at the time of writing data is relatively small (that is, when the dielectric layer 268b is provided, a larger voltage is applied as compared with a case where the dielectric layer 268b is not provided in order to trap the same amount of charge as the charge that can be trapped in a configuration in which the dielectric layer 268b is not provided).
On the other hand, according to the semiconductor device 10 according to the embodiment of the present disclosure, the first charge storage layer 68a in the charge storage layer 68 having the NON-configuration contains at least one additive of Si, N, and at least one of Al, Mo, Nb, Hf, Zr, Ti, B, or P, and thus it is possible to improve deterioration of write characteristics described above and the like of the semiconductor device 200 according to the comparative example. In addition, in the present embodiment, by adding at least one of Al, Mo, Nb, Hf, Zr, Ti, B, or P to the first charge storage layer 68a on the block insulating layer 54 side, the trap level in the first charge storage layer 68a can be deepened. Therefore, the charge is easily trapped, and thus it is possible to reduce the leakage of the charge. Therefore, it is possible to improve the write characteristics and the charge storage characteristics.
Further, in the semiconductor device 10 according to the embodiment of the present disclosure, the second charge storage layer 68c is provided in such that the second charge storage layer 68c has the concentration of the Si contained in the second charge storage layer 68c provided on the tunnel layer 66 side of the charge storage layer 68 entering the second concentration higher than the first concentration which is the concentration of the Si in the first charge storage layer 68a is contained. That is, since the second charge storage layer 68c contains a relatively large amount of Si, it is considered that the erasure of the stored charge (that is, the leakage of charge) is promoted, for example, at the time of erasing data. Therefore, it is considered that since the number of holes required when the data is erased can be reduced, the number of holes remaining in the region between the conductor layers 52 can be reduced as compared with that of the semiconductor device 200 according to the comparative example. Therefore, it is considered that it is possible to reduce the leakage of the charge caused by the remaining hole.
In the semiconductor device 10 according to the embodiment of the present disclosure, the concentration of Si is relatively high in the second charge storage layer 68c on the tunnel layer 66 side. Therefore, it is possible to reduce the charge leakage that is likely to occur when the concentration of Si in the charge storage layer 268 is simply increased, and thus the erase characteristics can be improved. In addition, it is possible to reduce the residual of the hole between the conductor layers 52 at the time of erasing, and the like, and thus it is possible to reduce the leakage of the charges in the Z-axis direction.
As described above, the semiconductor device 10 according to the embodiment of the present disclosure has the above-described configuration, and thus it is possible to improve write characteristics and the like. Therefore, it is possible to improve the reliability.
Hereinafter, a first modification example of the present embodiment will be described.
Hereinafter, a second modification example of the present embodiment will be described.
In addition, the anti-oxidation layer 65 may have the concentration of C in the SiCN or SiOCN contained in the anti-oxidation layer 65 higher on the block insulating layer 54 side than on the tunnel layer 66 side of the anti-oxidation layer 65. When the anti-oxidation layer 65 has the concentration of C higher on the block insulating layer 54 side, since the concentration of C at the interface of the anti-oxidation layer 65 with the first charge storage layer 68a is high, it is considered that the charge storage effect in the first charge storage layer 68a can be improved. Therefore, it is considered that it is possible to further reduce the deterioration of the above-described write characteristics and/or erase characteristics.
In addition, in the present embodiment, the first charge storage layer 68a contains at least one of Al, Mo, Nb, Hf, Zr, Ti, B, or P as described above, but the first charge storage layer 68a may contain an oxynitride of at least one of Al, Mo, Nb, Hf, Zr, Ti, B, or P.
In the present embodiment, each of the above-described configurations and modification examples may be used in combination. For example, as described above, when the interface dipole layer 63 containing AlOx is provided between the block insulating layer 54 and the first charge storage layer 68a, the anti-oxidation layer 65 containing SiCN or SiOCN may be provided between the first charge storage layer 68a and the dielectric layer 68b, and in this case, the dielectric layer 68b may contain AlOx. It is considered that, by combining these configurations, for example, the above-described write characteristics and/or erase characteristics can be further improved.
Next, a manufacturing method of the semiconductor device 10 according to the present embodiment will be described with reference to
As shown in
Next, as shown in
Subsequently, as shown in
Next, the charge storage layer 68 is formed on the inner surface side of the cover insulating film 54. As shown in
For example, when Al is added as an additive, a gas containing AlCl3 may be used as the gas containing an additive, or a gas containing trimethylaluminium (TMA, CH3Al) may be used. In addition, for example, when Mo is added as an additive, a MoNx gas may be used, and MoNx may be formed of, for example, MoCl5, NH3, and Zn. For example, when Nb is added as an additive, a gas of NbOxNy may be used, and NbOxNy may be formed by, for example, NbCl5+H2O+NH3. For example, when Nb is added as an additive, tetrakis(ethylmethylamino) hafnium (TEMAH, [(CH3) (C2H5)N]4Hf) may be used. In addition, for example, when Zr is added as an additive, a gas of zirconium acetate (Zac (Zirconium Acetate), C8H12O8Zr) may be used. In addition, for example, when Ti is added as an additive, a gas of tetrakis(dimethylamino) titanium (TDMAT, Ti[N(CH3)]2]4) may be used. In addition, for example, when B is added as an additive, boron trichloride (BCl3) gas may be used. In addition, for example, when P is added as an additive, a gas of hydrogen phosphide (PH3) may be used.
Next, as shown in
Next, as shown in
As described above, the charge storage layer 68 is formed by forming the first charge storage layer 68a, the dielectric layer 68b, and the second charge storage layer 68c.
Subsequently, as shown in
Next, after forming a groove (not shown) in the stack 50, the sacrificial layer 55 is removed using the groove. The groove may be formed in the depth direction (Z-axis direction) to reach the substrate 40 by, for example, RIE. The sacrificial layer 55 may be removed by wet etching through a groove using a chemical solution such as phosphoric acid. As a result, as shown in
Next, the first block insulating film 53 and the barrier metal film 56 are formed in this order on the surface of the insulator layer 51 in the Z-axis direction and the surface of the second block insulating film 54 in the Y direction. As a result, as shown in
Subsequently, as shown in
As described above, the semiconductor device 10 of the present embodiment is formed.
A semiconductor device including:
The semiconductor device according to appendix 1, in which
The semiconductor device according to appendix 1, further including:
The semiconductor device according to appendix 3, in which
The semiconductor device according to appendix 1, further including:
The semiconductor device according to appendix 5, in which
The semiconductor device according to appendix 1, in which
The semiconductor device according to appendix 1, in which
The semiconductor device according to appendix 2, in which
The semiconductor device according to appendix 3, further including:
The semiconductor device according to appendix 1, in which
A semiconductor device including:
A manufacturing method of a semiconductor device, the method including:
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-045519 | Mar 2023 | JP | national |
