This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-257750, filed Sep. 22, 2006, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly a semiconductor device manufactured by using a phase shift mask to control current characteristics and a manufacturing method thereof.
2. Description of the Related Art
As miniaturization of a semiconductor device advances, it is becoming difficult to suppress a variation in feature sizes. In particular, a variation in a patterned gate electrode size of a metal-insulator-semiconductor field-effect transistor (MISFET) is one of the causes of a variation in electrical characteristics, e.g., a current driving force of the MISFET. In order to suppress this variation, improvement in, e.g., a resolution and/or depth of focus (DOF) of lithography, is demanded.
One of methods of improving performance of lithography is a method of using a phase shift mask, e.g., a Levenson mask (an alternating-phase shift mask). In the Levenson mask, usually, a phase of light transmitted through a pair of opening portions adjacent to each other is shifted 180°, namely, a phase is inverted each other, to improve a critical resolution or a depth of focus. The phase inverted pattern arrangement is called a Levenson arrangement, in which the phases are expressed by using 0 and π.
However, in an actual pattern of the Levenson mask used in manufacturing a semiconductor device, patterns adjacent to each other do not have a desired Levenson arrangement, e.g., an arrangement of 0, π, 0, π, but has an arrangement of an inversed phase, i.e., π, 0, π, 0, . . . , in some cases. Jpn. Pat. Appln. KOKAI Publication No. 2000-77531 discloses a semiconductor device, which has both patterns of isolated patterns and line-and-space patterns, manufactured by using a mask pattern having the Levenson arrangement. In this technology, a pair of the two patterns is determined as one active region, and the active regions adjacent to each other are arranged in staggered manner, thereby realizing a mask pattern of the Levenson arrangement.
When using the Levenson mask in gate electrode patterning, it is general to invert a phase of light to 0 and π or to π and 0 on a source side and a drain side of a gate electrode.
Although the Levenson mask improves a resolution and DOF of lithography, slight variation in a light transmittance of a 0 region and a π region of the mask is caused by a phase shifting processing of the mask. Therefore, the Levenson mask patterns depicted in
According to one aspect of the present invention, there is provided a semiconductor device comprising: a first transistor including a first gate electrode provided above a semiconductor substrate, and a first source and a first drain provided in the semiconductor substrate; a second transistor arranged to be adjacent to the first transistor, and including a second gate electrode provided above the semiconductor substrate in parallel with the first gate electrode, and a second source and a second drain provided in the semiconductor substrate; and a third gate electrode provided between the first transistor and the second transistor and in parallel with the first and second gate electrodes.
According to another aspect of the present invention, there is provided a manufacturing method of a semiconductor device, comprising: forming a gate insulator on a semiconductor substrate; forming a conductor film on the gate insulator; forming a resist film on the conductor film; patterning the resist film with a pattern of gate electrodes including a first gate electrode of a first MISFET, a second gate electrode of a second MISFET, and a third gate electrode disposed between the first and second gate electrodes by using a phase shift mask having a pattern arrangement in which source regions and drain regions of the adjacent first and second MISFETs are disposed alternately and sequentially, the third electrode being disposed between a drain of the first MISFET and a source of the second MISFET; patterning the conductor film to form the first, second and third gate electrodes by using the patterned resist film as a mask; and forming source diffusion layers and drain diffusion layers of the first and second MISFETs in the semiconductor substrate by using the first, second and third gate electrodes as masks.
According to another aspect of the present invention, there is provided a manufacturing method of a semiconductor device, comprising: forming a gate insulator on a semiconductor substrate; forming a conductor film on the gate insulator; forming a resist film on the conductor film; patterning the resist film with a pattern of gate electrodes including a first gate electrode of a first MISFET, a second gate electrode of a second MISFET, and a third gate electrode disposed between the first and second gate electrodes by using a phase shift mask having a pattern arrangement in which the source regions, the gate electrode regions, and the drain regions of the first and second MISFETs are symmetrically arranged each other, respectively, with a third gate electrode region at the center; patterning the conductor film to form the first, second and third gate electrodes by using the patterned resist film as a mask; forming source diffusion layers and drain diffusion layers of the first and second MISFETs in the semiconductor substrate by using the first, second and third gate electrodes as masks; and forming interconnects respectively connecting the source diffusion layers, the drain diffusion layers, and the gate electrodes of the two symmetrically arranged MISFETs each other in parallel.
Embodiments according to the present invention disclose semiconductor devices whose current characteristics can be prevented from varying even if a phase shift mask, e.g., a Levenson mask, is used for patterning gate electrodes of MISFETs, and a manufacturing method thereof.
The embodiments of the present invention will be described with reference to the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention, and together with the general description given above and the detailed description of the embodiments given below, serve to explain principles of the invention. Throughout the drawings, corresponding portions are denoted by corresponding reference numerals. The embodiments are only examples, and various changes and modifications can be made without departing from the scope and spirit.
According to a first embodiment of the present invention, a third gate electrode (a dummy gate electrode) is provided between gate electrodes of a pair of MISFETs adjacent to each other and in parallel with these gate electrodes. As a result, a phase shift mask, e.g., a Levenson mask, which is used to manufacture the gate electrodes of the pair of MISFETs allows source regions or drain regions of the two MISFETs to be patterned to have the same phase. There is provided a semiconductor device in which a variation in current characteristic between the pair of MISFETs is suppressed based on this technology and a manufacturing method thereof.
As described above, an example where gate electrodes of the MISFET are patterned by using such a Levenson mask as depicted in
In a circuit in which matching of characteristics of two or more MISFETs is critical, e.g., a differential amplifier, the above-explained variation in current characteristics of the MISFETs considerably degrade characteristics of the circuit.
When the gate electrodes, the sources, and the drains are arranged in this manner, a mask with a Levenson arrangement having matched phases of the source regions and the drain regions can be formed even if a Levenson mask for patterning the gate electrodes is automatically generated. That is, two source regions Sml and Sm2 are generated to have the same phase on the mask uniquely. Likewise, two drain regions Dm1 and Dm2 can uniquely have the same phase which is opposite to the phase of the source regions.
Therefore, according to this embodiment, in the two MISFETs, the source regions or the drain regions can uniquely have the same Levenson mask phase. As a result, the source-drain current in each of the two MISFETs Tr1 and Tr2 is uniquely controlled in a direction from the 0 region to the π region or a direction from the π region to the 0 region of the Levenson mask. Accordingly, it is possible to provide a semiconductor device in which a variation in current driving characteristics of the MISFETs caused by distortion to the gate electrode pattern due to a difference in light transmittance between the 0 region and the π region in the Levenson mask is avoided.
An example of a manufacturing method of a semiconductor device according to this embodiment will now be explained with reference to cross-sectional views of
Before forming each gate electrode, although not shown in
Referring also to
In step S108, a first resist film (not shown) is formed on the mask insulator 26. Then, a pattern of each gate electrode G is formed on the first resist film by lithography using a Levenson mask having a Levenson arrangement in which source regions and drain regions are alternately arranged as depicted in
Although not shown in
In step S112, the mask insulator 26 is used as a mask, and etching is carried out by, e.g., RIE, thereby forming the gate electrodes G, the interconnects, and others on the conductor film 24. In this manner, the structure depicted in
Thereafter, the mask insulator 26 is removed by, e.g., wet etching. The gate electrodes G are used as a mask to introduce a dopant, e.g., arsenic (As), into the silicon substrate 10 by, e.g., ion implantation, thereby forming a first diffusion layer 34 of the source/drain (step S114). An insulator 36, e.g., an Si3N4 film is deposited to cover the entire surface, and etching back of the insulator 36 is carried out by RIE to form a sidewall insulator 36 on a side surface of each gate electrode G (step S116). Moreover, the gate electrodes G and the sidewall insulator 36 are used as a mask to ion-implant a dopant, e.g., arsenic (As), thereby forming a second diffusion layer 38 of the source/drain (step S118). The second diffusion layer 38 has a concentration higher than that of the first diffusion layer 34 and also has a deeper junction depth.
In this manner, the structure of the MISFET according to this embodiment depicted in
Then, a semiconductor device according to this embodiment is brought to completion through steps required for the semiconductor device, e.g., multilevel interconnections.
In the thus formed two MISFETs Tr1 and Tr2 adjacent to each other, a source 38-S1, a drain 38-D1, a source 38-S2, and a drain 38-D2 of Tr1 and Tr2 are sequentially arranged. In other words, the sources 38-S1 and 38-S2 or the drains 38-D1 and 38-D2 are formed with the same Levenson mask phase. As a result, the two MISFETs Tr1 and Tr2 have the same current driving force, thereby realizing matching.
Although the manufacturing method of using the hard mask to pattern the gate electrodes has been explained in this embodiment, a modification can be carried out to use a resist mask for manufacture like a second embodiment which will be explained next.
Therefore, according to the embodiment, there is provided a semiconductor device in which a variation in current driving characteristics of the MISFETs caused by distortion in the gate electrode shape due to a difference in transmittance between the 0 region and the π region of the phase shift mask, e.g., a Levenson mask, is avoided, and a manufacturing method thereof.
According to the second embodiment of the present invention, a dummy gate electrode is arranged at a center of a cell constituted of a pair of MISFETs, and sources and drains of the pair of MISFETs are symmetrically arranged with the dummy gate electrode as a symmetric axis. The pair of MISFETs are electrically connected in parallel, thereby providing a semiconductor device in which a variation in current characteristics among a plurality of the pairs of MISFETs is suppressed and a manufacturing method thereof.
Each of
Such a pair of MISFETs can be used for, e.g., an input element of a flip-flop in an inverter circuit which requires a large current driving force.
An example of a manufacturing method of a semiconductor device based on this embodiment will now be explained with reference to a cross-sectional view of
Since a first step S202 to a step of depositing a conductor film 24 shown in step S204 in
In step S208, a first resist film (not shown) is formed on the conductor film 24. Then, a Levenson mask having a Levenson arrangement as shown in
In step S210, the first resist film is used as a mask to etch the conductor film 24 by, e.g., RIE, thereby forming the gate electrodes G on the conductor film 24. The gate electrodes G having an arrangement where the third gate electrode G3 is arranged between gate electrodes G1 and G2 of the two MISFETs are formed in this manner. Then, the first resist film is removed.
Although not shown in
In step S214, the second resist film is used as a mask to etch the conductor film 24 by, e.g., RIE, thereby forming the first interconnects, the contact pads of the gate electrodes, and others on the conductor film 24. In the etching, the gate electrodes G are not etched since they are covered with the second resist film. Then, the second resist film is removed.
In step S216, first and second diffusion layers 34 and 38 serving as sources/drains are formed in the semiconductor substrate 10 and a sidewall insulator 36 on side surfaces of the gate electrodes G are formed through processes, for example, from steps S114 to S118 according to the first embodiment.
In step S218, an interlevel insulator 40 is formed on the entire surface to cover the gate electrodes G, and the surface is planarized by, e.g., chemical mechanical polishing (CMP). In step S220, contact plugs 42 connected with the sources, the drains, and the first and second gate electrodes are formed in the interlevel insulator 40.
In step S222, second interconnects 44 connected with the contact plugs 42 is formed on the interlevel insulator 40. The second interconnects 44 are formed to electrically connect the sources 38-S1 and 38-S2 with each other, the gate electrodes G1 and G2 with each other, and the drains 38-D1 and 38-D2 with each other, these members being symmetrically arranged with the third gate electrode G3 at the center as described above.
The MISFETs in the semiconductor device according to this embodiment depicted in
Thereafter, the semiconductor device according to this embodiment is brought to completion through processes required for the semiconductor device, e.g., formation of multilevel interconnects.
In the thus formed two MISFETs Tr1 and Tr2 connected with each other in parallel, a drain 38-D1 and source 38-S1 of Tr1 and a source 38-S2 and drain 38-D2 of Tr2 are symmetrically arranged in the mentioned order with the third gate electrode G3 at the center, for example. In other words, the sources 38-S1 and 38-S2 or the drains 38-D1 and 38-D2 are formed with opposed phases in the Levenson mask. Therefore, in regard to current flow directions from the sources to the drains of the pair of MISFETs according to this embodiment, one is from the 0 region toward the π region in the Levenson mask, and the other is from the π region toward the 0 region. As a result, a sum of current driving forces of the pair of MISFETs connected with each other in parallel is to be constant, and a plurality of pairs of such MISFETs have the same current driving forces.
Although the sources are arranged on the inner side in the symmetrical arrangement in this embodiment, the drains may be arranged on the inner side. Further, although the manufacturing method of using the resist mask to pattern the gate electrodes has been explained, a modification may be made to use the hard mask for the manufacturing like the first embodiment.
As explained above, according to the embodiments of the present invention, there is provided a semiconductor device in which a variation in current driving characteristics in the MISFETs due to distortion to the gate electrode pattern caused by a difference in transmittance between the 0 region and the π region in a phase shift mask, e.g., a Levenson mask, is avoided and a manufacturing method thereof.
(Modification)
In the semiconductor device according to the second embodiment, the sources S1 and S2 formed to interpose the third gate electrode therebetween are electrically connected with each other to operate. Therefore, for example, the sources of the two MISFETs can be formed in one diffusion layer, and thus the semiconductor device can be modified to remove the third gate electrode G3 after patterning the gate electrodes G, for example.
Then, like in the step S212 depicted in
Then, like the second embodiment, first and second diffusion layers 34 and 38 serving as a source and drains are formed in the semiconductor substrate 10, and a sidewall insulator 36 is formed on an each side surface of gate electrodes G. Moreover, an interlevel insulator 40 which covers each gate electrode G is formed, and contact plugs 42 are formed in the interlevel insulator 40. Since the source 38S is shared by the two MISFETs Tr1 and Tr2, the two contact plugs 42 on the source 38S as depicted in
In this manner, the MISFETs of the semiconductor device according to this modification depicted in
As explained above, according to this modification, the source region can be formed to be small when patterning each gate electrode G. Additionally, according to this modification, one source can be shared by the two MISFETs and the number of the contact plug with respect to the source is one, thereby providing the structure advantageous in miniaturization. Further, like the second embodiment, the gate electrodes G are formed by using the Levenson mask having the Levenson arrangement. Therefore, it is possible to avoid a variation in current driving characteristics in the MISFETs due to distortion to the gate electrode pattern caused by a difference in transmittance between the 0 region and the π region in the Levenson mask.
As explained above, according to the embodiments of the present invention, when using a phase shift mask, e.g., the Levenson mask, to pattern the gate electrodes of the MISFETs, the Levenson arrangement can be automatically provided to the source regions and the drain regions of the MISFETs adjacent to each other. Accordingly, there is provided a semiconductor device in which a variation in current driving characteristics of the MISFETs due to distortion to the gate electrode pattern can be suppressed, and a manufacturing method thereof.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
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2006-257750 | Sep 2006 | JP | national |
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Number | Date | Country |
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Number | Date | Country | |
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20080073728 A1 | Mar 2008 | US |