The present invention relates to a memory access device.
Scaling dimensions of phase change random access memory (PCRAM) and resistive random access memory (RRAM) to achieve dense cross-point memory requires development of a selector device with a small footprint. Typically, transistors have a larger footprint and limit the memory density achievable. Two-terminal access devices are more suitable selectors for scaled memory technology.
Large cross-point memory arrays typically require large amount of the selectors. Threshold voltages of selectors can be tuned by tuning the thickness of the selector layer. However, a decrease in thickness of the selector layer can cause an increase of device leakage current (IOFF) which, in turn, can increase power consumption of the memory array.
According to some embodiments of the disclosure, a semiconductor device includes a first electrode, a second electrode, and an In-doped chalcogenide-based selector layer disposed between the first electrode and the second electrode, in which the In-doped chalcogenide-based selector layer includes indium (In) in a range of about or equal to 2 at. % to about or equal to 10 at. %.
According to some embodiments of the disclosure, a memory cell, includes an access device and a phase change material disposed on the access device. The access device includes a first electrode, a second electrode, and an In-doped chalcogenide-based selector layer disposed between the first electrode and the second electrode, in which the In-doped chalcogenide-based selector layer includes indium (In) in a range of about or equal to 2 at. % to about or equal to 10 at. %.
The In-doped chalcogenide-based selector layer can improve the material stability, adhesion, and variability during the fabrication. Therefore, the semiconductor device using the In-doped chalcogenide-based selector layer may have improved yield and show less cycling degradation.
It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
As used herein, “around”, “about” or “approximately” shall generally mean within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range.
Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top”, may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower”, can therefore, encompasses both an orientation of “lower” and “upper”, depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.
The selector 100 includes an In-doped chalcogenide-based selector layer 130 sandwiched between the first electrode 110 and the second electrode 120. Example chalcogenide materials of the In-doped chalcogenide-based selector layer 130 include Arsenic (As), Germanium (Ge), Selenium (Se), and Indium (In), e.g. the In-doped chalcogenide-based selector layer 130 is an In-doped AsSeGe layer. In some embodiments, the In-doped chalcogenide-based selector layer 130 includes indium (In) (i.e., has an In compound content) in a range of about or equal to 2 at. % to about or equal to 10 at. %. If In doping amount of the In-doped chalcogenide-based selector layer 130 is too high, the leakage current (IOFF) becomes bad, and the threshold voltage (Vth) decreases accordingly.
In some embodiments, the In-doped chalcogenide-based selector layer 130 includes In in a range of about or equal to 2 at. % to about or equal to 10 at. %, As in a range of about or equal to 25 at. % to about or equal to 38 at. %, a Ge in a range of about or equal to 8 at. % to about or equal to 20 at. %, and Se in a range of about or equal to 30 at. % to about or equal to 60 at. %. More particularly, the In-doped chalcogenide-based selector layer 130 includes In in a range of 2 at. % to 10 at. %, As in a range of 25 at. % to 38 at. %, a Ge in a range of 8 at. % to 20 at. %, and Se in a range of 30 at. % to 60 at. %.
In some embodiments, the selector 100 further includes two etching stop layers 140, 142 disposed between the first electrode 110 and the In-doped chalcogenide-based selector layer 130 and between the In-doped chalcogenide-based selector layer 130 and the second electrode 120, respectively. In some embodiments, the etching stop layers 140, 142 can be carbon layers or silicon doped with carbon (Si:C) layers.
The In-doped chalcogenide-based selector layer 130 can improve the material stability, adhesion, and variability during the fabrication. Therefore, the selectors 100 using the In-doped chalcogenide-based selector layer 130 may have improved yield and show less cycling degradation. As discussed above, the In-doped chalcogenide-based selector layer 130 has the In compound content of about or equal to or equal to 2 at. % to about or equal to 10 at. %. If In doping amount of the In-doped chalcogenide-based selector layer 130 is too low, the improvement is not obvious. In some embodiments, the thickness of the In-doped chalcogenide-based selector layer 130 is about 15 nm to about 45 nm. The selector 100 that having the In-doped chalcogenide-based selector layer 130 having such thickness is still able to provide high threshold voltage and low IOFF of selectors 100 for a high density 3D cross-point array technology.
For example, in an example selector 100 that having the In-doped chalcogenide-based selector layer 130 with a thickness of about 30 nm, the threshold voltage of the selector 100 is about 3.7V, the IOFF is about 700 pA at 2V. This example selector 100 can be turned on at 10 ns, which is a very fast response speed.
An embodiment of the In-doped chalcogenide-based selector layer 130 has a thickness and concentrations of In, As, Ge and Se in amounts sufficient to have a IOFF less than 1 nA at 2V. An embodiment of the In-doped chalcogenide-based selector layer 130 has a thickness and concentrations of In, As, Ge and Se in amounts sufficient to have a IOFF less than 1 nA at 2V, and a threshold voltage greater than 3V. An embodiment of the In-doped chalcogenide-based selector layer 130 has a thickness and concentrations of In, As, Ge and Se in amounts sufficient to have an endurance of greater than 1010 cycles.
Reference is now made to
As shown in
In some embodiments, the dielectric layer 102 can be formed on the top surface of access circuitry. Then a photoresist layer is then deposited and patterned on the dielectric layer 102 by using photolithographic techniques so as to form a patterned photoresist layer overlying the location of the first electrode 110. Then the dielectric layer 102 is etched using the patterned photoresist layer as the mask, thereby forming a via in the dielectric layer 102. After the patterned photoresist layer is removed, a conductive material, such as W or TiN, is then filled in the via. A planarizing process is then performed to remove the portion of the conductive material exceeding the dielectric layer 102, thereby obtaining the first electrode 110 embedded in the dielectric layer 102.
Reference is made to
The dielectric layer 104 is patterned to form an opening O1 over the first electrode 110. The step of patterning the dielectric layer 104 includes forming a patterned photoresist layer on the layer of dielectric layer 104, and then etching dielectric layer 104 by using the patterned photoresist layer as the mask, and the etching process is stop at reaching the etching stop layer 140. In some embodiments, the portion of the etching stop layer 140 uncovered by the patterned photoresist layer may be entirely consumed to expose the underlying first electrode 110. In some other embodiments, the portion of the etching stop layer 140 uncovered by the patterned photoresist layer may remain on the dielectric layer 102. The patterned photoresist layer is then removed.
Reference is made to
During the sputter process, the target is biased relative to a grounded region of the processing chamber by a power source disposed in the RF source and the direct current (DC) source. During the sputter processing, a gas is supplied to the processing chamber from a gas source via conduits. The gas source may include a non-reactive gas such as argon, krypton, helium or xenon, which is capable of energetically impinging upon and sputtering material from the target. A plasma is formed between the substrate and the target from the gas. Ions within the plasma are accelerated toward the target and cause material to become dislodged from the target. The dislodged target material is deposited on the substrate, thereby forming the layer of In-doped chalcogenide-based material 130′.
In some embodiments, the composition of the target is identical or similar to that of the layer of In-doped chalcogenide-based material 130′. In some embodiments, the materials of the target include Arsenic (As), Germanium (Ge), Selenium (Se), and Indium (In). In some embodiments, the target includes In in a range of about or equal to 2 at. % to about or equal to 10 at. %, As in a range of about or equal to 25 at. % to about or equal to 38 at. %, Ge in a range of about or equal to 8 at. % to about or equal to 20 at. %, and Se in a range of about or equal to 30 at. % to about or equal to 60 at. %.
After the layer of In-doped chalcogenide-based material 130′ is deposited and filling the opening O1, a planarizing process is then performed to remove the portion of the In-doped chalcogenide-based material 130′ exceeding the dielectric layer 104, thereby obtaining the In-doped chalcogenide-based selector layer 130 embedded in the dielectric layer 104. In some embodiments, the thickness of the In-doped chalcogenide-based selector layer 130 is about 15 nm to about 45 nm.
Reference is made to
After the patterned photoresist layer is removed, a conductive material, such as W or TiN, is then filled in the opening O2. A planarizing process is then performed to remove the portion of the conductive material exceeding the dielectric layer 106, thereby obtaining the second electrode 120 embedded in the dielectric layer 106 and on the In-doped chalcogenide-based selector layer 130.
In some embodiments, the width of the In-doped chalcogenide-based selector layer 130 and the width of the second electrode 120 are substantially the same, and the width of the first electrode 110 is smaller than the width of the In-doped chalcogenide-based selector layer 130 and the second electrode 120 thereon. In some other embodiments, the widths of the first electrode 110, the In-doped chalcogenide-based selector layer 130, and the second electrode 120 are substantially the same.
Each memory cell 300 in the array includes an access device 310 and a memory layer 350, and the access device 310 and the memory layer 350 are in form of a pillar, which can be prism-like or cylinder-like. Bit lines BLs, which are conductive lines, are connected to first and second groups of memory cells 300 on the upper and lower levels of the 3D stack, and word lines WLs, which are conductive lines, running perpendicular to the bit lines BLs, are connected first groups of memory cells in the top layer, and to second groups of memory cells 300 in the bottom layer. The access device 310 includes the In-doped chalcogenide-based selector layer which comprise an ovonic threshold switch. In some embodiments, the In-doped chalcogenide-based selector layer includes In in a range of about or equal to 2 at. % to about or equal to 10 at. %. If In doping amount of the In-doped chalcogenide-based selector layer is too high, the leakage current becomes bad, and the threshold voltage decreases accordingly. In some embodiments, the In-doped chalcogenide-based selector layer includes In in a range of about or equal to 2 at. % to about or equal to 10 at. %, As in a range of about or equal to 25 at. % to about or equal to 38 at. %, Ge in a range of about or equal to 8 at. % to about or equal to 20 at. %, and Se in a range of about or equal to 30 at. % to about or equal to 60 at. %.
The memory layer 350 can comprise a layer of programmable resistance material. In one example, the memory layer 350 comprises a phase change memory material 454. In some embodiments, other programmable resistance memory elements can be implemented, such as metal-oxide resistive memories, magnetic resistive memories and conducting-bridge resistive memories, or other types of memory devices.
Embodiments of materials for the memory layer 350 can include chalcogenide-based materials and other materials. A chalcogenide-based material suitable for use as a memory element can contain one or more elements from group IVA of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be for example dielectric doped Ge2Sb2Te5, GeSb2Te4 and GeSb4Te7. In some embodiments, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te or Ga/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are disclosed in Ovshinsky, U.S. Pat. No. 5,687,112 at columns 11-13, which examples are incorporated by reference.
The memory layer 350 can comprise a layer of chalcogenide alloy with additives to modify conductivity, transition temperature, melting temperature, and other properties. Representative additives can include nitrogen (N), silicon (Si), oxygen (O), silicon dioxide (SiOx), silicon nitride (SiN), copper (Cu), silver (Ag), gold (Au), aluminum (Al), aluminum oxide (Al2O3), tantalum (Ta), tantalum oxide (TaOx), tantalum nitride (TaN), titanium (Ti), and titanium oxide (TiOx).
In some embodiments, the memory cells 300 may be vertically stacked in a three-dimensional memory array. A dielectric layer is formed surrounding the memory cells 300. In some embodiments, one memory cell 300 may be vertically stacked above another memory cell 300 and are spaced apart from each other by the dielectric layer. In some embodiments, etching stop layers 320 are interposed between the access device 310 and the memory layer 350, and between the conductive lines, e.g. the word lines WL or the bit lines BL, and the memory layer 350 and the access device 310. The etching stop layers 320 can be layers that include carbon or silicon doped with carbon (Si:C).
Thus, array of memory cells 300 is disclosed, in which each of the memory cells 300 includes a one-selector one-resistor (1S1R) semiconductor structure. The memory cells 300 of one-selector one-resistor structure allow high density and monolithic 3D integration. Additionally, by introducing the In-doped chalcogenide-based selector layer into the access device 310, the memory cells 300 may have high threshold voltage, low IOFF, and high endurance performance for high density 3D cross point technology. For example, the threshold voltage for switching on the ovonic threshold switch can be greater than 3V for a device using In-doped chalcogenide-based selector layer with 30 nm thickness, IOFF can be less than 1 nA with a voltage across the ovonic threshold switch of about 2V, the endurance can be greater than 1E10 cycles. The In-doped chalcogenide-based selector layer can improve the material stability, adhesion, and variability during the fabrication, thus cell to cell variation becomes small, yield is improved, and cycle to cycle degradation becomes less.
Reference is made to
Each of the word line WL extends along a first direction and connects the second group of memory cells 400 in parallel. The word line WL also serves as a first electrode 412 of each of the access device 410. An In-doped chalcogenide-based selector layer 414 is formed on the first electrode 412 of each of the access device 410. The In-doped chalcogenide-based selector layer 414 includes chalcogenide materials, such as Arsenic (As), Germanium (Ge), Selenium (Se), and Indium (In). In some embodiments, In-doped chalcogenide-based selector layer 414 is In-doped AsSeGe layer. In some embodiments, the In-doped chalcogenide-based selector layer 414 includes In in a range of about or equal to 2 at. % to about or equal to 10 at. %. If In doping amount of the In-doped chalcogenide-based selector layer 414 is too high, the IOFF becomes bad, and the threshold voltage decreases accordingly.
In some embodiments, the In-doped chalcogenide-based selector layer 414 includes In in a range of about or equal to 2 at. % to about or equal to 10 at. %, As in a range of about or equal to 25 at. % to about or equal to 38 at. %, Ge in a range of about or equal to 8 at. % to about or equal to 20 at. %, and Se in a range of about or equal to 30 at. % to about or equal to 60 at. %. In some embodiments, the thickness of the In-doped chalcogenide-based selector layer 414 is about 15 nm to about 45 nm.
A second electrode 416 is formed on the In-doped chalcogenide-based selector layer 414. The first electrode 412 and the second electrode 416 include conductive material such as W or TiN. In some embodiments, the In-doped chalcogenide-based selector layer 414 is physically and electrically in contact with the first electrode 412 and the second electrode 416. In some other embodiments, additional layers, such as etching stop layers, thermal layers, work function layers, or other suitable layers can be interposed between the first electrode 412, the In-doped chalcogenide-based selector layer 414, and the second electrode 416. The steps of manufacturing of the access device 410 are similar to that as discussed in
The second electrode 416 also serves as a bottom electrode of the memory layer 450. The memory layer 450 is electrically coupled to the access device 410 and is programmable to at least two resistive states. In some embodiments, the memory layer 450 includes a phase change material (PCM) 454 or other memory material. The memory layer 450 is electrically connected to the second electrode 416. The phase change material 454 may be a material programmable to either a first phase having a first electrical resistance or a second phase having a second electrical resistance, where the first electrical resistance is greater than the second electrical resistance.
In some embodiments, the array of memory cells 400 is a multi-bit memory array. Thus, the phase change material 454 or other memory material is programmed to one of at least three resistance levels. Also, other programmable resistance memory materials can be used as discussed above.
Each bit line BL extends along a second direction and connects the first group of memory cells 400 in parallel. The top electrode 456 of the memory 450 is disposed on the phase change material 454, or other memory material, and is connected to the bit line BL.
In some embodiments, etching stop layers 420 are interposed between the word line WL (the first electrode 412) and the In-doped chalcogenide-based selector layer 414, and between the selector layer 414 and the second electrode 416. Also, etching stop layer 420 are interposed between the second electrode and the phase change material 454. Also, etching stop layers 420 are interposed between the phase change material 454, and the top electrode 456. The etching stop layers 420 can be layers that include carbon or silicon doped with carbon (Si:C).
The access device in this embodiment is an ovonic threshold switch including a first etching stop layer 512 (first electrode), an In-doped chalcogenide-based selector layer 514, and a second etching stop layer 516 (second electrode). The memory layer comprises a first barrier layer 518 on the second etching stop layer 516, a layer of memory material 520 such as a phase change material on the first barrier layer 518, a second barrier layer 522 on the layer of memory material 520, and a top etching stop layer 524 (top electrode) on the second barrier layer. The electrodes 512, 516, 524 can comprise a metal such as tungsten or titanium nitride as discussed above. The layer of memory material 520 can comprise a phase change memory material, or other materials, examples of which are described above.
The width (W1) orthogonal to the current flow direction, of the top etching stop layer 524 can be less than the width (W2) of bottom etching stop layer 512, in some embodiments.
A phase change memory material can be, for example, a layer of chalcogenide having a thickness of about 10 nm to about 50 nm, preferably about 30 nm to about 40 nm. Chalcogenides utilized as phase change memory elements are capable of being switched between a relatively low resistance state, amorphous phase, and a relatively high resistance state, crystalline phase, by application of energy such as heat or electrical current. In some embodiments, multilevel cells having multiple resistance states can be used.
The barrier layers can have thickness in a range from 2 nm to 10 nm. Example materials for the barrier layers 518, 522 can be a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon nitride (MoSiN), molybdenum aluminum nitride (WAlN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN). In addition to metal nitrides, the barrier layers can comprise materials such as carbon, doped polysilicon, tungsten (W), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium silicide (TiSi), tantalum silicide (TaSi), titanium tungsten (TiW), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), and tantalum oxynitride (TaON). In some embodiments, the preferred material for the barrier layers 518 and 522 is tungsten.
As in
The access device in this embodiment is an ovonic threshold switch including a first electrode 612, an In-doped chalcogenide-based selector layer 614, and a second electrode 616. The memory layer comprises a first barrier layer 618 on the second electrode 616, a layer of memory material 620 such as a phase change material on the first barrier layer 618, a second barrier layer 622 on the layer of memory material 620, and a top electrode 624 on the second barrier layer. The electrodes 612, 616, 624 can comprise a metal such as tungsten or titanium nitride as discussed above. The electrodes 612, 616, 624 can comprise amorphous carbon in some embodiments. The thickness of the electrodes 612, 616, 624 can be in a range from 10 nm to 20 nm. The layer of memory material 620 can comprise a phase change memory material, or other materials, examples of which are described above.
In some embodiments, the In-doped chalcogenide-based selector layer 614 is physically and electrically in contact with the first electrode 612 and the second electrode 616. In some other embodiments, additional layers, such as etching stop layers, thermal layers, work function layers, or other suitable layers can be interposed between the first electrode 612, the In-doped chalcogenide-based selector layer 614, and the second electrode 616.
The access device and the memory layer of the memory cell are in form of a cylinder-like or prism-like pillar. Bit lines BLs, which are conductive lines, are connected to first groups (columns) of memory cells, and word lines WLs, which are conductive lines, running perpendicular to the bit lines BLs, are connected to second groups (rows) of memory cells. The access device includes the In-doped chalcogenide-based selector layer.
As described above, in some embodiments, the In-doped chalcogenide-based selector layer includes In in a range of about or equal to 2 at. % to about or equal to 10 at. %. If In doping amount of the In-doped chalcogenide-based selector layer is too high, the leakage current becomes bad, and the threshold voltage may decrease. In some embodiments, the In-doped chalcogenide-based selector layer includes In in a range of about or equal to 2 at. % to about or equal to 10 at. %, As in a range of about or equal to 25 at. % to about or equal to 38 at. %, Ge in a range of about or equal to 8 at. % to about or equal to 20 at. %, and Se in a range of about or equal to 30 at. % to about or equal to 60 at. %.
In some embodiments, the thickness of the In-doped chalcogenide-based selector layer 614 is about 15 nm to about 45 nm.
The second electrode 616 and barrier layer 618 also serve as a bottom electrode of the memory cell 650. The memory layer 620 is electrically coupled to, and in electrical series with, the access device 610 and is programmable to at least two resistive states. In some embodiments, the memory layer 620 includes a phase change material (PCM) on the barrier layer 618. The phase change material may be a material programmable to either a first phase having a first electrical resistance or a second phase having a second electrical resistance, where the first electrical resistance is greater than the second electrical resistance.
Thus, an array of memory cells is disclosed, in which each of the memory cells includes a one-selector one-resistor (1S1R) structure. The memory cells of one-selector one-resistor structure allow high density and monolithic 3D integration. Additionally, by introducing the In-doped chalcogenide-based selector layer into the access device, the memory cells may have high threshold voltage, low IOFF, and high endurance performance for high density 3D cross point technology. For example, the threshold voltage of the memory cell can be greater than 3V for a device using In-doped chalcogenide-based selector layer with 30 nm thickness, IOFF can be less than 1 nA at 2V, the endurance can be greater than 1E10 cycles. The In-doped chalcogenide-based selector layer can improve the material stability, adhesion, and variability during the fabrication, thus cell to cell variation becomes small, yield is improved, and cycle to cycle degradation becomes less.
Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
This application is a continuation-in-part of U.S. patent application Ser. No. 16/601,647 filed 15 Oct. 2019 (now U.S. Pat. No. 10,978,511), which application is incorporated herein by reference.
Number | Name | Date | Kind |
---|---|---|---|
3271591 | Ovshinsky | Sep 1966 | A |
3343034 | Ovshinsky | Sep 1967 | A |
3530441 | Ovshinsky | Sep 1970 | A |
3571669 | Fleming | Mar 1971 | A |
3571670 | Ovshinsky | Mar 1971 | A |
3571671 | Ovshinsky | Mar 1971 | A |
3571672 | Ovshinsky | Mar 1971 | A |
3588638 | Fleming et al. | Jun 1971 | A |
3611063 | Neale | Oct 1971 | A |
3619732 | Neale | Nov 1971 | A |
3656032 | Henisch | Apr 1972 | A |
3846767 | Cohen | Nov 1974 | A |
3875566 | Helbers | Apr 1975 | A |
3886577 | Buckley | May 1975 | A |
3980505 | Buckley | Sep 1976 | A |
5159661 | Ovshinsky et al. | Oct 1992 | A |
5177567 | Klersy et al. | Jan 1993 | A |
5687112 | Ovshinsky | Nov 1997 | A |
6579760 | Lung | Jun 2003 | B1 |
6800504 | Li et al. | Oct 2004 | B2 |
6967344 | Ovshinsky et al. | Nov 2005 | B2 |
6995390 | Tsukui | Feb 2006 | B2 |
7483293 | Pinnow et al. | Jan 2009 | B2 |
7688619 | Lung | Mar 2010 | B2 |
7893419 | Hudgens et al. | Feb 2011 | B2 |
7902538 | Lung | Mar 2011 | B2 |
7903457 | Lung | Mar 2011 | B2 |
7929340 | Lung et al. | Apr 2011 | B2 |
8138028 | Lung et al. | Mar 2012 | B2 |
8148707 | Ovshinsky | Apr 2012 | B2 |
8178387 | Cheng et al. | May 2012 | B2 |
8315088 | Lung | Nov 2012 | B2 |
8324605 | Lung et al. | Dec 2012 | B2 |
8330137 | Schrott et al. | Dec 2012 | B2 |
8344348 | Wicker | Jan 2013 | B2 |
8363463 | Shih et al. | Jan 2013 | B2 |
8374019 | Wu et al. | Feb 2013 | B2 |
8410468 | Zheng | Apr 2013 | B2 |
8426242 | Cheng et al. | Apr 2013 | B2 |
8467236 | Campbell | Jun 2013 | B2 |
8634235 | Lung | Jan 2014 | B2 |
8646666 | May | Feb 2014 | B2 |
8772747 | Cheng et al. | Jul 2014 | B2 |
8916414 | Cheng et al. | Dec 2014 | B2 |
8932901 | Cheng | Jan 2015 | B2 |
8946666 | Cheng et al. | Feb 2015 | B2 |
9177640 | Shintani et al. | Nov 2015 | B2 |
9190609 | Zheng | Nov 2015 | B2 |
9214229 | Cheng et al. | Dec 2015 | B2 |
9336879 | Lung et al. | May 2016 | B2 |
9337421 | Chin et al. | May 2016 | B2 |
9659998 | Lung | May 2017 | B1 |
9917252 | Cheng et al. | Mar 2018 | B2 |
10050196 | Cheng et al. | Aug 2018 | B1 |
10157671 | Lung et al. | Dec 2018 | B1 |
10256406 | Collins et al. | Apr 2019 | B2 |
10374009 | Cheng et al. | Aug 2019 | B1 |
10541271 | Cheng et al. | Jan 2020 | B2 |
10593875 | Lai et al. | Mar 2020 | B2 |
10978511 | Cheng et al. | Apr 2021 | B1 |
11158787 | Cheng et al. | Oct 2021 | B2 |
20050018098 | Sugihara et al. | Jan 2005 | A1 |
20070171705 | Parkinson | Jul 2007 | A1 |
20080142777 | Park et al. | Jun 2008 | A1 |
20080253166 | Raberg et al. | Oct 2008 | A1 |
20080272807 | Lowrey | Nov 2008 | A1 |
20090014705 | Hsu et al. | Jan 2009 | A1 |
20090194759 | Chin et al. | Aug 2009 | A1 |
20090230375 | Liang et al. | Sep 2009 | A1 |
20100051895 | Hampton | Mar 2010 | A1 |
20100054029 | Happ et al. | Mar 2010 | A1 |
20100328996 | Shih et al. | Dec 2010 | A1 |
20110049456 | Lung et al. | Mar 2011 | A1 |
20110084240 | Schell et al. | Apr 2011 | A1 |
20110095257 | Xu et al. | Apr 2011 | A1 |
20110097825 | Cheng et al. | Apr 2011 | A1 |
20110180775 | Lin et al. | Jul 2011 | A1 |
20110207284 | Tominaga et al. | Aug 2011 | A1 |
20110317480 | Lung et al. | Dec 2011 | A1 |
20120025164 | Deweerd | Feb 2012 | A1 |
20120062267 | Saito | Mar 2012 | A1 |
20120181499 | Chuang et al. | Jul 2012 | A1 |
20120193595 | Cheng et al. | Aug 2012 | A1 |
20120326111 | Cheng et al. | Dec 2012 | A1 |
20130043375 | Baleine et al. | Feb 2013 | A1 |
20130105759 | Cheng | May 2013 | A1 |
20130234093 | Cheng et al. | Sep 2013 | A1 |
20130270505 | Dahmani | Oct 2013 | A1 |
20130277638 | Moradpour et al. | Oct 2013 | A1 |
20140101371 | Nguyen et al. | Apr 2014 | A1 |
20140264240 | Cheng et al. | Sep 2014 | A1 |
20140376307 | Shintani | Dec 2014 | A1 |
20140376309 | Cheng et al. | Dec 2014 | A1 |
20150048291 | Cheng et al. | Feb 2015 | A1 |
20160276022 | Redaelli | Sep 2016 | A1 |
20160336378 | Ohba et al. | Nov 2016 | A1 |
20160372188 | Lung et al. | Dec 2016 | A1 |
20160372661 | Cheng et al. | Dec 2016 | A1 |
20170076797 | Lung et al. | Mar 2017 | A1 |
20170244026 | Wu et al. | Aug 2017 | A1 |
20170250222 | Wu et al. | Aug 2017 | A1 |
20170263863 | Lung et al. | Sep 2017 | A1 |
20170271581 | Seong et al. | Sep 2017 | A1 |
20180012938 | Lung et al. | Jan 2018 | A1 |
20180019391 | Ohba et al. | Jan 2018 | A1 |
20180040669 | Wu | Feb 2018 | A1 |
20180277601 | Ahn et al. | Sep 2018 | A1 |
20190043924 | Conti et al. | Feb 2019 | A1 |
20190081103 | Fantini et al. | Mar 2019 | A1 |
20190115393 | Cheng et al. | Apr 2019 | A1 |
20190148456 | Wu et al. | May 2019 | A1 |
20190252609 | Sei et al. | Aug 2019 | A1 |
20190355790 | Lung et al. | Nov 2019 | A1 |
20190355903 | Lung et al. | Nov 2019 | A1 |
20190386213 | Lai et al. | Dec 2019 | A1 |
20190393268 | Lai et al. | Dec 2019 | A1 |
20200052036 | Ikarashi et al. | Feb 2020 | A1 |
20200227475 | Park et al. | Jul 2020 | A1 |
20200295083 | Cheng et al. | Sep 2020 | A1 |
20210111224 | Cheng et al. | Apr 2021 | A1 |
20210143216 | Lai et al. | May 2021 | A1 |
20210184112 | Cheng et al. | Jun 2021 | A1 |
20210210554 | Cheng et al. | Jul 2021 | A1 |
Number | Date | Country |
---|---|---|
1568494 | Jan 2005 | CN |
107210302 | Sep 2017 | CN |
201633507 | Sep 2016 | TW |
201700407 | Jan 2017 | TW |
201733177 | Sep 2017 | TW |
201801300 | Jan 2018 | TW |
201907543 | Feb 2019 | TW |
202006931 | Feb 2020 | TW |
202036850 | Oct 2020 | TW |
Entry |
---|
U.S. Office Action in U.S. Appl. No. 16/355,292 dated Jul. 27, 2021 (and supplement dated Jul. 28, 2021), 66 pages. |
Cheng et al., “An ultra high endurance and thermally stable selector based on TeAsGeSiSe chalcogenides compatible with BEOL IC Integration for cross-point PCM,” IEEE IEDM Dec. 2-6, 2017, 4 pages. |
Cheng et al., “Si Incorporation into AsSeGe Chalcogenides for High Thermal Stability, High Endurance and Extremely Low Vth Drift 3D Stackable Cross-Point Memory,” IEEE Symp. on VLSI Tech., Jun. 16-19, 2020, 2 pages. |
Cheng et al. , “Ultra-High Endurance and Low IOFF Selector based on AsSeGe Chalcogenides for Wide Memory Window 3D Stackable Crosspoint Memory,” IEEE IEDM Dec. 1-5, 2018, 4 pages. |
Guo et al., “A Review of Germanium-Antimony-Telluride Phase Change Materials for Non-Volatile Memories and Optical Modulators,” Appl. Sci. Feb. 4, 2019, 26 pages; www.mdpi.com/journal/applsci. |
Kao et al., “Antimony alloys for phase-change memory with high thermal stability,” Scripta Materialia vol. 63, issue 8, Oct. 2010, 855-858. |
Mark-Lapedus, “Embedded Phase-Change Memory Emerges,” https://semiengineering.com/author/mark-lapedus, Jan. 24, 2019, 13 pages. |
NIST Special Publication 800-38D, Dworkin, “Recommendation for Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC,” Nov. 2007, 39 pages. |
Ohyanagi et al., “Special Electrical Characteristics of Superlattice Phase Change Memory,” ECS Trans., vol. 58, Issue 5, Oct. 31, 2013, pp. 135-158. |
Ovshinsky, “New Transformative Possibilities for Ovonic Devices,” E*PCOS2010, European Symposium on Phase Change and Ovonic Science, Milan, Italy Sep. 6-7, 2010, 9 pages. |
Schuller, Ivan K., Stevens, Rick, Pino, Robinson, and Pechan, Michael. Neuromorphic Computing—From Materials Research to Systems Architecture Roundtable. “Report of a Roundtable Convened to Consider Neuromorphic Computing Basic Research Needs,” Oct. 29-30, 2015, 40 pages. |
Shanks, “Ovonic threshold switching characteristics,” Journal of Non-Crystalline Solids, vol. 2, Jan. 1970, pp. 504-514. |
Shin et al., “The effect of doping Sb on the electronic structure and the device characteristics of Ovonic Threshold Switches based on Ge—Se,” Scientific Reports, Nov. 18, 2014, 5 pages. |
Simpson et al., “Interfacial phase-change memory,” Nature Nanotechnology, vol. 6, Jul. 3, 2011, 502-505. |
Velea et al., “Te-based chalcogenide materials for selector applications,” Scientific Reports, 7:8103, Aug. 14, 2019, 12 pages. |
Wikipedia, “Rutherford backscattering spectrometry,” downloaded Aug. 4, 2020, available at https://en.wikipedia.org/wiki/Rutherford_backscattering_spectrometry, 8 pages. |
Wu et al., “A 40nm Low-Power Logic Compatible Phase Change Memory Technology,” IEEE IEDM 2018, Dec. 1-5, 2018, 4 pages. |
Chen, et al., “Endurance Improvement of Ge2Sb2Te5-Based Phase Change Memory,” IEEE Int'l MemoryWorkshop, 2009, May 10-14, 2009, 2 pages. |
Cheng et al., “A thermally robust phase change memory by engineering the Ge/N concentration in (Ge, N)xSbyTe z phase change materiaL” 2012 Int'l IEEE IEDM, Dec. 10-13, 2012, 4 pages. |
Cheng et al., “The Crystallization Behavior of Ga—Sb Materials as a Function of Composition for Phase Change Random Access Memory,” Phase Change and Ovonics Symposium, Sep. 2011, 7 pages. |
Cheng et al., Ga46Sb54 Material for Fast Switching and Pb-Free Soldering Reflow Process Complying Phase-Change Memory, ECS J. Solid State Sci. Technol. 2014 vol. 3, issue 7, Jun. 2014, p. 263-p. 267. |
Cheng, et al., “A high performance phase change memory with fast switching speed and high temperature retention by engineering the GexSbyTez phase change material,” 2011 IEEE Int'l IEDM, Dec. 5-7, 2011, 4 pages. |
Cheng, H.Y., et al., “Atomic-level engineering of phase change material for novel fast-switching and high-endurance PCM for storage class memory application,” IEEE Int'l Electron Devices Meeting (IEDM), Dec. 9-11, 2013, p. 30.6.1,30.6.4. |
Ciocchini, N., et al. “Unified reliability modeling of Ge-rich phase change memory for embedded applications” IEEE Int'l Electron Devices Meeting (IEDM), Dec. 9-11, 2013, p. 22.1.1,22.1.4. |
Kim, I.S., et al., “High performance PRAM cell scalable to sub-20nm technology with below 4F2 cell size, extendable to DRAM applications,” 2010 Symp. on VLSI Technology, Jun. 15-17, 2010, 2 pages. |
Lu et al., Ga14Sb86 film for ultralong data retention phase-change memory, J. Appl. Phys. 109, 064503, Jun. 2011, 4 pages. |
Morales-Sanchez et al., “Structural, electric and kinetic parameters of ternary alloys of GeSbTe,” Thin Solid Films, vol. 471, Issues 1-2, Jan. 3, 2005, pp. 243-247. |
Navarro, G., et al., “Trade-off between SET and data retention performance thanks to innovative materials for phase-change memory,” IEEE Int'l Electron Devices Meeting (IEDM), Dec. 9-11, 2013, p. 21.5.1,21.5.4. |
Putero et al., Unusual crystallization behavior in Ga—Sb phase change alloys, APL Mat. 1, Jun. 21, 2001, Dec. 2013, 7 pages. |
Raoux, et al. “Phase change materials and phase change memory,” MRS Bulletin, 39(8), 703-710. |
Shah et al., “GaSb—Ge pseudobinary phase diagram,” Journal of Electronic Materials, vol. 11, Issue 1, Jan. 1982, 53-58. |
U.S. Office Action in U.S. Appl. No. 17/205,767 dated Dec. 21, 2021, 11 pages. |
U.S. Office Action in U.S. Appl. No. 16/833,349 dated Oct. 6, 2021, 10 pages. |
Wimmer, et al., Role of activation energy in resistance drift of amorphous phase change materials, Frontiers in Physics, Dec. 2014, vol. 2, Article 75, pp. 1-12. |
Zuliani, P., et al., “Overcoming Temperature Limitations in Phase Change Memories With Optimized GexSbyTez,” IEEE Trans, on Electron Devices, 60(12), Dec. 2013, pp. 4020,4026. |
Number | Date | Country | |
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20210210554 A1 | Jul 2021 | US |
Number | Date | Country | |
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Parent | 16601647 | Oct 2019 | US |
Child | 17205767 | US |