BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A to 3C are step cross-sectional views schematically illustrating a method for fabricating a complementary MIS transistor according to a first embodiment of the present invention;
FIG. 4 is a cross-sectional view showing a complementary MIS transistor according to a variation of the first embodiment;
FIGS. 5A to 6C are step cross-sectional views schematically illustrating a method for fabricating a complementary semiconductor device according to a second embodiment of the present invention;
FIG. 7 is a cross-sectional view showing a complementary MIS transistor according to a variation of the second embodiment;
FIGS. 8A and 8B are step cross-sectional views illustrating a method for fabricating a conventional complementary MIS transistor; and
FIGS. 9A to 9D are cross-sectional views illustrating a method for fabricating another conventional complementary MIS transistor.