Patent Application
20250015168
An embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. In particular, an embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device in which an oxide semiconductor is used as a channel.
In recent years, a semiconductor device in which an oxide semiconductor is used for a channel instead of amorphous silicon, low-temperature polysilicon, and single-crystal silicon has been developed (for example, Japanese laid-open patent publication No. 2021-141338, Japanese laid-open patent publication No. 2014-099601, Japanese laid-open patent publication No. 2021-153196, Japanese laid-open patent publication No. 2018-006730, Japanese laid-open patent publication No. 2016-184771, and Japanese laid-open patent publication No. 2021-108405). The semiconductor device in which the oxide semiconductor is used for the channel can be formed with a simple structure and a low-temperature process, similar to a semiconductor device in which amorphous silicon is used as a channel. The semiconductor device in which the oxide semiconductor is used for the channel is known to have higher mobility than the semiconductor device in which amorphous silicon is used for the channel.
It is essential to supply oxygen to an oxide semiconductor layer in the manufacturing process and to reduce oxygen deficiencies formed in the oxide semiconductor layer in order for the semiconductor device in which the oxide semiconductor is used for the channel to perform a stable operation. For example, a technique of forming an insulating layer covering the oxide semiconductor layer under the condition that the insulating layer contains more oxygen is disclosed as one method of supplying oxygen to the oxide semiconductor layer.
A method for manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first metal oxide layer containing aluminium as a main component above an insulating surface, performing a planarization process on a surface of the first metal oxide layer, forming an oxide semiconductor layer on the insulating surface on which the planarization process was performed, forming a gate insulating layer above the oxide semiconductor layer, and forming a gate electrode facing the oxide semiconductor layer above the gate insulating layer.
A semiconductor device according to an embodiment of the present invention includes a metal oxide layer containing aluminium as a main component above an insulating surface, an oxide semiconductor layer on the metal oxide layer, a gate electrode facing the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein a relationship between an arithmetic mean roughness Ra (nm) of a surface of the metal oxide layer and a field effect mobility μ (cm2/Vs) is expressed by the following formula.
μ=−10.033Ra+48.23
(Where, the arithmetic mean roughness Ra≤0.80 nm)
The insulating layer formed with more oxygen-containing conditions contains more defects. As a result, abnormal characteristics of the semiconductor device or a variation in characteristics in a reliability test occur, which are considered to be caused by electrons becoming trapped in the defect. On the other hand, if an insulating layer with fewer defects is used, oxygen in the insulating layer cannot be increased. Therefore, sufficient oxygen cannot be supplied from the insulating layer to the oxide semiconductor layer. As described above, there is a demand for realizing a structure capable of repairing oxygen deficiencies formed in the oxide semiconductor layer while reducing defects in the insulating layer that cause the variation in characteristics of the semiconductor device.
Further, a semiconductor device with high mobility can be obtained by relatively increasing a ratio of indium contained in the oxide semiconductor layer. However, if the ratio of indium contained in the oxide semiconductor layer is high, oxygen deficiencies are likely to be formed in the oxide semiconductor layer. Therefore, in order to realize high mobility while maintaining high reliability, it is necessary to devise a configuration of the insulating layer around the oxide semiconductor layer.
An object of the embodiment of the present invention is to realize a highly reliable semiconductor device having high mobility.
Embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. A configuration that can be easily conceived by a person skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. For the sake of clarity of description, the drawings may be schematically represented with respect to widths, thicknesses, shapes, and the like of the respective portions in comparison with actual embodiments. However, the shape shown is merely an example and does not limit the interpretation of the present invention. In this specification and each of the drawings, the same symbols are assigned to the same components as those described previously with reference to the preceding drawings, and a detailed description thereof may be omitted as appropriate.
“Semiconductor device” refers to all devices that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are a form of semiconductor device. For example, a semiconductor device may be used in an integrated circuit (IC) such as a micro-processing unit (MPU) or a memory circuit in addition to a transistor used in a display device.
“Display device” refers to a structure configured to display an image using electro-optic layers. For example, the term display device may refer to a display panel including the electro-optic layer, or it may refer to a structure in which other optical members (e.g., polarizing member, backlight, touch panel, etc.) are attached to a display cell. The “electro-optic layer” can include a liquid crystal layer, an electroluminescence (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, as long as there is no technical contradiction. Therefore, although the embodiments described later will be described by exemplifying the liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as the display device, the structure in the present embodiment can be applied to a display device including the other electro-optic layers described above.
In the embodiments of the present invention, a direction from a substrate to an oxide semiconductor layer is referred to as “on” or “above”. Reversely, a direction from the oxide semiconductor layer to the substrate is referred to as “under” or “below”. As described above, for convenience of explanation, although the phrase “above (on)” or “below (under)” is used for explanation, for example, a vertical relationship between the substrate and the oxide semiconductor layer may be arranged in a different direction from that shown in the drawing. In the following description, for example, the expression “the oxide semiconductor layer on the substrate” merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. Above or below means a stacking order in a structure in which multiple layers are stacked, and when it is expressed as a pixel electrode above a transistor, it may be a positional relationship where the transistor and the pixel electrode do not overlap each other in a plan view. On the other hand, when it is expressed as a pixel electrode vertically above a transistor, it means a positional relationship where the transistor and the pixel electrode overlap each other in a plan view.
The expressions “α includes A, B, or C”, “α includes any of A, B, and C”, and “α includes one selected from a group consisting of A, B, and C” do not exclude the case where α includes multiple combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.
In addition, the following embodiments may be combined with each other as long as there is no technical contradiction.
A semiconductor device according to an embodiment of the present invention will be described with reference to
A configuration of a semiconductor device 10 according to an embodiment of the present invention will be described with reference to
As shown in
The gate electrode 105 is arranged above the substrate 100. The gate insulating layer 110 and the gate insulating layer 120 are arranged above the substrate 100 and the gate electrode 105. The metal oxide layer 130 is arranged above the gate insulating layer 120. The metal oxide layer 130 is in contact with the gate insulating layer 120. The oxide semiconductor layer 140 is arranged above the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the metal oxide layer 130. In the main surface of the oxide semiconductor layer 140, a surface in contact with the metal oxide layer 130 is referred to as a lower surface 142. An end portion of the metal oxide layer 130 substantially coincides with an end portion of the oxide semiconductor layer 140.
In the present embodiment, no semiconductor layer or oxide semiconductor layer is arranged between the metal oxide layer 130 and the substrate 100.
In the present embodiment, although a configuration in which the metal oxide layer 130 is in contact with the gate insulating layer 120 and the oxide semiconductor layer 140 is in contact with the metal oxide layer 130 is exemplified, the configuration is not limited to this configuration. Other layers may be arranged between the gate insulating layer 120 and the metal oxide layer 130. Other layers may also be arranged between the metal oxide layer 130 and the oxide semiconductor layer 140.
In
The gate electrode 160 faces the oxide semiconductor layer 140. The gate insulating layer 150 is arranged between the oxide semiconductor layer 140 and the gate electrode 160. The gate insulating layer 150 is in contact with the oxide semiconductor layer 140. In the main surface of the oxide semiconductor layer 140, a surface in contact with the gate insulating layer 150 is referred to as an upper surface 141. A surface between the upper surface 141 and the lower surface 142 is referred to as a side surface 143. The insulating layers 170 and 180 are arranged above the gate insulating layer 150 and the gate electrode 160. Openings 171 and 173 that reach the oxide semiconductor layer 140 are arranged in the insulating layers 170 and 180. The source electrode 201 is arranged inside the opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is arranged inside the opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.
The gate electrode 105 has a function as a bottom-gate of the semiconductor device 10 and a function as a light-shielding film for the oxide semiconductor layer 140. The gate insulating layer 110 has a function as a barrier film for shielding impurities that diffuse from the substrate 100 toward the oxide semiconductor layer 140. The gate insulating layers 110 and 120 have a function as a gate insulating layer for the bottom-gate. The metal oxide layer 130 is a layer containing a metal oxide containing aluminum as the main component, and has a function as a gas barrier film for shielding a gas such as oxygen or hydrogen.
The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH. The channel region CH is a region of the oxide semiconductor layer 140 vertically below the gate electrode 160. The source region S is a region of the oxide semiconductor layer 140 that does not overlap the gate electrode 160 and is closer to the source electrode 201 than the channel region CH. The drain region D is a region of the oxide semiconductor layer 140 that does not overlap the gate electrode 160 and is closer to the drain electrode 203 than the channel region CH. The oxide semiconductor layer 140 in the channel region CH has physical properties as a semiconductor. The oxide semiconductor layer 140 in the source region S and the drain region D has physical properties as a conductor.
The gate electrode 160 has a function as a top-gate of the semiconductor device 10 and a light-shielding film for the oxide semiconductor layer 140. The gate insulating layer 150 has a function as a gate insulating layer for the top-gate, and has a function of releasing oxygen by a heat treatment in a manufacturing process. The insulating layers 170 and 180 insulate the gate electrode 160 and the source-drain electrode 200 and have a function of reducing parasitic capacitance therebetween. Operations of the semiconductor device 10 are controlled mainly by a voltage supplied to the gate electrode 160. An auxiliary voltage is supplied to the gate electrode 105. However, in the case of using the gate electrode 105 simply as a light-shielding film, a specific voltage is not supplied to the gate electrode 105, and the gate electrode 105 may be in a floating state. That is, the gate electrode 105 may simply be referred to as a “light-shielding film.”
In the present embodiment, although a configuration using a dual-gate transistor in which the gate electrode is arranged both above and below the oxide semiconductor layer as the semiconductor device 10 is exemplified, the configuration is not limited to this configuration. For example, a bottom-gate transistor in which the gate electrode is arranged only below the oxide semiconductor layer or a top-gate transistor in which the gate electrode is arranged only above the oxide semiconductor layer may be used as the semiconductor device 10. The above configuration is merely an embodiment, and the present invention is not limited to the above configuration.
As shown in
In the present embodiment, although a configuration in which all of the lower surface 142 of the oxide semiconductor layer 140 is covered with the metal oxide layer 130 is exemplified, the present invention is not limited to this configuration. For example, a part of the lower surface 142 of the oxide semiconductor layer 140 may not be in contact with the metal oxide layer 130. For example, all of the lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may be covered with the metal oxide layer 130, and all or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be covered with the metal oxide layer 130. That is, all or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be in contact with the metal oxide layer 130. However, in the above configuration, a part of the lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may not be covered with the metal oxide layer 130, and the other part of the lower surface 142 may be in contact with the metal oxide layer 130.
In the present embodiment, although a configuration in which the gate insulating layer 150 is formed on the entire surface and the openings 171 and 173 are arranged in the gate insulating layer 150 is exemplified, the configuration is not limited to this configuration. The gate insulating layer 150 may be patterned. For example, the gate insulating layer 150 may be patterned to expose the oxide semiconductor layer 140 in the source region S and the drain region D. That is, the gate insulating layer 150 in the source region S and the drain region D may be removed, and the oxide semiconductor layer 140 and the insulating layer 170 may be in contact with each other in these regions.
In
A rigid substrate having translucency, such as a glass substrate, a quartz substrate, a sapphire substrate, or the like, is used as the substrate 100. In the case where the substrate 100 needs to have flexibility, a substrate containing a resin such as a polyimide substrate, an acryl substrate, a siloxane substrate, or a fluororesin substrate is used as the substrate 100. In the case where the substrate containing a resin is used as the substrate 100, impurities may be introduced into the resin in order to improve the heat resistance of the substrate 100. In particular, in the case where the semiconductor device 10 is a top-emission display, since the substrate 100 does not need to be transparent, impurities that deteriorate the translucency of the substrate 100 may be used. In the case where the semiconductor device 10 is used for an integrated circuit that is not a display device, a substrate without translucency such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, a compound semiconductor substrate, or a conductive substrate such as a stainless substrate is used as the substrate 100.
Common metal materials are used for the gate electrode 105, the gate electrode 160, and the source-drain electrode 200. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys thereof or compounds thereof are used as these members. The above-described materials may be used in a single layer or in a stacked layer as the gate electrode 105, the gate electrode 160, and the source-drain electrode 200.
Common insulating materials are used for the gate insulating layers 110 and 120 and the insulating layers 170 and 180. For example, insulating layers such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride (SiNx), silicon nitride oxide (SiNxOy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride oxide (AlNxOy), and aluminum nitride (AlNx) are used as the inorganic insulating layers.
Among the above-described insulating layers, the insulating layer containing oxygen is used as the gate insulating layer 150. For example, an inorganic insulating layer such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), and aluminum oxynitride (AlOxNy) is used as the gate insulating layer 150.
An insulating layer having a function of releasing oxygen by a heat treatment is used as the gate insulating layer 120. For example, the temperature of the heat treatment at which the gate insulating layer 120 releases oxygen is 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, for example, in the case where the glass substrate is used as the substrate 100, the gate insulating layer 120 releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 10.
An insulating layer with few defects is used as the gate insulating layer 150. For example, when a composition ratio of oxygen in the gate insulating layer 150 is compared with a composition ratio of oxygen in an insulating layer (hereinafter referred to as “other insulating layer”) having a composition similar to that of the gate insulating layer 150, the composition ratio of oxygen in the gate insulating layer 150 is closer to the stoichiometric ratio with respect to the insulating layer than the composition ratio of oxygen in that other insulating layer. Specifically, in the case where silicon oxide (SiOx) is used for each of the gate insulating layer 150 and the insulating layer 180, the composition ratio of oxygen in the silicon oxide used as the gate insulating layer 150 is close to the stoichiometric ratio of silicon oxide as compared with the composition ratio of oxygen in the silicon oxide used as the insulating layer 180. For example, a layer in which no defects are observed when evaluated by electron-spin resonance (ESR) may be used as the gate insulating layer 150.
SiOxNy and AlOxNy described above are a silicon compound and an aluminum compound containing nitrogen (N) in a ratio (x>y) smaller than that of oxygen (O). SiNxOy and AlNxOy are a silicon compound and an aluminum compound containing oxygen in a ratio (x>y) smaller than that of nitrogen.
A metal oxide containing aluminum as the main component is used as the metal oxide layer 130. For example, an inorganic insulating layer such as aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride oxide (AlNxOy), or aluminum nitride (AlNx) is used as the metal oxide layer 130. The “metal oxide layer containing aluminum as the main component” means that the ratio of aluminum contained in the metal oxide layer 130 is 1% or more of the total amount of the metal oxide layer 130. The ratio of aluminum contained in the metal oxide layer 130 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the total amount of the metal oxide layer 130. The above ratio may be a mass ratio or a weight ratio.
A metal oxide having semiconductor properties is used as the oxide semiconductor layer 140. For example, an oxide semiconductor containing two or more metals containing indium (In) is used as the oxide semiconductor layer 140. The ratio of indium to the entire oxide semiconductor layer 140 is 50% or more. Gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), and lanthanoids are used as the oxide semiconductor layer 140 in addition to indium. Elements other than those described above may be used for the oxide semiconductor layer 140.
The oxide semiconductor layer 140 may be amorphous or crystalline. The oxide semiconductor layer 140 may be a mixed phase of amorphous and crystalline. Oxygen deficiencies are likely to be formed in the oxide semiconductor layer 140 in which the ratio of indium is 50% or more, as described below. Oxygen deficiencies are less likely to be formed in a crystalline oxide semiconductor as compared with an amorphous oxide semiconductor. Therefore, the oxide semiconductor layer 140 as described above is preferably crystalline.
In the case where the ratio of indium in the oxide semiconductor layer 140 is 50% or more, the semiconductor device 10 with high mobility is realized. On the other hand, since the oxygen contained in the oxide semiconductor layer 140 is easily reduced in such an oxide semiconductor layer 140, oxygen deficiencies are easily formed in the oxide semiconductor layer 140.
In the semiconductor device 10, hydrogen is released from a layer (for example, the gate insulating layers 110 and 120) arranged closer to the substrate 100 side than the oxide semiconductor layer 140 in the heat treatment step of the manufacturing process. When the hydrogen reaches the oxide semiconductor layer 140, oxygen deficiencies occur in the oxide semiconductor layer 140. The occurrence of the oxygen deficiencies is more pronounced the larger the pattern size of the oxide semiconductor layer 140 becomes. In order to suppress the occurrence of such oxygen deficiencies, it is necessary to suppress hydrogen from reaching the lower surface 142 of the oxide semiconductor layer 140. This is the first problem.
Apart from the above problem, there is a second problem shown below. The upper surface 141 of the oxide semiconductor layer 140 is affected by a process (for example, a patterning process or an etch process) after the oxide semiconductor layer 140 is formed. On the other hand, the lower surface 142 of the oxide semiconductor layer 140 (the surface of the oxide semiconductor layer 140 facing the substrate 100) is not affected as described above.
Therefore, there are more oxygen deficiencies formed near the upper surface 141 of the oxide semiconductor layer 140 than the oxygen deficiencies formed near the lower surface 142 of the oxide semiconductor layer 140. That is, the oxygen deficiencies in the oxide semiconductor layer 140 do not exist uniformly in a thickness direction of the oxide semiconductor layer 140, but exist in a non-uniform distribution in the thickness direction of the oxide semiconductor layer 140. Specifically, there are fewer oxygen deficiencies in the oxide semiconductor layer 140 toward the lower surface 142 side of the oxide semiconductor layer 140 and more oxygen deficiencies toward the upper surface 141 side of the oxide semiconductor layer 140.
In the case where an oxygen supply process is uniformly performed on the oxide semiconductor layer 140 having the oxygen deficiency distribution as described above, oxygen is excessively supplied to the lower surface 142 side of the oxide semiconductor layer 140 when supplying oxygen in an amount required to repair the oxygen deficiencies formed on the upper surface 141 side of the oxide semiconductor layer 140. As a result, a defect level different from the oxygen deficiency is formed on the lower surface 142 side due to the excess oxygen. As a result, phenomenon such as variation in characteristics in the reliability test or a decrease in field-effect mobility occurs. Therefore, in order to suppress such phenomenon, it is necessary to supply oxygen to the upper surface 141 side of the oxide semiconductor layer 140 while suppressing the oxygen supply to the lower surface 142 side of the oxide semiconductor layer 140.
The above problems are newly recognized in the process of reaching the present invention but are not problems that have been conventionally recognized. In the conventional configuration and manufacturing method, there was a trade-off relationship between the initial characteristics and the reliability test, in which the variation in characteristics according to the reliability test occurs even when the initial characteristics of the semiconductor device are improved by the oxygen supply process to the oxide semiconductor layer. However, with the configuration according to the present embodiment, the above problems are solved, and it is possible to obtain good initial characteristics and a reliability test result of the semiconductor device 10.
Furthermore, a flatness of a surface on which the oxide semiconductor layer 140 is deposited affects the crystallinity of the oxide semiconductor layer 140. In this embodiment, the metal oxide layer 130 on which the oxide semiconductor layer 140 is deposited is usually deposited by sputtering. A surface roughness (arithmetic mean roughness Ra) immediately after the metal oxide layer 130 is deposited by sputtering is about 1 nm to 4 nm. When a surface of the metal oxide layer 130 is uneven even by 1 nm to 4 nm, crystal growth in a thickness direction of the oxide semiconductor layer 140 is inhibited when crystallization is performed by a heat treatment on the oxide semiconductor layer 140 deposited thereon. In other words, the direction of crystal growth of the oxide semiconductor layer 140 becomes random due to surface irregularities. In a semiconductor device using such an oxide semiconductor layer, further improvement in field-effect mobility cannot be expected. Therefore, there is room for improvement in order to increase the field-effect mobility of semiconductor devices.
In the semiconductor device 10 of an embodiment of the present invention, a relationship between the arithmetic mean roughness Ra (nm) of the metal oxide layer 130 and the field effect mobility μ (cm2/Vs) is expressed by the following formula.
(where the arithmetic mean roughness is Ra≤0.80 nm.)
In an embodiment of the invention, a top surface of the metal oxide layer 130 has flatness at an interface between the metal oxide layer 130 and the oxide semiconductor layer 140. As described below, the oxide semiconductor layer 140 is deposited over a surface with reduced surface irregularities. When the oxide semiconductor layer 140 deposited on the metal oxide layer 130 is heat treated, a direction and speed at which the crystals of the oxide semiconductor layer 140 grow can be aligned. By using the oxide semiconductor layer 140 having such crystallinity, the field-effect mobility of the semiconductor device 10 can be further improved. Specifically, the field-effect mobility of the semiconductor device 10 can be increased to 40 cm2/Vs or higher.
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to
As shown in
Using silicon nitride as the gate insulating layer 110 allows the gate insulating layer 110 to block impurities that diffuse, for example, from the substrate 100 toward the oxide semiconductor layer 140. The silicon oxide used as the gate insulating layer 120 is silicon oxide having a physical property of releasing oxygen by a heat treatment.
As shown in
For example, a thickness of the metal oxide layer 130 at deposition is 6 nm or more and 60 nm or less, 6 nm or more and 50 nm or less, 6 nm or more and 25 nm or less, or 6 nm or more and 15 nm or less. The thickness of the metal oxide layer 130 may be set appropriately according to the planarization process described later. In the present embodiment, aluminum oxide is used as the metal oxide layer 130. Aluminum oxide has a high barrier property against gases such as oxygen or hydrogen. The metal oxide layer 130 is deposited by sputtering. In the present embodiment, the aluminum oxide used as the metal oxide layer 130 blocks hydrogen and oxygen released from the gate insulating layer 120, and suppresses the released hydrogen and oxygen from reaching the oxide semiconductor layer 140.
A surface of the metal oxide layer 130 immediately after deposition has surface irregularities of 1 nm to 4 nm. When crystallizing the oxide semiconductor layer 140, which is deposited on the metal oxide layer 130, if the surface irregularities of even 1 nm to 4 nm exist, a direction of crystal growth will be random. However, it is difficult to sputter the metal oxide layer 130 so that the surface irregularity is less than 1 nm. Therefore, it is preferable to make the surface irregularity of the metal oxide layer 130 less than 1 nm by performing a planarization process on the surface of the metal oxide layer 130.
As shown in
When the planarization process is performed by wet etching, an alkaline chemical solution is used as a chemical solution, for example, a developer solution to remove resist materials. Solutions of tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH) solutions are used as alkaline chemicals. Acidic chemical solutions such as phosphoric acid, nitric acid, hydrofluoric acid, hydrochloric acid, sulfuric acid, acetic acid, oxalic acid, or a mixture of these solutions may also be used. For example, a mixed acid containing phosphoric acid, nitric acid, and acetic acid may be used as an acidic chemical solution. It is preferable to remove 5 nm or more of the surface of the metal oxide layer 130 by wet etching, and it is more preferable to remove 40 nm or more. When the thickness of the metal oxide layer 130 is 6 nm or more and 25 nm or less, or 6 nm or more and 15 nm or less at the time of deposition, the thickness of the metal oxide layer 130 is 1 nm or more and 20 nm or less, preferably 1 nm or more and 10 nm or less by the planarization process. The arithmetic mean roughness of the metal oxide layer 130, as measured by observing the surface of the metal oxide layer 130 with AFM at 1000 nm square and 10 nm height (fixed), should be Ra<1 nm, Ra≤0.80, and Ra≤0.73 nm is more preferred. When wet etching is used as the planarization process, it can also serve as a cleaning process before depositing the oxide semiconductor layer 140.
When the planarization process is performed by a plasma process, it is performed by reverse sputtering or etching. When the plasma process is performed by reverse sputtering, an inert gas such as argon gas, helium gas, or nitrogen gas may be used. When the plasma process is performed by reverse sputtering, oxygen gas may be used, or a mixture of oxygen gas and an inert gas may be used. Alternatively, when the plasma process is performed in etching, halogen gas such as chlorine gas or fluorine gas may be used. It is preferable to remove 5 nm or more of the surface of the metal oxide layer 130 by the plasma process. When the thickness of the metal oxide layer 130 is 6 nm or more and 60 nm or less, or 6 nm or more and 50 nm or less at the time of deposition, the thickness of the metal oxide layer 130 is 1 nm or more and 20 nm or less, preferably 1 nm or more and 10 nm or less by the planarization process. The arithmetic mean roughness of the metal oxide layer 130, as measured by observing the surface of the metal oxide layer 130 with an AFM at 1000 nm square and 10 nm height (fixed), should be Ra<1 nm, Ra≤0.73 nm, and Ra≤0.67 is more preferred. When the plasma process is performed as the planarization process, particles adhering to the surface can also be removed.
A method for evaluating a flatness of the surface of the metal oxide layer 130 will be described. The flatness of the metal oxide layer 130 can be evaluated using an atomic force microscope (AFM: Atomic Force Microscope). A roughness curve is obtained by AFM analysis. Based on a roughness curve, an arithmetic mean roughness (Ra), a root mean square roughness (Rq), a maximum height difference (Rmax), and the like are obtained as roughness curve parameters.
The arithmetic mean roughness (Ra) is an average of absolute values of the ordinate Z(X) at the reference length. The lower the arithmetic mean roughness (Ra), the higher the flatness of the film. An ordinate value Z(X) is a height of the roughness curve at any position X. A root mean square height (Rq) is the root mean square at a reference length. It represents a standard deviation of a surface roughness.
The above roughness curve parameters are defined according to JIS B 0601-2001 (equivalent to ISO 4287-1997).
The roughness curve parameter of the metal oxide layer 130 may be calculated using a contrast of a cross-sectional TEM image of the semiconductor device instead of an atomic force microscope. In the cross-sectional TEM image, a contrast (brightness) of the metal oxide layer 130 and the oxide semiconductor layer 140 are different. Therefore, the boundary of the contrast between the metal oxide layer 130 and the oxide semiconductor layer 140 may be approximated as a roughness curve on the surface of the metal oxide layer 130. Based on the approximated roughness curve, the arithmetic mean roughness (Ra) and a root mean square roughness (Rq) may be calculated as roughness curve parameters according to JIS B 0601-2001.
A thickness of the metal oxide layer after the planarization process is 1 nm or more and 20 nm or less, preferably 1 nm or more and 10 nm or less.
As shown in
For example, a thickness of the oxide semiconductor layer 140 is 10 nm or more and 100 nm or less, 15 nm or more and 70 nm or less, or 20 nm or more and 40 nm or less. In this embodiment, an oxide containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer 140. Before the heat treatment (OS anneal) described below, the oxide semiconductor layer 140 is amorphous. The oxide semiconductor layer 140 before the heat treatment (OS anneal) described later is amorphous.
When the oxide semiconductor layer 140 is crystallized by the OS anneal process described later, the oxide semiconductor layer 140 after the deposition and before the OS anneal is preferably in an amorphous state (a state in which there are less low crystalline components of the oxide semiconductor). That is, the deposition conditions of the oxide semiconductor layer 140 are preferred to be such that the oxide semiconductor layer 140 immediately after the deposition does not crystallize as much as possible. For example, in the case where the oxide semiconductor layer 140 is deposited by the sputtering method, the oxide semiconductor layer 140 is deposited in a state where the temperature of the object to be deposited (the substrate 100 and structures formed thereon) is controlled.
In the case where the deposition is performed on the object to be deposited by the sputtering method, ions generated in the plasma and atoms recoiled by a sputtering target collide with the object to be deposited. Therefore, the temperature of the object to be deposited rises with the deposition process. When the temperature of the object to be deposited rises during the deposition process, microcrystals occur in the oxide semiconductor layer 140 immediately after the deposition process. The microcrystals inhibit crystallization by a subsequent OS anneal. For example, in order to control the temperature of the object to be deposited as described above, deposition may be performed while cooling the object to be deposited. For example, the object to be deposited may be cooled from a surface opposite to a deposited surface so that the temperature of the deposited surface of the object to be deposited (hereinafter, referred to as “deposition temperature”) is 100° C. or less, 70° C. or less, 50° C. or less, or 30° C. or less. As described above, depositing the oxide semiconductor layer 140 while cooling the object to be deposited makes it possible to deposit the oxide semiconductor layer 140 with few crystalline components in a state immediately after the deposition.
As shown in
A heat treatment (OS anneal) (“Annealing OS” in step S1006 of
As shown in
As shown in
A heat treatment (oxidation anneal) for supplying oxygen to the oxide semiconductor layer 140 is performed in a state where the gate insulating layer 150 is deposited on the oxide semiconductor layer 140 and the metal oxide layer 190 is deposited on the gate insulating layer 150 (“Annealing for Oxidation” in step S1009 of
Oxygen released from the gate insulating layer 120 by the oxidation anneal is blocked by the metal oxide layer 130. Therefore, oxygen is less likely to be supplied to the lower surface 142 of the oxide semiconductor layer 140. The oxygen released from the gate insulating layer 120 diffuses from a region where the metal oxide layer 130 is not formed to the gate insulating layer 150 arranged on the gate insulating layer 120 and reaches the oxide semiconductor layer 140 via the gate insulating layer 150. As a result, the oxygen released from the gate insulating layer 120 is less likely to be supplied to the lower surface 142 of the oxide semiconductor layer 140, and is mainly supplied to the side surface 143 and the upper surface 141 of the oxide semiconductor layer 140. Further, the oxidation anneal makes it possible to supply oxygen released from the gate insulating layer 150 to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. The oxidation anneal may release hydrogen from the gate insulating layers 110 and 120 but the hydrogen is blocked by the metal oxide layer 130.
As described above, in the annealing for oxidation step, it is possible to supply oxygen to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140 having a large amount of oxygen deficiencies while suppressing the supply of oxygen to the lower surface 142 of the oxide semiconductor layer 140 having a small amount of oxygen deficiencies.
As shown in
Resistances of the source region S and the drain region D of the oxide semiconductor layer 140 are reduced (“Reducing resistance of SD” in step S1011 of
As shown in
As shown in
With respect to the semiconductor device 10 manufactured by the above-described manufacturing method, in the oxide semiconductor layer 140, the direction and speed of crystal growth can be aligned. As a result, it is possible to obtain electrical characteristics having a mobility of 30 [cm2/Vs] or more, 35 [cm2/Vs] or more, or 40 [cm2/Vs] or more in a range where the channel length L of the channel region CH in the semiconductor device 10 is 2 μm or more and 4 μm or less and the channel width of the channel region CH is 2 μm or more and 25 μm or less. The mobility in the present embodiment is the field-effect mobility in a saturation region in the electrical characteristics of the semiconductor device 10. Specifically, the mobility means the largest value of the field-effect mobility in a region where a potential difference (Vd) between the source electrode and the drain electrode is greater than a value (Vg−Vth) obtained by subtracting a threshold-voltage (Vth) of the semiconductor device 10 from a voltage (Vg) supplied to the gate electrode.
In the semiconductor device 10 in which the metal oxide layer 130 is planarized by wet etching in the above manufacturing method, a relationship between an arithmetic mean roughness Ra (nm) of a surface of the metal oxide layer 130 and the field effect mobility μ (cm2/Vs) is expressed by the following formula.
(Where the arithmetic mean roughness Ra≤0.80)
In the semiconductor device 10 in which the metal oxide layer 130 is planarized by a plasma process in the above manufacturing method, a relationship between an arithmetic mean roughness Ra (nm) of a surface of the metal oxide layer 130 and the electric field effect mobility μ (cm2/Vs) is expressed by the following formula.
(Where the arithmetic mean roughness Ra≤0.67)
In the semiconductor device 10 in which the metal oxide layer 130 is planarized by wet etching or a plasma process in the above manufacturing method, the relationship between the arithmetic mean roughness Ra (nm) of the surface of the metal oxide layer 130 and the field effect mobility μ (cm2/Vs) is expressed by the following formula.
(Where the arithmetic mean roughness Ra≤0.73)
Modification 1 of the present embodiment will be described with reference to
As shown in
Modification 2 of the present embodiment will be described with reference to
As shown in
As shown in
Modification 3 of the present embodiment will be described with reference to
As shown in
The source-drain electrode 200 is in contact with the oxide semiconductor layer 140 in a region where the metal oxide layer 130 is not provided. In the plan view of
As shown in
As shown in
As described above, according to the semiconductor device 10 according to Modifications 1 to 3 of the present embodiment, the same effects as in the present embodiment can be obtained.
The configuration of the semiconductor device 10 for this embodiment is the same as that of the first embodiment. Therefore, the semiconductor device 10 according to this embodiment will be described with reference to
As shown in
Using silicon nitride as the gate insulating layer 110 allows the gate insulating layer 110 to block impurities diffusing, for example, from the substrate 100 toward the oxide semiconductor layer 140. The silicon oxide used as the gate insulating layer 120 is silicon oxide having a physical property of releasing oxygen by a heat treatment.
As shown in
For example, the thickness of the metal oxide layer 130 at deposition is 6 nm or more and 60 nm or less, 6 nm or more and 50 nm or less, 6 nm or more and 25 nm or less, or 6 nm or more and 15 nm or less. The thickness of the metal oxide layer 130 may be set appropriately according to the planarization process described later. In the present embodiment, aluminum oxide is used as the metal oxide layer 130. Aluminum oxide has a high barrier property against gases such as oxygen and hydrogen. The metal oxide layer 130 is deposited by sputtering. In the present embodiment, the aluminum oxide used as the metal oxide layer 130 blocks hydrogen and oxygen released from the gate insulating layer 120, and suppresses the released hydrogen and oxygen from reaching the oxide semiconductor layer 140.
The surface of the metal oxide layer 130 immediately after deposition has surface irregularities of 1 nm to 4 nm. When crystallizing the oxide semiconductor layer 140, which is deposited on the metal oxide layer 130, if surface irregularities of even 1 nm to 4 nm exist, the direction of crystal growth will be random. However, it is difficult to sputter the metal oxide layer 130 so that the surface irregularities are less than 1 nm. Therefore, it is preferable to make the surface irregularities of the metal oxide layer 130 less than 1 nm by performing a planarization process on the surface of the metal oxide layer 130.
As shown in
When the planarization process is performed by a wet etching process, an alkaline chemical solution, such as a chemical solution, for example, a developer solution to remove resist materials is used. Solutions of tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH) solutions are used as alkaline chemicals. Acidic chemical solutions such as phosphoric acid, nitric acid, hydrofluoric acid, hydrochloric acid, sulfuric acid, acetic acid, oxalic acid, or a mixture of these solutions may also be used. For example, a mixed acid containing phosphoric acid, nitric acid, and acetic acid may be used as an acidic chemical solution. It is preferable to remove 5 nm or more of the surface of the metal oxide layer 130 by wet etching, and it is more preferable to remove 40 nm or more. When the thickness of the metal oxide layer 130 is 6 nm or more and 25 nm or less, or 6 nm or more and 15 nm or less at the time of deposition, the thickness of the metal oxide layer 130 is 1 nm or more and 20 nm or less, preferably 1 nm or more and 10 nm or less by the planarization process. The arithmetic mean roughness of the metal oxide layer 130, as measured by observing the surface of the metal oxide layer 130 with AFM at 1000 nm square and 10 nm height (fixed), should be Ra<1 nm, Ra≤0.80, and Ra≤0.73 nm is more preferred. When wet etching is used as the planarization process, it can also serve as a cleaning process before depositing the oxide semiconductor layer 140.
When the planarization process is performed by a plasma process, it is performed by reverse sputtering or etching. When the plasma process is performed by reverse sputtering, an inert gas such as argon gas, helium gas, or nitrogen gas may be used. When the plasma process is performed by reverse sputtering, oxygen gas may be used, or a mixture of oxygen gas and an inert gas may be used. Alternatively, when the plasma process is performed in etching, halogen gas such as chlorine gas or fluorine gas may be used. It is preferable to remove 5 nm or more of the surface of the metal oxide layer 130 by the plasma process. When the thickness of the metal oxide layer 130 is 6 nm or more and 60 nm or less, or 6 nm or more and 50 nm less at the time of deposition, the thickness of the metal oxide layer 130 is 1 nm or more and 20 nm or less, preferably 1 nm or more and 10 nm or less by the planarization process. The arithmetic mean roughness of the metal oxide layer 130, as measured by observing the surface of the metal oxide layer 130 with an AFM at 1000 nm square and 10 nm height (fixed), should be Ra<1 nm, Ra≤0.73 nm, and Ra≤0.67 is more preferred. When the plasma process is performed as the planarization process, particles adhering to the surface can also be removed.
A method for evaluating a flatness of the surface of the metal oxide layer 130 will be described. A roughness curve is obtained by AFM analysis. Based on a roughness curve, an arithmetic mean roughness (Ra), a root mean square roughness (Rq), a maximum height difference (Rmax), and the like are obtained as roughness curve parameters.
A thickness of the metal oxide layer after the planarization process is 1 nm or more and 20 nm or less, preferably 1 nm or more and 10 nm or less.
As shown in
For example, the thickness of the oxide semiconductor layer 140 is 10 nm or more and 100 nm or less, 15 nm or more and 70 nm or less, or 20 nm or more and 40 nm or less. In this embodiment, an oxide containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer 140. Before the heat treatment (OS anneal) described below, the oxide semiconductor layer 140 is amorphous. The oxide semiconductor layer 140 before the heat treatment (OS anneal) described later is amorphous.
When the oxide semiconductor layer 140 is crystallized by the OS anneal described later, the oxide semiconductor layer 140 after the deposition and before the OS anneal is preferably in an amorphous state (a state in which there are less low crystalline components of the oxide semiconductor). That is, the deposition conditions of the oxide semiconductor layer 140 are preferred to be such that the oxide semiconductor layer 140 immediately after the deposition does not crystallize as much as possible. For example, in the case where the oxide semiconductor layer 140 is deposited by the sputtering method, the oxide semiconductor layer 140 is deposited in a state where the temperature of the object to be deposited (the substrate 100 and structures formed thereon) is controlled.
In the case where the deposition is performed on the object to be deposited by the sputtering method, ions generated in the plasma and atoms recoiled by a sputtering target collide with the object to be deposited. Therefore, the temperature of the object to be deposited rises with the deposition process. When the temperature of the object to be deposited rises during the deposition process, microcrystals occur in the oxide semiconductor layer 140 immediately after the deposition process. The microcrystals inhibit crystallization by a subsequent OS anneal. For example, in order to control the temperature of the object to be deposited as described above, deposition may be performed while cooling the object to be deposited. For example, the object to be deposited may be cooled from a surface opposite to a deposited surface so that the temperature of the deposited surface of the object to be deposited (hereinafter, referred to as “deposition temperature”) is 100° C. or less, 70° C. or less, 50° C. or less, or 30° C. or less. As described above, depositing the oxide semiconductor layer 140 while cooling the object to be deposited makes it possible to deposit the oxide semiconductor layer 140 with few crystalline components in a state immediately after the deposition.
As shown in
After the patterning of the oxide semiconductor layer 140, a heat treatment (“Annealing OS” in step S2006 of
As shown in
As shown in
For example, a thickness of the metal oxide layer 190 is 5 nm or more and 100 nm or less, 5 nm or more and 50 nm or less, 5 nm or more and 30 nm or less, or 7 nm or more and 15 nm or less. In this embodiment, aluminum oxide is used as the metal oxide layer 190. Aluminum oxide has a high barrier property against gases such as oxygen and hydrogen. In this embodiment, the aluminum oxide used as the metal oxide layer 190 suppresses an outward diffusion of oxygen that is launched into the gate insulating layer 150 during the deposition of the metal oxide layer 190.
For example, when the metal oxide layer 190 is formed by sputtering, the process gas used in sputtering remains in the film of the metal oxide layer 190. For example, when Ar is used as the process gas for sputtering, Ar may remain in the film of the metal oxide layer 190. Residual Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer 190.
With the gate insulating layer 150 deposited on the oxide semiconductor layer 140 and the metal oxide layer 190 deposited on the gate insulating layer 150, a heat treatment (Annealing for Oxidation) is performed to provide oxygen to the oxide semiconductor layer 140 (“Annealing for Oxidation” in step S2010 of
Oxygen released from the gate insulating layer 120 by the oxidation anneal is blocked by the metal oxide layer 130. Therefore, oxygen is less likely to be supplied to the lower surface 142 of the oxide semiconductor layer 140. The oxygen released from the gate insulating layer 120 diffuses from a region where the metal oxide layer 130 is not formed to the gate insulating layer 150 arranged on the gate insulating layer 120 and reaches the oxide semiconductor layer 140 via the gate insulating layer 150. As a result, the oxygen released from the gate insulating layer 120 is less likely to be supplied to the lower surface 142 of the oxide semiconductor layer 140, and is mainly supplied to the side surface 143 and the upper surface 141 of the oxide semiconductor layer 140. Further, the oxidation anneal makes it possible to supply oxygen released from the gate insulating layer 150 to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. The oxidation anneal may release hydrogen from the gate insulating layers 110 and 120 but the hydrogen is blocked by the metal oxide layer 130.
As described above, in the oxidation anneal step, it is possible to supply oxygen to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140 having a large amount of oxygen deficiencies while suppressing the supply of oxygen to the lower surface 142 of the oxide semiconductor layer 140 having a small amount of oxygen deficiencies.
Similarly, in the above oxidation annealing, the oxygen hammered into the gate insulating layer 150 is blocked by the metal oxide layer 190. Therefore, the release of the oxygen into the atmosphere is suppressed. Therefore, the oxygen is efficiently supplied to the oxide semiconductor layer 140 by the oxidation annealing, and the oxygen deficiencies are repaired.
As shown in
As shown in
Resistances of the source region S and the drain region D of the oxide semiconductor layer 140 are reduced (“Reducing resistance of SD” in step S2013 of
As shown in
As shown in
With respect to the semiconductor device 10 manufactured by the above-described manufacturing method, in the oxide semiconductor layer 140, the direction and speed of crystal growth can be aligned. As a result, it is possible to obtain electrical characteristics having a mobility of 50 [cm2/Vs] or more, 55 [cm2/Vs] or more, or 60 [cm2/Vs] or more in a range where the channel length L of the channel region CH in the semiconductor device 10 is 2 μm or more and 4 μm or less and the channel width of the channel region CH is 2 μm or more and 25 μm or less. The mobility in the present embodiment is the field-effect mobility in a saturation region in the electrical characteristics of the semiconductor device 10. Specifically, the mobility means the largest value of the field-effect mobility in a region where a potential difference (Vd) between the source electrode and the drain electrode is greater than a value (Vg−Vth) obtained by subtracting a threshold-voltage (Vth) of the semiconductor device 10 from a voltage (Vg) supplied to the gate electrode.
In the semiconductor device 10 in which the metal oxide layer 130 is planarized by a wet etching in the above manufacturing method, the relationship between the arithmetic mean roughness Ra (nm) of the surface of the metal oxide layer 130 and the field effect mobility μ (cm2/Vs) is expressed by the following formula.
(Where the arithmetic mean roughness Ra≤0.80)
In the semiconductor device 10 in which the metal oxide layer 130 is planarized by a plasma process in the above manufacturing method, the relationship between the arithmetic mean roughness Ra (nm) of a surface of the metal oxide layer 130 and the electric field effect mobility μ (cm2/Vs) is expressed by the following formula.
(Where the arithmetic mean roughness Ra≤0.67)
In the semiconductor device 10 in which the metal oxide layer 130 is planarized by a wet etching or a plasma process in the above manufacturing method, the relationship between the arithmetic mean roughness Ra (nm) of the surface of the metal oxide layer 130 and the field effect mobility μ (cm2/Vs) is expressed by the following formula.
(Where the arithmetic mean roughness Ra≤0.73)
A display device using a semiconductor device according to an embodiment of the present invention will be described with reference to
A seal region 24 where the seal portion 310 is arranged is a region surrounding the liquid crystal region 22. The FPC 330 is arranged in a terminal region 26. The terminal region 26 is a region where the array substrate 300 is exposed from the counter substrate 320 and is arranged outside the seal region 24. Outside the seal region 24 means regions outside the region where the seal portion 310 is arranged and the region surrounded by the seal portion 310. The IC chip 340 is arranged on the FPC 330. The IC chip 340 supplies a signal for driving each pixel circuit 301.
A source wiring 304 extends from the source driver circuit 302 in the first direction D1 and is connected to the plurality of pixel circuits 301 arranged in the first direction D1. A gate wiring 305 extends from the gate driver circuit 303 in the second direction D2 and is connected to the plurality of pixel circuits 301 arranged in the second direction D2.
A terminal portion 306 is arranged in the terminal region 26. The terminal portion 306 and the source driver circuit 302 are connected by a connection wiring 307. Similarly, the terminal portion 306 and the gate driver circuit 303 are connected by the connection wiring 307. By connecting the FPC 330 to the terminal portion 306, an external device which is connected to the FPC 330 and the display device 20 are connected, and a signal from the external device drives each pixel circuit 301 arranged in the display device 20.
The semiconductor device 10 shown in the first embodiment and the second embodiment is used as a transistor included in the pixel circuit 301, the source driver circuit 302, and the gate driver circuit 303.
An insulating layer 360 is arranged on the source electrode 201 and the drain electrode 203. A common electrode 370 arranged in common for the plurality of pixels is arranged on the insulating layer 360. An insulating layer 380 is arranged on the common electrode 370. An opening 381 is arranged in the insulating layers 360 and 380. A pixel electrode 390 is arranged on the insulating layer 380 and within the opening 381. The pixel electrode 390 is connected to the drain electrode 203.
A display device using a semiconductor device according to an embodiment of the present invention will be explained with reference to
As shown in
In the third embodiment and the fourth embodiment, although the configuration in which the semiconductor device explained in the first embodiment and the second embodiment was applied to a liquid crystal display device and an organic EL display device was exemplified, the semiconductor device may be applied to display devices (for example, a self-luminous display device or an electronic paper display device other than an organic EL display device) other than these display devices. In addition, the semiconductor device described above can be applied without any particular limitation from a small sized display device to a large sized display device.
In this example, the effect of the planarization process on the surface of the aluminum-based oxide metal layer is explained with reference to
In this example, the semiconductor device was formed according to the sequence diagram of the manufacturing method of the semiconductor device 10 shown in
Conditions for planarization process of aluminum oxide are as follows:
The thickness of the aluminum oxide at deposition is set to be 10 nm in both cases by performing the planarization process. When the thickness at deposition is 50 nm, the thickness is reduced to 10 nm by removing 40 nm through the planarization process. When the thickness at deposition is 15 nm, the thickness is reduced to 10 nm by removing 5 nm through the planarization process. When the thickness is 10 nm at deposition, the thickness is reduced 10 nm by removing less than 1 nm by performing the planarization process.
The measurement conditions for the electrical characteristics shown in
First, the results of the planarization process of the aluminum oxide under Condition 1 (developer solution (TMAH)) of the planarization process are described.
As shown by the arrows in the graphs in
The average threshold voltage in the substrate plane of the electrical characteristics are shown in
As shown in
Next, the results of the planarization process of the aluminum oxide under Condition 2 (Ar gas) of the planarization process are described.
As indicated by the arrows in the graphs in
The average value of the threshold voltage in the substrate plane of the electrical characteristics is shown in
As shown in
As explained above, it was shown that the average value of the mobility of the semiconductor device 10 exceeds 40 cm2/Vs by removing 5 nm or more of the aluminum oxide in Conditions 1 and 2 of the planarization process.
Next, the correlation between the arithmetic mean roughness Ra after planarization process on the surface of aluminum oxide and the field effect mobility u is verified, and the results are explained with reference to
First, the arithmetic mean roughness Ra and the root mean square roughness Rq after forming an aluminum oxide layer on the substrate and performing the planarization process on the aluminum oxide layer are explained.
Condition 2 for planarization process of aluminum oxide are as follows:
The thickness of the aluminum oxide at the deposition is set to be 10 nm in all cases by the planarization process. When the thickness at the deposition is 50 nm, the thickness is reduced to 10 nm by removing 40 nm through the planarization process. When the thickness at the deposition is 15 nm, the thickness is reduced to 10 nm by removing 5 nm through the planarization process. When the thickness at the deposition is 10 nm, the thickness is reduced to 10 nm by removing less than 1 nm through the planarization process.
Roughness curves were obtained from the AFM images shown in
As shown in Table 1, both the arithmetic mean roughness (Ra) and the root mean square roughness (Rq) were found to decrease with the amount of surface removal of the aluminum oxide layer in both Condition 1 and Condition 2.
Next, the correlation between the arithmetic mean roughness Ra of the surface of the aluminum oxide layer and the field-effect mobility μ of the semiconductor device was verified, and the results are explained with reference to
The arithmetic mean roughness Ra shown in
The arithmetic mean roughness Ra shown in
The approximate line shown in
As shown in
Each of the embodiments described above as an embodiment of the present invention can be appropriately combined and implemented as long as no contradiction is caused. In addition, the addition, deletion, or design change of components, or the addition, deletion, or condition change of processes as appropriate by those skilled in the art based on a semiconductor device and a display device of each embodiment are also included in the scope of the present invention as long as they are provided with the gist of the present invention.
Further, it is understood that, even if the effect is different from those provided by each of the above-described embodiments, the effect obvious from the description in the specification or easily predicted by persons ordinarily skilled in the art is apparently derived from the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-057450 | Mar 2022 | JP | national |
This application is a Continuation of International Patent Application No. PCT/JP2023/009876, filed on Mar. 14, 2023, which claims the benefit of priority to Japanese Patent Application No. 2022-057450, filed on Mar. 30, 2022, the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2023/009876 | Mar 2023 | WO |
| Child | 18894340 | US |
