Patent Application
20250098246
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-151598, filed on Sep. 19, 2023; the entire contents of which are incorporated herein by reference.
Embodiments of the invention generally relate to a semiconductor device and a method for manufacturing the same.
Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and the like are used in applications such as power conversion. It is desirable for the characteristic fluctuation between semiconductor devices to be small.
According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a gate electrode, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a second electrode. The first semiconductor region is located on the first electrode, and is electrically connected with the first electrode. The gate electrode is located on the first semiconductor region with a gate insulating layer interposed. The second semiconductor region faces the gate electrode via the gate insulating layer in a second direction perpendicular to a first direction that is from the first electrode toward the first semiconductor region. The second semiconductor region includes a first portion, a second portion, and a third portion. The second portion is located on the first portion and has a higher second-conductivity-type impurity concentration than the first portion. The third portion is positioned between the second portion and the gate electrode in the second direction and has a higher concentration of a first element than the second portion. The first element is at least one selected from the group consisting of carbon, germanium, antimony, and indium. The third semiconductor region is located on the second semiconductor region. The second electrode is electrically connected with the second and third semiconductor regions, and includes a contact part arranged with the third semiconductor region in the second direction and located on the second portion.
Various embodiments will be described hereinafter with reference to the accompanying drawings. The drawings are schematic and conceptual; and the relationships between the thickness and width of portions, the proportions of sizes among portions, etc., are not necessarily the same as the actual values thereof. Further, the dimensions and proportions may be illustrated differently among drawings, even for identical portions. In the specification and drawings, components similar to those described or illustrated in a drawing thereinabove are marked with like reference numerals, and a detailed description is omitted as appropriate.
In the following description, the notations of n+, n, n−, p+, and p indicate relative levels of the impurity concentrations of the conductivity types. Namely, n+ indicates that the n-type impurity concentration is relatively higher than that of n; and n− indicates that the n-type impurity concentration is relatively lower than that of n. Also, p+ indicates that the p-type impurity concentration is relatively higher than that of p. According to the embodiments described below, each embodiment may be implemented by inverting the p-type and the n-type of the semiconductor regions.
The semiconductor device 100 according to the embodiment shown in
An XYZ orthogonal coordinate system is used in the description of embodiments. The direction from the lower electrode 21 toward the n−-type drift region 1 is taken as a Z-direction (a first direction). Two mutually-orthogonal directions perpendicular to the Z-direction are taken as an X-direction (a second direction) and a Y-direction (a third direction). In the description, the direction from the lower electrode 21 toward the n−-type drift region 1 is called “up/upward/higher than”, and the opposite direction is called “down/downward/lower than”. These directions are based on the relative positional relationship between the lower electrode 21 and the n−-type drift region 1, and are independent of the direction of gravity.
The lower electrode 21 is located at the lower surface of the semiconductor device 100. The n+-type drain region 4 is located on the lower electrode 21, and is electrically connected with the lower electrode 21. The n−-type drift region 1 is located on the n+-type drain region 4. The n−-type drift region 1 is electrically connected with the lower electrode 21 via the n+-type drain region 4. The n-type impurity concentration of the n−-type drift region 1 is less than the n-type impurity concentration of the n+-type drain region 4.
The gate electrode 10 is located on the n−-type drift region 1 with the gate insulating layer 11 interposed. The p-type base region 2 is located on the n−-type drift region 1. The n+-type source region 3 is located on the p-type base region 2. A portion of the n−-type drift region 1, the p-type base region 2, and at least a portion of the n+-type source region 3 face the gate electrode 10 via the gate insulating layer 11 in the X-direction.
The upper electrode 22 is located on the p-type base region 2 and the n+-type source region 3, and is positioned at the upper surface of the semiconductor device 100. The upper electrode 22 includes a contact part 22a. The contact part 22a extends downward, and is arranged with the n+-type source region 3 and a portion of the p-type base region 2 in the X-direction. The insulating layer 12 is located between the gate electrode 10 and the upper electrode 22; and the gate electrode 10 and the upper electrode 22 are electrically isolated from each other.
Pluralities of each of the p-type base region 2, the n+-type source region 3, the gate electrode 10, and the contact part 22a are arranged in the X-direction. The p-type base region 2 is positioned between gate electrodes 10 adjacent to each other in the X-direction. The p-type base regions 2, the n+-type source regions 3, the gate electrodes 10, and the contact parts 22a extend in the Y-direction.
As shown in
The p-type impurity concentration in the second portion 2b and the p-type impurity concentration in the third portion 2c are greater than the p-type impurity concentration in the first portion 2a. The concentration of a first element in the third portion 2c is greater than the concentration of the first element in the second portion 2b and the concentration of the first element in the first portion 2a. The first element is at least one selected from the group consisting of carbon, germanium, antimony, and indium.
As shown in
In the illustrated example, the p-type base region 2 includes a pair of third portions 2c that are separated from each other, and a pair of fourth portions 2d that are separated from each other. The second portion 2b is positioned between the pair of third portions 2c in the X-direction. The contact part 22a is positioned between the pair of fourth portions 2d in the X-direction. The second portion 2b and the pair of fourth portions 2d contact the contact part 22a.
The maximum impurity concentration is taken as “1” in the concentration distributions shown in
The concentrations of the p-type impurity and the first element in the components of the p-type base region 2 can be acquired by secondary ion mass spectrometry (SIMS) or atom probe. Or, the carrier densities of the components of the p-type base region 2 may be measured with a scanning capacitance microscope (SCM). The carrier density can be considered to be substantially equal to the impurity concentration of each component. Accordingly, the distribution of the carrier density in the p-type base region 2 can be used as the distribution of the p-type impurity concentration in the p-type base region 2.
Operations of the semiconductor device 100 will now be described.
A voltage that is not less than a threshold is applied to the gate electrode 10 in a state in which a positive voltage with respect to the upper electrode 22 is applied to the lower electrode 21. As a result, a channel (an inversion layer) is formed in the p-type base region 2; and the semiconductor device 100 is set to an on-state. Electrons flow from the upper electrode 22 toward the lower electrode 21 via the channel. When the voltage applied to the gate electrode 10 drops below the threshold, the channel in the p-type base region 2 disappears, and the semiconductor device 100 is set to an off-state.
Examples of the materials of the components will now be described.
The n−-type drift region 1, the p-type base region 2, the n+-type source region 3, and the n+-type drain region 4 include single-crystal silicon as a semiconductor material. These semiconductor regions may include silicon carbide, gallium nitride, or gallium arsenide instead of single-crystal silicon. When single-crystal silicon is used as the semiconductor material, arsenic, phosphorus, or antimony is used as an n-type impurity. Boron is used as a p-type impurity. The gate electrode 10 includes a conductive material such as polysilicon, etc. The gate insulating layer 11 and the insulating layer 12 include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The lower electrode 21 and the upper electrode 22 include metals such as aluminum, titanium, copper, etc.
First, a semiconductor substrate that includes an n−-type semiconductor region 1x and an n+-type semiconductor region 4x is prepared. The n−-type semiconductor region 1x is positioned on the n+-type semiconductor region 4x. The n-type impurity concentration in the n−-type semiconductor region 1x is less than the n-type impurity concentration in the n+-type semiconductor region 4x. A p-type semiconductor region 2x is formed by ion-implanting a p-type impurity into the upper surface of the n−-type semiconductor region 1x. A portion of the p-type semiconductor region 2x and a portion of the n−-type semiconductor region 1x are removed by reactive ion etching (RIE). As a result, openings OP0 that extend in the Y-direction are formed as shown in
An insulating layer 11x is formed along the surface of the n−-type semiconductor region 1x and the surface of the p-type semiconductor region 2x by thermal oxidation. A conductive layer 10x is formed on the insulating layer 11x by chemical vapor deposition (CVD). The openings OP0 are filled with the conductive layer 10x. The upper surface of the conductive layer 10x is caused to recede by chemical mechanical polishing (CMP) and wet etching. As a result, as shown in
An n+-type semiconductor region 3x is formed by ion-implanting an n-type impurity into the upper surface of the p-type semiconductor region 2x. An insulating layer 12x is formed on the conductive layer 10x and the insulating layer 11x by CVD. A portion of the insulating layer 12x and a portion of the insulating layer 11x are removed by RIE. An opening OP1 is formed thereby. A portion of the n+-type semiconductor region 3x is exposed via the opening OP1.
As shown in
A portion of the n+-type semiconductor region 3x and a portion of the p-type semiconductor region 2x are removed by RIE via the opening OP1. As shown in
As shown in
As shown in
As an example, the aspect ratio of the opening OP2 is not less than 2 and not more than 3 in the processes shown in
As shown in
The lower surface of the n+-type semiconductor region 4x is polished until the n+-type semiconductor region 4x has a prescribed thickness. A metal layer 21x is formed at the lower surface of the n+-type semiconductor region 4x by sputtering. The metal layer 21x includes aluminum. As shown in
Advantages of the embodiment will now be described.
As shown in
In particular, it is desirable to form more gate electrodes 10 per unit area in the semiconductor device 100. By increasing the number of the gate electrodes 10 per unit area, the number of channels per unit area can be increased, and the on-resistance of the semiconductor device 100 can be reduced. On the other hand, when the number of the gate electrodes 10 is increased, the spacing between the gate electrodes 10 decreases. Also, the X-direction distance between the gate electrode 10 and the contact part 22a decreases. As a result, the effects of the diffusion of the p-type impurity on the threshold of the gate electrode 10 increase. For example, the fluctuation of the turn-on threshold voltage between the semiconductor devices increases.
For this problem, according to the embodiment, the p-type base region 2 includes the third portion 2c. The concentration of the first element in the third portion 2c is greater than the concentration of the first element in the second portion 2b. In the region into which the first element is implanted, the crystal of the semiconductor material is damaged, and at least a portion of this region becomes amorphous. When the p-type impurity diffuses, the p-type impurity accumulates more easily in amorphous regions than in crystalline regions. By providing the third portion 2c between the second portion 2b and the gate insulating layer 11, the p-type impurity that diffuses toward the gate insulating layer 11 easily accumulates in the third portion 2c. As a result, the diffusion of the p-type impurity toward the gate insulating layer 11 can be suppressed, and the fluctuation of the threshold of the gate electrode 10 can be suppressed.
The first element is at least one selected from the group consisting of carbon, germanium, antimony, and indium. These elements are easy to ion-implant, and have atomic radii sufficient to damage the silicon crystal lattice. Also, the effects on the operations of the semiconductor device 100 are small. According to the semiconductor device 100, the diffusion of the p-type impurity in the Z-direction is not suppressed. Therefore, the second portion 2b can be formed to have a sufficiently large Z-direction thickness. The electrical resistance between the p-type base region 2 and the contact part 22a can be sufficiently reduced.
According to the embodiment, the fluctuation of the threshold of the gate electrode 10 can be suppressed while suppressing a reduction of the Z-direction thickness of the second portion 2b.
By including the third portion 2c, a concentration distribution difference is obtained in the p-type base region 2 between the p-type impurity concentration distribution in the X-direction from the second portion 2b toward the gate insulating layer 11 and the p-type impurity concentration distribution in the Z-direction from the second portion 2b toward the first portion 2a. Generally, the diffusion distance of a p-type impurity in a semiconductor region is constant regardless of the direction. In contrast, by including the third portion 2c in the semiconductor device 100, the diffusion distance of the p-type impurity in the X-direction is less than the diffusion distance of the p-type impurity in the Z-direction. As a result, as shown in
Favorably, the concentration of the first element in the third portion 2c is greater than 3.0×1017 atoms/cm3. By setting the concentration of the first element to be greater than 3.0×1017 atoms/cm3, the diffusion of the p-type impurity can be effectively suppressed by the third portion 2c. On the other hand, when the concentration of the first element in the third portion 2c is excessively high, there is a possibility that the operations of the semiconductor device 100 may become unstable. It is therefore favorable for the concentration of the first element in the third portion 2c to be less than 5.0×1020 atoms/cm3.
In particular, it is favorable for the first element to be at least one selected from the group consisting of carbon and germanium. Carbon and germanium are Group 4 elements, and are electrically neutral. Even when carbon and germanium are included in the p-type base region 2, these elements substantially do not affect the operations of the semiconductor device 100.
Other than carbon, germanium, antimony, and indium, according to the manufacturing method according to the embodiment, argon or silicon may be ion-implanted into the p-type semiconductor region 2x when performing the process shown in
The semiconductor device 110 shown in
When a voltage that is not less than a threshold is applied to the gate electrode 10 in a state in which a positive voltage with respect to the upper electrode 22 is applied to the lower electrode 21, the semiconductor device 110 is set to the on-state. At this time, a channel (an inversion layer) is formed at the gate insulating layer 11 vicinity of the p-type base region 2. Electrons are injected from the n+-type emitter region 3e into the n−-type drift region 1 via the channel. Holes are injected from the collector region 5 into the n−-type drift region 1. Conductivity modulation occurs in the n−-type drift region 1; and the electrical resistance in the n−-type drift region 1 decreases. Subsequently, when the voltage applied to the gate electrode 10 drops below the threshold, the channel in the p-type base region 2 disappears, and the semiconductor device 110 is set to the off-state.
In the semiconductor device 110 as well, by including the third portion 2c in the p-type base region 2, the diffusion of the p-type impurity from the second portion 2b toward the gate insulating layer 11 can be suppressed. As a result, the fluctuation of the threshold of the gate electrode 10 can be suppressed while suppressing a reduction of the Z-direction thickness of the second portion 2b.
The embodiments may include the following features.
A semiconductor device, comprising:
The device according to Feature 1, wherein
The device according to Feature 1 or 2, wherein
The device according to any one of Features 1 to 3, wherein
The device according to any one of Features 1 to 4, wherein
A semiconductor device, comprising:
The device according to Feature 6, wherein
A method for manufacturing a semiconductor device,
While certain embodiments of the inventions have been illustrated, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. These novel embodiments may be embodied in a variety of other forms; and various omissions, substitutions, modifications, etc., can be made without departing from the spirit of the inventions. These embodiments and their modifications are within the scope and spirit of the inventions and are within the scope of the inventions described in the claims and their equivalents. The embodiments described above can be implemented in combination with each other.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-151598 | Sep 2023 | JP | national |
