Semiconductor device and method of fabricating the same

Abstract

A semiconductor device capable of suppressing reduction of the electric characteristics and fluctuation of the threshold voltage resulting from ion implantation is obtained. This semiconductor device comprises a pair of source/drain regions formed on the main surface of a semiconductor region to hold a channel region therebetween and a gate electrode formed on the channel region through a gate insulating film, and the gate electrode includes a first metal-containing layer, a second metal-containing layer formed on the first metal-containing layer and an intermediate layer formed between the first metal-containing layer and the second metal-containing layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view showing the structure of an n-channel MOS transistor according to an embodiment of the present invention; and

FIGS. 2 to 8 are sectional views for illustrating a process of fabricating the n-channel MOS transistor according to the embodiment of the present invention.

Claims

1. A semiconductor device comprising: a pair of source/drain regions formed on the main surface of a semiconductor region to hold a channel region therebetween; anda gate electrode formed on said channel region through a gate insulating film, whereinsaid gate electrode includes a first metal-containing layer, a second metal-containing layer formed on said first metal-containing layer and an intermediate layer formed between said first metal-containing layer and said second metal-containing layer.

2. The semiconductor device according to claim 1, wherein said first metal-containing layer is so formed as to partially cover the surface of said gate insulating film.

3. The semiconductor device according to claim 2, wherein said first metal-containing layer is provided in the form of dots to partially cover the surface of said gate insulating film.

4. The semiconductor device according to claim 2, wherein said second metal-containing layer is so formed as to partially cover the surface of said intermediate layer, anda region formed with said first metal-containing layer and a region formed with said second metal-containing layer deviate from each other in a direction parallel to the surface of said gate insulating film in plan view.

5. The semiconductor device according to claim 4, wherein said second metal-containing layer is provided in the form of dots to partially cover the surface of said intermediate layer.

6. The semiconductor device according to claim 1, wherein said intermediate layer includes a first semiconductor layer.

7. The semiconductor device according to claim 1, wherein said first metal-containing layer and said second metal-containing layer are provided on the surfaces of said gate insulating film and said intermediate layer to disperse substantially over the whole areas thereof respectively.

8. The semiconductor device according to claim 1, wherein said gate electrode further includes a second semiconductor layer formed on said second metal-containing layer, andsaid first metal-containing layer and said second metal-containing layer are arranged in the vicinity of the interface between said gate electrode and said gate insulating film.

9. The semiconductor device according to claim 8, wherein said second semiconductor layer includes a third semiconductor layer formed on said intermediate layer to come into contact with said second metal-containing layer and cover said second metal-containing layer and a fourth semiconductor layer formed on said third semiconductor layer.

10. The semiconductor device according to claim 9, wherein the thickness of said fourth semiconductor layer is larger than the thickness of said third semiconductor layer.

11. The semiconductor device according to claim 9, wherein said second metal-containing layer is arranged in the vicinity of the interface between said third semiconductor layer and said intermediate layer.

12. The semiconductor device according to claim 1, wherein said first metal-containing layer and said second metal-containing layer are made of TaN.

13. A method of fabricating a semiconductor device, comprising steps of: forming a gate electrode by successively forming a first metal-containing layer, an intermediate layer and a second metal-containing layer on the main surface of a semiconductor region through a gate insulating film; andion-implanting an impurity from above said gate electrode.

14. The method of fabricating a semiconductor device according to claim 13, wherein said step of forming said gate electrode includes a step of forming said first metal-containing layer to partially cover the surface of said gate insulating film.

15. The method of fabricating a semiconductor device according to claim 14, wherein said step of forming said first metal-containing layer includes a step of flocculating a first metal-containing film formed on said gate insulating film by heat treatment.

16. The method of fabricating a semiconductor device according to claim 14, wherein said step of forming said gate electrode includes a step of forming said second metal-containing layer to partially cover the surface of said intermediate layer.

17. The method of fabricating a semiconductor device according to claim 16, wherein said step of forming said second metal-containing layer includes a step of flocculating a second metal-containing film formed on said intermediate layer by heat treatment.

18. The method of fabricating a semiconductor device according to claim 16, wherein said step of forming said gate electrode includes a step of forming said first metal-containing layer and said second metal-containing layer so that a region formed with said first metal-containing layer and a region formed with said second metal-containing layer deviate from each other in a direction parallel to the surface of said gate insulating film in plan view.

19. The method of fabricating a semiconductor device according to claim 13, wherein said step of forming said gate electrode includes steps of forming said first metal-containing layer on said gate insulating film and forming said intermediate layer to cover said first metal-containing layer formed on said gate insulating film.

20. The method of fabricating a semiconductor device according to claim 19, wherein said step of forming said gate electrode further includes steps of forming said second metal-containing layer on said intermediate layer and forming a semiconductor layer to cover said second metal-containing layer formed on said intermediate layer.