SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Abstract

A semiconductor device such as a Static Random Access Memory (SRAM) cell includes an access transistor. A drain of the access transistor includes a first N-type impurity and a second N-type impurity. The diffusion coefficient of the first N-type impurity is smaller than the diffusion coefficient of the second N-type impurity. By providing a drain as described above, hot carrier effects within the access transistor may be minimized.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an equivalent circuit diagram of a conventional semiconductor device;

FIG. 2 illustrates an equivalent circuit diagram of a semiconductor device according to an embodiment exemplarily described herein;

FIG. 3 illustrates a plan view of one embodiment of a semiconductor device;

FIG. 4 illustrates a cross-sectional view of the semiconductor device shown in FIG. 3, taken along line I-I′;

FIG. 5 is an enlargement of region “A” shown in FIG. 4;

FIGS. 6 to 9 illustrate cross-sectional views describing one embodiment of a method of forming the semiconductor device shown in FIG. 3, taken along line I-I-′; and

FIGS. 10 to 13 illustrate cross-sectional views to describing another embodiment of a method of forming the semiconductor device shown in FIG. 3, taken along line I-I′.

Claims

1. A semiconductor device, comprising: a substrate having an active region;a first impurity region and a second impurity region in the active region;an access gate insulating layer and an access gate electrode stacked on the active region between the first and second impurity regions;an interlayer dielectric on the access gate electrode; anda bit line on the interlayer dielectric and electrically connected to the first impurity region,wherein the first impurity region includes a first N-type impurity and a second N-type impurity, the second impurity region includes the first N-type impurity and a diffusion coefficient of the first N-type impurity is smaller than a diffusion coefficient of the second N-type impurity.

2. The semiconductor device of claim 1, wherein the access gate electrode overlaps the first and second impurity regions, wherein an area of overlap between the first impurity region and the access gate electrode is larger than an area of overlap between the second impurity region and the access gate electrode.

3. The semiconductor device of claim 1, further comprising: a first junction including the first impurity region and a channel region under the access gate electrode; anda second junction including the second impurity region and the channel region,wherein an impurity concentration of a portion of the first impurity region adjacent to the first junction is smaller than an impurity concentration of a portion of the second impurity region adjacent to the second junction.

4. The semiconductor device of claim 1, further comprising a gate spacer on a sidewall of the access gate electrode.

5. The semiconductor device of claim 1, wherein the first impurity region comprises a first low-concentration region and a first high-concentration region and the second impurity region comprises a second low-concentration region and a second high-concentration region, wherein the first low-concentration region is between the first high-concentration region and a channel region under the access gate electrode,the second low-concentration region is between the second high-concentration region and the channel region, anda concentration of first N-type impurity in the first high-concentration region is higher than a concentration of first N-type impurity in the first low-concentration region.

6. The semiconductor device of claim 1, further comprising: a third impurity region in the active region; anda driver gate insulating layer and a driver gate electrode on the active region between the second and third impurity regions,wherein the second impurity region is operably proximate to the access gate electrode and the driver gate electrode.

7. The semiconductor device of claim 6, wherein the third impurity region includes the first N-type impurity.

8. The semiconductor device of claim 1, wherein the first N-type impurity is arsenic (As) and the second N-type impurity is phosphorus (P).

9. The semiconductor device of claim 6, further comprising: a load transistor having a gate electrode and first and second source/drain regions,wherein the first source/drain region is connected to a power line, the second source/drain region is connected to the second impurity region, and the gate electrode is connected to the driver gate electrode.

10. The semiconductor device of claim 1, wherein the access gate electrode is connected to a word line.

11. A method of forming a semiconductor device, the method comprising: forming an access gate insulating layer and access gate electrode on an active region of a substrate;forming a first impurity region and a second impurity region in the active region on either side of the access gate electrode;forming an interlayer dielectric on the access gate electrode; andforming a bit line on the interlayer dielectric, the bit line being electrically connected to the first impurity region,wherein the first impurity region includes a first N-type impurity and a second N-type impurity, the second impurity region includes the first N-type impurity, and a diffusion coefficient of the first N-type impurity is smaller than a diffusion coefficient of the second N-type impurity.

12. The method of claim 11, wherein forming the first and the second impurity region comprises: implanting the first N-type impurity into the active region at both sides of the access gate electrode in a first ion implant process to form a preliminary first implant region and a second implant region;implanting the second N-type impurity into the preliminary first implant region in a second ion implant process to form a first implant region; andactivating the implanted first and second N-type impurities.

13. The method of claim 12, further comprising: forming gate spacers on sidewalls of the access gate electrode after forming the first implant region; andimplanting the first N-type impurity into the first and second implant regions in a third ion implant process using the access gate electrode and the gate spacers as an implantation mask,wherein a concentration of the first N-type impurity implanted in the third ion implant process is higher than a concentration of the first N-type impurity implanted in the first ion implant process.

14. The method of claim 12, further comprising forming a gate spacer on a sidewall of the access gate electrode before performing the second ion implant process.

15. The method of claim 14, further comprising: implanting the first N-type impurity into the active region in a third ion implant process using the access gate electrode and gate spacer as an implantation mask,wherein a concentration of the first N-type impurity implanted in the third ion implant process is higher than a concentration of the first N-type impurity implanted in the first ion implant process.

16. The method of claim 11, wherein the access gate electrode overlaps the first and second impurity regions, wherein an area of overlap between the first impurity region and the access gate electrode is larger than an area of overlap between the second impurity region and the access gate electrode.

17. The method of claim 11, further comprising forming a channel region under the access gate electrode, wherein a first junction includes the first impurity region and the channel region; and a second junction includes the second impurity region and the channel region, wherein an impurity concentration of a portion of the first impurity region adjacent to the first junction is smaller than an impurity concentration of a portion of the second impurity region adjacent to the second junction.

18. The method of claim 11, wherein the first N-type impurity is arsenic (As) and the second N-type impurity is phosphorus (P).

19. The method of claim 11, further comprising: forming a driver gate insulating layer and a driver gate electrode on the active region; andforming a third impurity region in the active region,wherein the second impurity region is operably proximate to the access gate electrode and the driver gate electrode and the driver gate electrode is between the second impurity region and the third impurity region.

20. The method of claim 19, wherein the third impurity region includes the first N-type impurity.