Patent Application
20250194220
The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.
Various techniques on semiconductor devices have been proposed. For example, Japanese Patent Application Laid-Open No. 2010-062421 proposes a technology for covering a surface electrode connected to a guard ring, with a passivation film such as an interlayer film.
In a known art, however, a side surface of the surface electrode rises vertically with respect to an upper surface of a semiconductor substrate. Accordingly, a side surface of a portion of the passivation film which covers the surface electrode also rises vertically with respect to the upper surface of the semiconductor substrate. In such a structure, the vertically rising portion of the passivation film is prone to have cracks due to concentration of stresses such as a thermal stress. Thus, the surface electrode is sometimes subject to corrosion due to moisture ingress from a crack to an end of a chip during a temperature humidity bias (THB) reliability test. This consequently causes a problem of decrease in the reliability of the semiconductor device.
The present disclosure has been conceived in view of the problem, and the object is to provide a technology capable of enhancing the reliability of a semiconductor device.
A semiconductor device according to the present disclosure includes: a semiconductor substrate having an end; an insulating film along an upper surface of the semiconductor substrate; a first surface electrode selectively provided on the insulating film; and a passivation film covering the insulating film and the first surface electrode, wherein the passivation film includes a cover portion covering the first surface electrode, the cover portion having a tapered shape with at least one of a first structure or a second structure such that the cover portion becomes wider as the cover portion is closer to the semiconductor substrate in a cross-sectional view, in the first structure, the first surface electrode includes a first metal portion, and a second metal portion made of a metal with corrosion resistance higher than corrosion resistance of the first metal portion, the second metal portion being in contact with a side surface of the first metal portion on a same side as the end of the semiconductor substrate in a plan view, and having a tapered shape such that the second metal portion becomes wider as the second metal portion is closer to the semiconductor substrate in the cross-sectional view, and in the second structure, a first angle between a side surface of the cover portion and the upper surface of the semiconductor substrate on the cover portion side is smaller in the cross-sectional view than a second angle between a side surface of the first surface electrode and the upper surface of the semiconductor substrate on the first surface electrode side.
This can enhance the reliability of the semiconductor device.
These and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
Hereinafter, Embodiments will be described with reference to the accompanying drawings. The features to be described in Embodiments below are mere exemplification, and all of the features are not necessarily essential. In the description below, identical constituent elements in a plurality of Embodiments will be denoted by the same or similar reference numerals, and the different constituent elements will be mainly described. In the following description, a particular position and a particular direction such as “up”, “down”, “left”, “right”, “front”, or “back” need not always coincide with an actual position and an actual direction. Furthermore, n-type and p-type may be replaced with p-type and n-type, respectively, in the following description.
The cell region 81 is a region including a plurality of semiconductor elements. The semiconductor elements include, for example, at least one of a metal oxide semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor 10 (IGBT), a reverse-conducting IGBT (RC-IGBT), a Schottky barrier diode (SBD), or a PN junction diode (PND). In this SPECIFICATION, for example, at least one of A, B, C, . . . , or Z means any one of all combinations obtained by combining one type or more extracted from each of groups of A, B, C, . . . , and Z.
The pad region 82 is a region including a control pad for controlling the semiconductor elements in the cell region 81. The control pad may include, for example, a current sense pad, a Kelvin emitter pad, a gate pad, and a temperature sensing diode pad.
The current sense pad is a control pad for detecting a current flowing through the cell region 81 of the semiconductor device. This current sense pad is a control pad electrically connected to a part of the cell region 81 so that a fraction to one several ten-thousandth of the current flowing through the entirety of the cell region 81 flows through the current sense pad when the current flows through the cell region 81. The Kelvin emitter pad and the gate pad are control pads to which a gate drive voltage for controlling on/off of the semiconductor device is applied. The Kelvin emitter pad is electrically connected to a p-type base layer of the cell region 81. The gate pad is electrically connected to gate electrodes of the cell region 81. The temperature sensing diode pad is a control pad electrically connected to an anode and a cathode of a temperature sensing diode of the semiconductor device. A voltage between the anode and the cathode of the temperature sensing diode is measured. The temperature sensing diode, which is not illustrated, is disposed in the cell region 81. Then, the temperature of the semiconductor device is measured based on the voltage.
The termination region 83 for maintaining the breakdown voltage of the semiconductor device is disposed around a region obtained by combining the cell region 81 and the pad region 82. The termination region 83 appropriately has a breakdown voltage maintaining structure. The breakdown voltage maintaining structure may be established by, for example, a field limiting ring (FLR) surrounding the cell region 81 with p-type termination well layers of a p-type semiconductor or variation of lateral doping (VLD) surrounding the cell region 81 with p-type termination well layers having a concentration slope, on a first main surface that is a front side of the semiconductor device. The number of the ring-shaped p-type termination well layers to be used for the FLR and the concentration distribution of the VLD should be appropriately selected according to the design of the breakdown voltage of the semiconductor device. The p-type termination well layers may be formed on almost the whole pad region 82. Alternatively, a part of the cell region 81 may be formed in the pad region 82.
The end of the semiconductor substrate 1 corresponds to a perimeter of the termination region 83 in
The semiconductor substrate 1 may be made of silicon (Si) or a wide bandgap semiconductor. The wide bandgap semiconductor includes, for example, at least one of silicon carbide (SiC), silicon nitride (SiN), gallium oxide (Ga2O3), gallium nitride (GaN), or diamond. Particularly, a higher electric field can be applied to the termination region 83 in the semiconductor substrate 1 made of SiC than that in a semiconductor substrate made of Si. Furthermore, the semiconductor substrate 1 may be obtained from a normal semiconductor wafer or an epitaxial growth layer.
The semiconductor substrate 1 includes a guard ring region 1a that is a p-type termination well layer. The guard ring region 1a is ring-shaped similarly to the termination region 83 in a plan view. Although the number of the guard ring regions 1a in
The insulating film 2 is, for example, an oxide film, and is formed along the upper surface of the semiconductor substrate 1. Although the insulating film 2 is formed directly on the semiconductor substrate 1 in
The first surface electrode 3 is selectively provided on the insulating film 2. The first surface electrode 3 in Embodiment 1 is electrically connected to the guard ring region 1a through a contact hole of the insulating film 2, and functions as a field plate for maintaining the breakdown voltage. Typically, an electric field in driving the semiconductor elements is prone to concentrate on an interface between the insulating film 2 and the guard ring region 1a directly below the contact hole of the insulating film 2. Since the first surface electrode 3 functioning as the field plate can reduce such electric field concentration, the first surface electrode 3 can increase the breakdown voltage. Although the first surface electrode 3 in Embodiment 1 functions as the field plate, the first surface electrode 3 need not function as the field plate.
The first surface electrode 3 in Embodiment 1 includes a first metal portion 3a and a second metal portion 3b. The first metal portion 3a is made of, for example, AlSi. The first metal portion 3a may have a laminated structure consisting of a plurality of layers.
The second metal portion 3b is made of a metal with corrosion resistance higher than that of the first metal portion 3a, for example, tungsten. The second metal portion 3b is formed in contact with a side surface of the first metal portion 3a on the same side as the end of the semiconductor substrate 1 in a plan view. In other words, the second metal portion 3b is formed in contact with the right side surface of the first metal portion 3a in
The glass coat 4 continuously covers the insulating film 2 and the first surface electrode 3. With a first structure of the first surface electrode 3 including the first metal portion 3a and the second metal portion 3b as described above, a cover portion 4a of the glass coat 4 which covers the first surface electrode 3 has a tapered shape such that the cover portion 4a becomes wider as the cover portion 4a is closer to the semiconductor substrate 1 in a cross-sectional view. The glass coat 4 may have a laminated structure consisting of, for example, a SInSiN film and a SiN film. The SInSiN film can stabilize the termination breakdown voltage by correcting field nonuniformity caused by varying interface charges Qss and mobile ions from the outside (e.g., a mold resin). The SiN film can function as a protective film for preventing moisture ingress.
The polyimide film 5 covers the glass coat 4. The overcoating structure using the polyimide film 5 can reduce external influence. In the cross-sectional views subsequent to
Next, a conductive component made of, for example, AlSi is formed on the guard ring region 1a and the insulating film 2 through the film formation process. Then, patterning the conductive component forms the first metal portion 3a. Next, for example, a conductive component 31 made of, for example, tungsten is formed on the insulating film 2 and the first metal portion 3a through the film formation process.
Then, patterning the conductive component 31, such as etching back the conductive component 31 forms the second metal portion 3b having a tapered shape in a cross-sectional view as illustrated in
Then, the glass coat 4 continuously covering the insulating film 2 and the first surface electrode 3 is formed. The cover portion 4a of the glass coat 4 has a tapered shape in a cross-sectional view, with the first structure of the first surface electrode 3 having the tapered shape. Then, forming the polyimide film 5 covering the glass coat 4 completes the semiconductor device in
In the semiconductor device according to Embodiment 1, the glass coat 4 includes the cover portion 4a covering the first surface electrode 3, the cover portion 4a having a tapered shape such that the cover portion 4a becomes wider as the cover portion 4a is closer to the semiconductor substrate 1 in a cross-sectional view. Thus, a structure in which the side surface of the cover portion 4a obliquely rises with respect to the upper surface of the semiconductor substrate 1 can reduce cracks caused by concentration of stresses such as a thermal stress more than a structure in which the side surface vertically rises. This can prevent corrosion of the first surface electrode 3 due to moisture ingress from a crack to an end of a chip during a temperature humidity bias (THB) reliability test. Consequently, the reliability of the semiconductor device can be enhanced.
In Embodiment 1, the second metal portion 3b made of a metal with corrosion resistance higher than corrosion resistance of the first metal portion 3a is in contact with a side surface of the first metal portion 3a on the same side as the end of the semiconductor substrate 1 in a plan view. Even when a crack appears, such a structure can prevent corrosion of the first surface electrode 3 due to moisture ingress from the crack to an end of a chip.
In Embodiment 2, a first angle θ1 between the side surface of the cover portion 4a and the upper surface of the semiconductor substrate 1 on the cover portion 4a side is smaller in a cross-sectional view than a second angle θ2 between the side surface of the first surface electrode 3 and the upper surface of the semiconductor substrate 1 on the first surface electrode 3 side. With a second structure in which the first angle θ1 is smaller than the second angle θ2, the cover portion 4a of the glass coat 4 which covers the first surface electrode 3 has a tapered shape such that the cover portion 4a becomes wider as the cover portion 4a is closer to the semiconductor substrate 1 in a cross-sectional view.
Then, as illustrated in
The cover portion 4a of the glass coat 4 has a tapered shape in a cross-sectional view, with the second structure in which the first angle θ1 is smaller than the second angle θ2. Then, forming the polyimide film 5 covering the glass coat 4 completes the semiconductor device in
In the semiconductor device according to Embodiment 2, the glass coat 4 includes the cover portion 4a covering the first surface electrode 3, the cover portion 4a having a tapered shape such that the cover portion 4a becomes wider as the cover portion 4a is closer to the semiconductor substrate 1 in a cross-sectional view. Since such a structure can prevent cracks similarly to Embodiment 1, the reliability of the semiconductor device can be enhanced.
Thus, the semiconductor substrate 1 in Embodiment 3 includes a plurality of ring-shaped guard ring regions 1a as illustrated in
The structure according to Embodiment 3 is identical to a structure obtained by adding a second surface electrode 7 to the structure of Embodiment 2. The second surface electrode 7 is farther from the end of the semiconductor substrate 1 than the first surface electrode 3. In other words, the second surface electrode 7 is closer to the cell region 81 than the first surface electrode 3.
The guard ring region 1a at the outermost circumference is electrically connected to the first surface electrode 3 through a contact hole in the insulating film 2, and the other guard ring region 1a is electrically connected to the second surface electrode 7 through respective contact hole in the insulating film 2. The first surface electrode 3 is lower than the second surface electrode 7 with respect to the upper surface of the insulating film 2. The glass coat 4 may cover the second surface electrode 7, or a cover portion of the glass coat 4 which covers the second surface electrode 7 may have a tapered shape such that the cover portion becomes wider as the cover portion is closer to the semiconductor substrate 1 in a cross-sectional view.
Then, a resist 22 is formed, an etching process is performed on the conductive component 32, and the resist 22 is removed so that the first surface electrode 3 is formed on the guard ring region 1a at the outermost circumference and the second surface electrode 7 is formed on the other guard ring region 1a as illustrated in
Then, forming the glass coat 4 similarly to Embodiment 2 allows the cover portion 4a of the glass coat 4 which covers the first surface electrode 3 to have a tapered shape in a cross-sectional view. Then, forming the polyimide film 5 covering the glass coat 4 completes the semiconductor device in
In the semiconductor device according to Embodiment 3, the first surface electrode 3 is lower than the second surface electrode 7 with respect to the upper surface of the insulating film 2, the second surface electrode 7 being farther from the end of the semiconductor substrate 1 than the first surface electrode 3. Such a structure can easily form a tapered shape of the cover portion 4a covering the first surface electrode 3, and can reduce cracks in the second surface electrode 7 which is caused by, for example, wire bonding.
Although the number of the first surface electrodes 3 is one in the aforementioned description, the number may be multiple when the semiconductor device includes the second surface electrode 7. Although the use of Embodiment 3 in Embodiment 2 is described above, Embodiment 3 may be used in Embodiment 1. These are the same with Embodiment 4 and subsequent Embodiments.
The structure of the termination region 83 in a semiconductor device according to Embodiment 4 is identical to that in the semiconductor device according to Embodiment 3 which is illustrated in
Next, a resist is applied to the conductive component 32, and an exposure process is performed. The exposure process according to Embodiment 4 includes a first exposure process and a second exposure process to be performed separately.
In the first exposure process, an upper portion of a resist 23b in a second region which corresponds to the first surface electrode 3 except a lower portion of the resist 23b is exposed to light using a mask A as illustrated in
In the second exposure process, a resist 23c in a third region except a resist 23a in a first region which corresponds to the second surface electrode 7, and the resist 23b in the second region is exposed to light using a mask B as illustrated in
As described above, an exposure process of exposing, to light, the upper portion of the resist 23b in the second region and the resist 23c in the third region except the resist 23a in the first region is performed as illustrated in
Then, a development process is performed which removes the upper portion of the resist 23b in the second region and the resist 23c in the third region which have been exposed to light as illustrated in
Then, the etching process is performed which selectively etches the conductive component 32 using the lower portion of the resist 23b in the second region and the resist 23a in the first region. Consequently, not the conductive component 32 with the resist 23a in the first region, but the conductive component 32 without the resists 23a and 23b in the third region is etched. Furthermore, the thin resist 23b in the second region is removed during the etching process, and the conductive component 32 in the second region is half etched. Consequently, the first surface electrode 3 lower than the second surface electrode 7 is formed in the second region, and the second surface electrode 7 is formed in the first region that is farther from the end of the semiconductor substrate 1 than the second region as illustrated in
Next, the resists 23a is removed. Then, forming the glass coat 4 continuously covering the insulating film 2 and the first surface electrode 3, and forming the polyimide film 5 covering the glass coat 4 similarly to Embodiment 3 completes the semiconductor device in
The method of manufacturing the semiconductor device according to Embodiment 4 can reduce the number of etching processes on the conductive component 32 more than that according to Embodiment 3.
The structure of the termination region 83 in a semiconductor device according to Embodiment 5 is identical to that in the semiconductor device according to Embodiment 3 which is illustrated in
The method of manufacturing the semiconductor device according to Embodiment 5 can reduce the number of exposure processes more than that according to Embodiment 4.
As illustrated in
Since the first surface electrode 3 can be lowered with respect to the upper surface of the insulating film 2 in the semiconductor device according to Embodiment 6, the tapered shape of the cover portion 4a covering the first surface electrode 3 can be easily formed. The semiconductor device may additionally include the second surface electrode 7 described in, for example, Embodiment 3, although Embodiment 6 does not describe such a structure. This is the same with next Embodiment 7.
Each of the pattern portions 8 includes an oxide film 8a and a polyimide layer 8b. The oxide film 8a is formed on the semiconductor substrate 1, similarly to the insulating film 2 described in Embodiment 1. The polyimide layer 8b is formed on the oxide film 8a, and is formed inside an outline of the oxide film 8a in a plan view.
Reflecting the shape of the pattern portions 8 on the shape of the insulating film 9 in a cross-sectional view allows providing a recess 9a on the insulating film 9. Furthermore, the recess 9a on the insulating film 9 accommodates at least the lower portion of the first surface electrode 3. The height of the first surface electrode 3 with respect to the upper surface of the insulating film 9 is, for example, approximately 1 μm, and may be identical to the thickness of the glass coat 4.
Then, for example, the conductive component 32 made of, for example, AlSi is formed on the guard ring region 1a and the insulating film 9 through the film formation process as illustrated in
Since the first surface electrode 3 can be lowered with respect to the upper surface of the insulating film 9 in the semiconductor device according to Embodiment 7, the tapered shape of the cover portion 4a covering the first surface electrode 3 can be easily formed. Furthermore, the first surface electrode 3 can be lowered even in a region of the semiconductor substrate 1 where the trench 1b described in Embodiment 6 cannot be formed due to, for example, design constraints.
Embodiments and modifications can be combined without restraint, and appropriately modified or omitted.
A summary of various aspects of the present disclosure will be hereinafter described as Appendixes.
A semiconductor device, comprising:
The semiconductor device according to appendix 1, further comprising
The semiconductor device according to appendix 1 or 2,
The semiconductor device according to appendix 1 or 2, further comprising
A method of manufacturing a semiconductor device, the method comprising:
The method according to appendix 5,
The method according to appendix 5,
While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-206637 | Dec 2023 | JP | national |
