Patent Application
20250194124
This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0178629 filed in the Korean Intellectual Property Office on Dec. 11, 2023, the entire contents of which are hereby incorporated herein by reference.
The present disclosure relates to a semiconductor device and a method of manufacturing the same.
A diode is a two-terminal device that can conduct current in one direction. In particular, diodes for power semiconductors for switching require high voltage and large current.
Because diode devices have different electrical characteristics depending on the structures, appropriate devices are used depending on application fields. However, the diode devices commonly require high current density, a low turn-on voltage, a high breakdown voltage, a low leakage current, and a fast switching speed. In order to simultaneously satisfy these requirements, various structures have been proposed. The most generally-used diode structure is a PN diode made of a PN junction, where an intrinsic region is added to the PN diode to secure high voltage characteristics used for power semiconductors.
An embodiment provides a semiconductor device with a reduced turn-on voltage and increased current density in an on-state.
Another embodiment provides a method of manufacturing the semiconductor device.
According to an embodiment, a semiconductor device is provided. The semiconductor device includes a substrate, an epi layer on an upper surface of the substrate, and a P region located within the epi layer. The semiconductor device also includes at least one N+ region located within the P region and at least one insulating layer in contact with the epi layer, the P region, and the at least one N+ region. The semiconductor device further includes an anode on the P region, the at least one N+ region, and the at least one insulating layer.
The at least one insulating layer may be located on an upper surface of the epi layer, the P region and the N+ region. The at least one insulating layer may be located in a trench structure along sides of the P region and the N+ region within the epi layer.
The substrate may include at least one of an N+ type substrate, a P+ type substrate, or any combination thereof.
The epi layer may include at least one of an N− type epi layer, a P− type epi layer, or any combination thereof.
The semiconductor device may further include a P-well region or an N-well region located between the epi layer and the P region within the epi layer.
The semiconductor device may further include a P-well region located between the epi layer and the P region within the epi layer. The semiconductor device may also include an N region located between the P-well region and the P region.
The P region may include a P+ type.
The at least one N+ regions may include a number of N+ regions in the range of two to four N+ regions. The at least one insulating layer may include a number of insulating layers in the range of two to four insulating layers.
The semiconductor device may further include a cathode located on a lower surface of the substrate or spaced apart in the same layer as the anode.
In the semiconductor device, an inversion channel may be formed in a portion where the P region and the insulating layer contact each other in an on state.
According to another embodiment, a method of manufacturing a semiconductor device is provided. The method includes forming an epi layer on an upper surface of the substrate. The method also includes forming a P region in the epi layer through ion implantation. The method additionally includes forming at least one N+ region within the P region through ion implantation. The method further includes forming at least one insulating layer at a location in contact with the epi layer, the P region, and the at least one N+ region. The method further still includes forming an anode on the P region, the at least one N+ region, and the at least one insulating layer.
Forming the P region may include patterning by placing a mask on the epi layer before the ion implantation.
Forming the N+ region may include patterning by placing a mask on the P region and the epi layer before the ion implantation.
Forming the insulating layer may include forming the insulating layer on upper surfaces of the epi layer, the P region, and the at least one N+ region, or forming the insulating layer in a trench structure along sides of the P region and the at least one N+ region within the epi layer.
The method may include, after forming the epi layer and before forming the P region, forming a P-well region or an N-well region within the epi layer between the epi layer and the P region.
The method may further include, after forming the epi layer and before forming the P region, forming a P-well region within the epi layer between the epi layer and the P region. The method may also include forming an N region between the P-well region and the P region.
Forming the at least one N+ region may include forming a number of N+ regions in the range of two to four N+ regions through ion implantation in the P region. Forming the at least one insulating layer may include forming a number of insulating layers in the range of two to four insulating layers on upper surfaces of the epi layer, the P region, and the N+ region.
The method may further include, after forming the anode, forming a cathode on a lower surface of the substrate or spaced apart in the same layer as the anode.
The semiconductor device according to an embodiment has a reduced turn-on voltage, enabling diode operation without a cut-in voltage, and increasing current density in the on state.
The advantages, features, and aspects described hereinafter should become more apparent from the following description of the embodiments with reference to the accompanying drawings. However, the present disclosure should not be construed as being limited to the embodiments set forth herein. Although not specifically defined, all of the terms including the technical and scientific terms used herein have meanings understood by those having ordinary skill in the art to which the present disclosure pertains. The terms defined in a generally-used dictionary should not be interpreted ideally or exaggeratedly unless clearly defined in the present specification. In addition, unless explicitly described to the contrary, the terms such as “comprise”, “include”, and the like, and variations such as “comprises”, “comprising”, “includes”, “including”, and the like, should be understood to imply the inclusion of stated elements but not the exclusion of any other elements.
Further, the singular includes the plural unless mentioned otherwise.
In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like reference numerals designate like elements throughout the specification.
It should be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, the element can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
When a component, device, element, or the like of the present disclosure is described as having a purpose or performing an operation, function, or the like, the component, device, or element should be considered herein as being “configured to” meet that purpose or perform that operation or function.
Semiconductor devices according to embodiments are described below with reference to
Referring to
The substrate 100 may include an N+ type substrate, a P+ type substrate, or a combination thereof.
The N+ type substrate may include, for example, a material such as N+ type silicon carbide (SiC), N+ type gallium nitride (GaN), N+ type gallium oxide (Ga2O3), N+ type diamond, N+ type silicon (Si), N+ type gallium arsenide (GaAs), N+ type germanium (Ge), N+ type aluminum nitride (AlN), or the like. The P+ type substrate may include, for example, a material such as P+ type silicon carbide (SiC), P+ type gallium nitride (GaN), P+ type gallium oxide (Ga2O3), P+ type diamond, P+ type silicon (Si), P+ type gallium arsenide (GaAs), P+ type germanium (Ge), P+ type aluminum nitride (AlN), or the like.
The epi layer 200 is an epitaxial layer and is located on the upper surface of the substrate 100.
The epi layer 200 may include an N− type epi layer, a P− type epi layer, or a combination thereof.
The N− type epi layer may include, for example, a material such as N− type silicon carbide (SiC), N− type gallium nitride (GaN), N− type gallium oxide (Ga2O3), N− type diamond, N− type silicon (Si), N− type gallium arsenide (GaAs), N− type germanium (Ge), N− type aluminum nitride (AlN), and the like. The P− type epi layer may include, for example, a material such as P− type silicon carbide (SiC), P− type gallium nitride (GaN), P− type gallium oxide (Ga2O3), P− type diamond, P− type silicon (Si), P− type gallium arsenide (GaAs), P− type germanium (Ge), P− type aluminum nitride (AlN), or the like.
For example, the substrate 100 may be an N+ type substrate, and the epi layer 200 may be an N− type epi layer.
The P region 300 is located within the epi layer 200. The upper surface of the epi layer 200 and the upper surface of the P region 300 may be located on the same line.
The P region 300 may be formed through an ion implantation process.
The P region 300 may include a P type semiconductor material, for example P type silicon carbide (SiC), P type gallium nitride (GaN), P type gallium oxide (Ga2O3), P type diamond, P type silicon (Si), P type gallium arsenide (GaAs), P type germanium (Ge), P type aluminum nitride (AlN), or the like.
The N+ region 400 may be located within the P region 300. The upper surface of the P region 300 and the upper surface of the N+ region 400 may be located on the same line.
One or more N+ region 400 may be included within the P region 300. For example, one N+ region 400 may be included as shown in
The N+ region 400 may be formed through an ion implantation process.
The N+ region 400 may include an N+ type semiconductor material, for example N+ type silicon carbide (SiC), N+ type gallium nitride (GaN), N+ type gallium oxide (Ga2O3), N+ type diamond, N+ type silicon (Si), N+ type gallium arsenide (GaAs), N+ type germanium (Ge), N+ type aluminum nitride (AlN), or the like.
The insulating layer 500 may be located in contact with the epi layer 200, the P region 300, and the N+ region 400. For example, the insulating layer 500 may be located on the upper surfaces of the epi layer 200, the P region 300, and the N region 400.
The semiconductor device 10 according to an embodiment may include one or more insulating layers 500. For example, one insulating layer 500 may be included as shown in
The insulating layer 500 may include at least one of silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), or any combination thereof.
The anode 600 may be located on the P region 300, the N+ region 400, and the insulating layer 500. The anode 600 may include, for example, an ohmic metal.
The cathode 700 may be located on the lower surface of the substrate 100. The cathode 700 may include, for example, an ohmic metal.
A diode based on a PN junction has a built-in voltage due to the PN junction and can operate in the on state only when a voltage higher than this voltage is applied. The voltage before the diode turns on and conducts is referred to as cut-in voltage, threshold voltage, built-in voltage, etc.
The built-in voltage (Vbi) caused by the PN junction is determined by the N region doping concentration (Nd) and the P region doping concentration (Na) as shown in Equation 1. The built-in voltage (Vbi) is inevitably generated. Therefore, current is not conducted in the region of 0<applied voltage (VAK)<built-in voltage (Vbi) region, which causes a decrease in output voltage during diode rectification. As shown in Equation 1, since the voltage is inversely proportional to the intrinsic concentration (ni), power semiconductor materials with low intrinsic concentration, such as SiC, GaN, Ga2O3, and diamond, have a higher built-in voltage, and, accordingly, a higher cut-in voltage, which becomes a factor in increasing power consumption.
The semiconductor device 10 according to an embodiment has a structure that reduces a turn-on voltage by using a metal oxide semiconductor (MOS) channel. In other words, the semiconductor device 10 may realize a lower turn-on voltage than a theoretical limit turn-on voltage of a typical diode structure. In an embodiment, the structure of the semiconductor device 10 may achieve a turn-on voltage of about 0 V or negative (−) voltages, which may not be achieved by the typical diode structure. As a result, the semiconductor device 10 may perform the rectification operation even in a region where rectification operation may not be implanted by the conventional diode, i.e., from about 0 V or negative (−) voltages to existing turn-on voltages. In addition, the semiconductor device 10 according to an embodiment uses an ion implantation process and an epi process and thus does not require development of new process technology.
The operating mechanism of the semiconductor device 10 according to an embodiment is described in more detail below with reference to
Referring to
On the other hand, referring to
Accordingly, because the semiconductor device 10 according to an embodiment has a lower turn-on voltage as compared to a turn-on voltage in conventional diode structure, the semiconductor device 10 may realize diode operation without a blocking voltage. In addition, the semiconductor device 10 may increase current density in the on-state according to the conduction of the electron current due to the inversion channel, the conduction of the electron current and the hole current due to the PN junction.
Referring to
The insulating layer 500 may be disposed in contact with the epi layer 200, the P region 300, and the N+ region 400. For example, the insulating layer 500, as shown in
Referring to
Referring to
The P-well region 800 may be located between the epi layer 200 and the P region 300 within the epi layer 200. In addition, the P-well region 800 may be located in a trench structure within the epi layer 200. The P-well region 800 may be located on the same line as the upper surface of the epi layer 200, an extension line of the upper surface of the P region 300, and an extension line of the upper surface of the N+ region 400.
The P-well region 800 may be formed through an ion implantation process.
The P-well region 800 may include a P type semiconductor material, for example P type silicon carbide (SiC), P type gallium nitride (GaN), P type gallium oxide (Ga2O3), P type diamond, P type silicon (Si), P type gallium arsenide (GaAs), P type germanium (Ge), P type aluminum nitride (AlN), or the like.
An N region 900 may be located between the P-well region 800 and the P region 300. The N region 900 may include the same material as the epi layer 200.
In the semiconductor device 30 with the structure, the P region 300 may be, for example, a P+ type.
The anode 600 is disposed on the P region 300, the N+ region 400, and the insulating layer 500, and the cathode 700 may be spaced apart in the same layer as the anode 600.
Referring to
Referring to
In the semiconductor device 40, the substrate 100 may be a P+ type substrate, and the epi layer 200 may be a P− type epi layer, for example.
An N-well region 850 may be disposed between the epi layer 200 and the P region 300 in the epi layer 200. In addition, the N-well region 850 may be located on the same line as the upper surface of the epi layer 200, the upper surface of the P region 300, and the upper surface of the N+ region 400.
The N-well region 850 may be formed through an ion implantation process.
The N-well region 850 may include an N-type semiconductor material, for example N-type silicon carbide (SiC), N-type gallium nitride (GaN), N-type gallium oxide (Ga2O3), N-type diamond, and N-type silicon (Si), N-type gallium arsenide (GaAs), N-type germanium (Ge), N-type aluminum nitride (AlN), or the like.
In the semiconductor device 40, the P region 300 may be, for example, a P+ type.
The anode 600 may be disposed on the P region 300, the N+ region 400, and the insulating layer 500, and the cathode 700 may be spaced apart in the same layer as the anode 600.
Referring to
Referring to
For example, the semiconductor device 50 may include two N+ regions 400 and two insulating layers 500, respectively.
Referring to
Referring to
For example, the semiconductor device 60 may include two N+ regions 400 and two insulating layers 500, respectively.
Referring to
Hereinafter, a method for manufacturing a semiconductor device according to an embodiment is described.
Specifically, a method of manufacturing the semiconductor device 10 shown in
Referring to
Referring to
When forming the P region 300, before the ion implantation, a mask 500′ for patterning the P region 300 may be disposed on the epi layer 200. The mask 500′ may include the same material as the insulating layer 500. After forming the P region 300, the mask 500′ may be not removed. Rather, the mask 500′ be maintained and thus formed as the insulating layer 500.
Referring to
When forming the N+ region 400, before the ion implantation, a mask 550 for patterning the N+ region 400 may be disposed on the P region 300. The mask 550 may be removed after forming the N+ region 400.
Referring to
Referring to
Referring to
Referring to
When forming the P region 300, before the ion implantation, for patterning the P region 300, the mask 550 may be disposed on the epi layer 200. The mask 550 may be removed after forming the P region 300.
Referring to
When forming the N+ region 400, before the ion implantation, for patterning the N+ region 400, the mask 550 on the epi layer 200 and the P region 300 may be disposed. The mask 550 may be removed after forming the N+ region 400.
Referring to
Referring to
The semiconductor device 20 shown in
The semiconductor device 30 shown in
The semiconductor device 40 shown in
The semiconductor device 50 shown in
The semiconductor device 60 shown in
Hereinafter, example embodiments are illustrated in more detail with reference to examples. However, these embodiments are illustrative, and the scope of the present disclosure is not limited thereto.
Example 1 is a semiconductor device manufactured to have a structure shown in
Each of the semiconductor devices of Example 1 and Comparative Example 1 were measured with respect to a turn-on voltage and on-state current density, and the results are shown in Table 1 and
The turn-on voltage was measured at current density of 0.33 A/cm2, and the on-state current density was measured at each forward voltage of 1.5 V, 4.0 V, and 10 V.
Referring to Table 1 and
Specifically, in Example 1, compared with Comparative Example 1, the turn-on voltage is decreased to 98.7% and reaches almost 0 V. In addition, the decreased turn-on voltage and removal of a cut-in voltage increased usable regions, so that the semiconductor device according to some embodiments might be applied in more various fields. For reference, if an operating point is below a turn-on voltage, it is impossible to use a semiconductor device.
In addition, in Example 1, compared with Comparative Example 1, on-state current density is increased by at least 26.6%, which leads to conduction of an electron current by an inversion channel and conduction of the electron current and a hole current by PN junction. As a result, an on-state current in Example 1 is increased. In addition, in Example 1, compared with Comparative Example 1, a chip area was reduced by 21.1%, improving the number of semiconductor devices per unit wafer and a yield of the semiconductor devices and thereby, resulting in cost reduction.
While inventive concepts of the present disclosure have been described in connection with example embodiments, it should be understood that the present disclosure is not limited to the disclosed embodiments. On the contrary, the present disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0178629 | Dec 2023 | KR | national |
