Patent Application
20080135976
This application claims priority from Japanese Patent Application Number JP2006-330148 filed Dec. 7, 2006, the content of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly relates to a high-frequency semiconductor device in which reduction in a capacitance of an insulating region is achieved and a method of manufacturing the high-frequency semiconductor device.
2. Description of the Related Art
In a semiconductor device used in a high-frequency band, particularly, an ultra-high frequency semiconductor device operated in a GHz band or higher, reduction in a stray capacitance of electrode wiring is demanded for improving high-frequency characteristics such as PG (Power Gain) characteristics. Particularly, since a bonding pad has a large area immediately below an electrode, it is necessary to reduce the stray capacitance of the bonding pad. Thus, in an ultra-high frequency transistor and the like, a thickness of an oxide film immediately below the bonding pad is increased by use of a LOCOS (local oxidation of silicon) method, a shallow-etching LOCOS method or the like to reduce the stray capacitance. This technology is described for instance in Japanese Patent Application Publication No. 2005-51160.
However, in the case where a thick oxide film is formed by use of the LOCOS method, there are problems such as an increase in defects due to an increase of a bird's beak in size, an increase in defects caused by a long period of high-temperature oxidation, and an increase in the amount of impurities in a high-concentration substrate to be diffused into a low-concentration epitaxial layer. In consideration of the problems as described above, the limit of the thickness of the oxide film that can be currently used in the ultra-high frequency semiconductor device is about 12,000 Å.
Moreover, although a step coverage can be reduced by use of the shallow-etching LOCOS method, the thickness is similarly limited to about 12,000 Å due to an increase in defects caused by an increase of a bird's beak in size or an increase in defects caused by an increase in oxidation time.
Furthermore, there has been also known a method for reducing an area of a first layer electrode portion having a large stray capacitance and for increasing an area of a second layer electrode portion having a relatively small stray capacitance, by employing a multilayer electrode wiring structure. However, when the multilayer electrode wiring structure is used, the number of processes is increased. Moreover, an interlayer insulating film is required between the first layer electrode portion and the second layer electrode portion. It is desirable to use a nitride film as the interlayer insulating film because of its denseness. However, since the nitride film has a high permittivity, a stray capacitance thereof is larger than that in an oxide film having the same thickness. Thus, it is necessary to increase a thickness of the nitride film.
The invention provides a semiconductor device including a semiconductor layer having an element region and an insulating region. The device also includes a semiconductor element formed in the element region. The insulating region includes an insulating film formed in the semiconductor layer to define a void.
The invention also provides a method of manufacturing a semiconductor device. The method includes providing a semiconductor layer, forming a trench in the semiconductor layer, forming an insulating film in the trench so as not to fill the trench completely so that a void is formed in the trench, forming a cover film on the trench, and forming an semiconductor element in the semiconductor layer outside the trench.
The invention provides another method of manufacturing a semiconductor device. The method includes providing a semiconductor layer, forming a plurality of trenches in the semiconductor layer; thermally oxidizing inside walls of the trenches so as to grow an insulating film so that voids are formed in the trenches, forming a cover film on the trenches, and forming an semiconductor element in the semiconductor layer outside the trenches. The oxidation of the inside walls of the trenches is performed so that portions of the semiconductor layer between the trenches are completely oxidized.
The invention further provides a semiconductor device including a semiconductor substrate, a semiconductor element formed on the substrate, an electrode pad formed on the substrate and connected to the semiconductor element, and an insulating region formed in the substrate under the electrode pad and having an insulating portion and an void portion defined by the insulating portion.
With reference to
A semiconductor device of this embodiment includes a semiconductor layer 11, an element region 12 and an insulating region 18. In the element region 12, for example, a Schottky barrier diode, a bipolar transistor and the like are provided.
With reference to
Moreover, a wiring electrode (an anode electrode) 14 connected to the element region 12 is provided above the surface of the semiconductor layer 11, and an electrode (a cathode electrode) 13 is provided on a back surface. Furthermore, on the semiconductor layer 11 outside the element region 12, an electrode pad 16 is provided, which is connected to the wiring electrode 14.
In the semiconductor layer 11 below the electrode pad 16, the thick insulating region 18 is disposed. The insulating region 18 is provided in an area approximately overlapping with the electrode pad 16 as indicated by a dashed line in
In this case, an element region 12 is provided near a center of an electrode pad 16. In a semiconductor layer 11 around the element region 12, a thick insulating region 18 is disposed. The insulating region 18 is provided so as to approximately overlap with the electrode pad 16 except for a portion in which the element region 12 is provided.
Moreover, on a surface of the semiconductor layer 11, wiring electrodes 14 and 15 are provided, which are connected to the element region 12, respectively. The wiring electrodes 14 and 15 are an emitter electrode and a base electrode, respectively.
Furthermore, on the semiconductor layer 11 outside the element region 12, electrode pads 16 and 17 are provided, which are connected to the wiring electrodes 14 and 15, respectively.
In the semiconductor layer 11 below the electrode pads 16 and 17, thick insulating regions 18 and 19 are disposed. The insulating regions 18 and 19 are provided in areas approximately overlapping with the electrode pads 16 and 17 as indicated by broken lines in
With reference to
The insulating region 18 has an insulating film 22 and void parts 23. Although a manufacturing method will be described later, the insulating film 22 is a thermal oxide film formed by providing trenches 21 in the semiconductor layer 11 and oxidizing insides thereof. A plurality of the trenches are provided so as to be spaced apart from each other by a predetermined distance below the electrode pad 16. The thermal oxide film 22 does not completely fill up the insides of the trenches 21, and the void parts 23 are formed in approximately center portions of the trenches 21, respectively. Meanwhile, the semiconductor layer 11 between the adjacent trenches 21 is thermally oxidized from both sides, and the plurality of trenches 21 are integrated by the thermal oxide film 22. Specifically, the thermal oxide film 22 and the plurality of void parts 23 spaced apart from each other constitute the insulating region 18.
On the insulating region 18, a cover film 24 is provided. The cover film 24 is another insulating film formed by use of a deposition method such as CVD, and is an oxide film, for example.
Alternatively, the cover film 24 is, for example, a metal film such as aluminum (Al) formed by use of a physical deposition method such as vapor deposition and sputtering.
By providing the cover film 24 formed by use of the deposition method on the insulating region 18 as described above, upper portions (near the surface of the semiconductor layer 11) of the void parts 23 are continuously covered with the cover film 24. The film formed by use of the deposition method generally has poor step coverage regardless of the insulating film and the metal film. In this embodiment, the cover film 24 is formed to cover the insulating 18 with poor step coverage. Thus, the void parts 23 that have been formed in the insulating film 18 remain being empty space.
The insulating region 18 can be controlled by a depth of each of the trenches 21. Specifically, even if the trench 21 is formed to have a depth of, for example, 7 μm to 8 μm, the inside thereof can be thermally oxidized.
As to oxidation conditions in this event, oxidation time for a normal LOCOS method may be adopted. Moreover, occurrence of crystal defects caused by a long period of high-temperature oxidation can be suppressed to the same level as that in a normal LOCOS oxidation method.
Therefore, the thick insulating region 18 can be formed without causing the crystal defects or thermal strain in the semiconductor layer 11. For example, in the surface of the semiconductor layer 11 below the wiring electrode 14, a field oxide film 20 (thickness: about 12,000 Å) is provided, which is formed by use of the LOCOS method. However, the insulating region 18 in this embodiment can be formed to have a thickness six to seven times larger than that of the field oxide film. Thus, particularly, a stray capacitance (a capacitance between the electrode pad 16 and an unillustrated back surface electrode (for example, a collector electrode)) below the electrode pad 16 can be significantly reduced.
Furthermore, in this embodiment, the void parts 23 are provided in the insulating region 18. A width of each of the void parts 23 is (although varying depending on a thermal oxidation state), for example, about 0.1 μm to 0.5 μm (here, 0.2 μm). Moreover, a relative permittivity of the void parts 23 is about “1”. Thus, it is possible to further contribute to reduction in the stray capacitance below the electrode pad 16.
Note that, when an insulating film is adopted as the cover film 24, the electrode pad 16 is formed by further providing a metal layer such as aluminum on the cover film 24. Meanwhile, when a metal layer such as aluminum is adopted as the cover film 24, the electrode pad can be formed by use of the cover film 24.
In this embodiment, the thermal oxide film 22 is formed on the insides of the trenches 21 and in the semiconductor layer 11 on the outsides of the trenches 21 by thermal oxidation of the trenches 21. In this event, the thermal oxide film 22 grown on the insides of the trenches 21 does not fill up the trenches 21. Moreover, a distance between the adjacent trenches 21 and an opening width thereof are selected so that the semiconductor layer 11 between the adjacent trenches 21 is completely insulated by the thermal oxide film 22 grown outward in the semiconductor layer 11. Specifically, an opening width w1 of each of the trenches 21 is set larger than a distance w2 between the adjacent trenches 21, and the void parts 23 (see
Technically, a ratio between a proportion of the oxide film grown toward the inside of the silicon substrate and a proportion of the oxide film grown toward the outside of the silicon substrate is 0.9/1.1. Thus, in the case where a ratio between the width w1 of the trench 21 and the distance (a width of the semiconductor layer 11) w2 between the trenches 21 is set to w2/w1=0.9 μm/1.1 μm, when the trenches 21 are filled up with the grown thermal oxide film 22, the portions of the thermal oxide film grown toward the inside of the semiconductor layer 11 also come into contact with each other. Therefore, in this embodiment, by setting w2/w1<0.9 μm/1.1 μm, the semiconductor layer 11 between the adjacent trenches 21 can be completely thermally oxidized from both sides while forming the void parts 23 in the trenches 21.
As an example, the opening width w1 of the trench 21 is 1.5 μm and the distance w2 between the trenches 21 is 0.8 μm.
Next, with reference to
The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which an element region and an insulating region are formed in a semiconductor layer. The method includes the steps of: forming trenches in the semiconductor layer outside a formation region of the element region; forming an insulating film in the trenches so as not to completely fill up the trenches; forming a cover film over the trenches and forming the insulating region having void parts therein; and forming the element region in the semiconductor layer.
Note that
First step (
A high-concentration silicon semiconductor substrate 10 having a semiconductor layer 11 formed thereon by epitaxial growth or the like, for example, is prepared. Thereafter, trenches are formed in the semiconductor layer 11 in a formation region of an electrode pad outside the formation region of the element region.
First, as shown in
Next, resist patterning is performed. First, a photoresist is applied onto the entire surface. Thereafter, the photoresist is exposed and developed according to a mask having a pattern as shown in
Subsequently, as shown in
Furthermore, as shown in
Second step (
Thereafter, thermal oxidation is performed in a state of leaving the oxide film 33 as shown in
Specifically, thermal oxidation is performed in a steam atmosphere of 1100° C. for 170 minutes, for example, to form thermal oxide films 22. The oxidation is extended toward inside of the semiconductor layer 11 and is also grown in the trenches 21 on the outside of the semiconductor layer 11. Accordingly, as shown in
Note that, when a width of each of the void parts 23′ is too large after the thermal oxidation in this step, an insulating film 22′ may be additionally formed. The void parts 23′ having the openings in the upper sides are covered with a cover film in a subsequent step. However, if the width of the void part 23′ is too large after the thermal oxidation in this step, there is a risk that the inside thereof is filled up with the cover film. Thus, the void parts 23′ can be reduced to a desired width by deposition of a TEOS film 22′ or the like as shown in
Third step (
A cover film 24 such as an insulating film and a metal film is formed over the trenches 21 by use of a deposition method. Specifically, an oxide film 24a is deposited by low-temperature CVD (Chemical Vapor Deposition) or by CVD using decomposition of TEOS. The cover film 24a has a thickness of, for example, about 8000 Å (
Alternatively, a metal film 24b such as aluminum is formed, for example, by use of a physical deposition method. The physical deposition method is vapor deposition or sputtering. Although described later, the metal film 24b may be used to form an electrode pad 16. In this case, the metal film 24b has a thickness of about 1 μm when gold (Au) is adopted, for example, in the case of a bipolar transistor or has a thickness of about 2.5 μm when aluminum (Al) is adopted, for example, in the case of a Schottky barrier diode (
Accordingly, upper sides (near the surface of the semiconductor layer 11) of the trenches 21 are continuously covered with the cover film 24. Thus, an insulating region 18 having a plurality of void parts 23 disposed therein is formed.
The film formed by use of the deposition method generally has poor step coverage. In this embodiment, the cover film 24 is formed to cover the insulating 18 with poor step coverage. Thus, the void parts 23 that have been formed in the insulating film 18 remain being empty space.
Each of the void parts 23 has a width of, for example, about 0.1 μm to 0.5 μm (here, 0.2 μm).
The depth of the trench 21 is, for example, 7 μm to 8 μm, which is much larger than a thickness limit (for example, 12,000 Å) of an oxide film formed by use of a LOCOS method. Thus, it is possible to significantly contribute to reduction in a capacitance below the electrode pad 16.
In addition, since a relative permittivity of the void parts 23 is about “1”, the capacitance below the electrode pad 16 can be further reduced.
Fourth step (
In manufacturing of a semiconductor device for high-frequency use, the thermal oxide film 22 in the insulating region 18 having a thickness of about 8 μm is formed in an arrangement portion of the electrode pad as described above. Moreover, by use of a normal LOCOS method, a field oxide film is formed on the surface of the semiconductor layer 11 to be a formation region of a wiring electrode, for example. Subsequently, after the cover film 24 is formed, diffusion regions such as an emitter region 12a and a base region 12b are formed, for example, to form an element region 12.
Next, for example, a wiring electrode material such as aluminum is deposited by sputtering or the like to form electrode pads 16 and 17 on the insulating regions 18 and 19 by resist patterning. Specifically, the electrode pads 16 and 17 approximately overlap with the insulating regions 18 and 19 and are connected to the element region 12. Moreover, at the same time, wiring electrodes 14 and 15 are also formed (by use of the same metal layers as those of the electrode pads 16 and 17).
Particularly, in the Schottky barrier diode, when the insulating region 18 is provided to reduce the capacitance below the electrode pad 16, the electrode pad 16 may be formed by use of the metal film 24b.
Moreover, in the case of the Schottky barrier diode as shown in
The Schottky metal layer 25 may be provided only in the element region 12 and may be formed to have the same pattern as that of the wiring electrode layer 14. However, in the latter case, when the metal film 24b is adopted as the cover film 24 as described above, the Schottky metal layer 25 (thickness: for example, 2000 Å) is disposed below the cover layer 24b in
In this embodiment, the description was given by taking, as an example, the case where the insulating region 18 is provided below the electrode pad 16 for reducing the capacitance. However, without being limited thereto, the insulating region 18 of this embodiment may be formed instead of LOCOS oxide films for element isolation (for example, the field oxide films 20 at both ends in
According to this embodiment, the insulating region having the void parts therein is provided by oxidizing the insides of the trenches provided in the silicon semiconductor layer so as not to completely fill up the trenches. Specifically, a required thickness of the insulating region can be achieved by controlling the depth of the trenches.
As to oxidation conditions in this event, oxidation time for a normal LOCOS method may be adopted. Moreover, occurrence of crystal defects caused by a long period of high-temperature oxidation can be suppressed to the same level as that in a normal LOCOS oxidation method.
For example, by forming the trenches to have a larger depth (for example, 12,000 Å or more), the insulating region having a thickness larger (for example, six to seven times larger) than that of an oxide film formed by oxidation using the normal LOCOS method can be formed. Furthermore, the capacitance of the insulating region can be reduced by the void parts formed inside the trenches.
Particularly, by providing, below the electrode pad, the insulating region as thick as, for example, about 7 to 8 μm, a stray capacitance in the electrode wiring portion can be significantly reduced. Thus, high-frequency characteristics of a high-frequency semiconductor device can be significantly improved. Therefore, the high-frequency characteristics such as power gain characteristics can be improved. Moreover, since the insulating region having a sufficient thickness can be obtained, a single-layer structure is enough for electrode wiring. Thus, manufacturing steps can be simplified.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-330148 | Dec 2006 | JP | national |
