Semiconductor device and related fabrication method

Abstract

Embodiments of the invention provide a semiconductor device and a related method of fabricating a semiconductor device. In one embodiment, the invention provides a semiconductor device comprising a first gate electrode comprising a lower silicon pattern and an upper silicon pattern and disposed on an active region of a semiconductor substrate, wherein the upper silicon pattern has the same crystal structure as the lower silicon pattern and the active region is defined by a device isolation layer. The semiconductor device further comprises a gate insulating layer disposed between the active region and the first gate electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will be described herein with reference to the accompanying drawing, in which like reference symbols indicate like or similar elements throughout. In the drawings, thicknesses of layers and regions may be exaggerated for clarity. In the drawings:

FIG. 1 is a schematic cross-sectional view of a conventional MOS transistor;

FIGS. 2 and 3 are schematic cross-sectional views of another conventional nonvolatile memory device;

FIGS. 4A and 4B are cross-sectional views illustrating a method for forming the non-volatile memory device illustrated in FIG. 3;

FIG. 5 is a schematic cross-sectional view of a semiconductor device in accordance with an embodiment of the invention;

FIG. 6 is a schematic cross-sectional view of a semiconductor device in accordance with another embodiment of the invention;

FIG. 7 is a schematic cross-sectional view of a semiconductor device in accordance with another embodiment of the invention;

FIGS. 8A through 8E are cross-sectional views illustrating a method for forming a semiconductor device in accordance with another embodiment of the invention;

FIGS. 9A through 9G are cross-sectional views illustrating a method for forming a semiconductor device in accordance with another embodiment of the invention;

FIGS. 10A and 10B are cross-sectional views illustrating a method for forming a semiconductor device in accordance with another embodiment of the invention;

FIGS. 11A and 11B are cross-sectional views illustrating a method for forming a semiconductor device in accordance with another embodiment of the invention;

FIGS. 12A through 12G are cross-sectional views illustrating a method for forming a semiconductor device in accordance with another embodiment of the invention; and

FIGS. 13A and 13B are cross-sectional views illustrating a method for forming a semiconductor device in accordance with another embodiment of the invention.

Claims

1. A semiconductor device comprising: a first gate electrode comprising a lower silicon pattern and an upper silicon pattern and disposed on an active region of a semiconductor substrate, wherein the active region is defined by a device isolation layer; anda gate insulating layer disposed between the active region and the first gate electrode,wherein the upper silicon pattern has the same crystal structure as the lower silicon pattern.

2. The semiconductor device of claim 1, wherein the lower silicon pattern is wider than the upper silicon pattern.

3. The semiconductor device of claim 1, further comprising: a second gate electrode disposed on the first gate electrode, the active region, and at least a portion of the device isolation layer; andan inter-gate insulating layer disposed between the first gate electrode and the second gate electrode.

4. The semiconductor device of claim 3, further comprising a buffer insulating layer pattern disposed between an upper surface of the lower silicon pattern and the inter-gate insulating layer.

5. The semiconductor device of claim 4, further comprising a buffer spacer disposed between a sidewall of the lower silicon pattern and the inter-gate insulating layer.

6. The semiconductor device of claim 3, wherein at least a portion of a lower surface of the second gate electrode is disposed lower than a lower surface of the first gate electrode.

7. A semiconductor device comprising: a memory cell transistor disposed in a cell region of a semiconductor substrate, the memory cell transistor comprising: a floating gate electrode disposed on a first active region of the semiconductor substrate and comprising a first lower silicon pattern and a first upper silicon pattern, wherein the first upper silicon pattern has the same crystal structure as the first lower silicon pattern and the first active region is defined by a device isolation layer;a first gate insulating layer disposed between the first active region and the floating gate electrode;a control gate electrode disposed on the floating gate electrode, the first active region, and the device isolation layer; andan inter-gate insulating layer disposed between the floating gate electrode and the control gate electrode; anda peripheral circuit transistor disposed in a peripheral region of the semiconductor substrate, the peripheral circuit transistor comprising: a peripheral circuit gate electrode disposed on a second active region of the semiconductor substrate and comprising a second lower silicon pattern and a second upper silicon pattern, wherein the second upper silicon pattern has the same crystal structure as the second lower silicon pattern; anda second gate insulating layer disposed between the second active region and the peripheral circuit gate electrode.

8. The semiconductor device of claim 7, wherein the first lower silicon pattern is wider than the first upper silicon pattern and the second lower silicon pattern is as wide as or wider than the second upper silicon pattern.

9. The semiconductor device of claim 7, wherein the first lower silicon pattern is as wide as or wider than the first active region and the second lower silicon pattern is as wide as or wider than the second active region.

10. The semiconductor device of claim 7, further comprising a buffer insulating layer pattern disposed between an upper surface of the first lower silicon pattern and the inter-gate insulating layer.

11. The semiconductor device of claim 10, further comprising a buffer spacer disposed between a sidewall of the first lower silicon pattern and the inter-gate insulating layer.

12. The semiconductor device of claim 7, wherein at least a portion of a lower surface of the control gate electrode is disposed lower than a lower surface of the floating gate electrode.

13. A method for forming a semiconductor device, the method comprising: forming a gate electrode on a semiconductor substrate by: forming a lower silicon pattern on the semiconductor substrate;forming a device isolation layer having an upper surface disposed higher than the upper surface of the lower silicon pattern; andgrowing an upper silicon pattern from the lower silicon pattern through selective epitaxial growth; andforming a source/drain region on a first side of the gate electrode and in an active region of the semiconductor substrate.

14. The method of claim 13, wherein: forming the lower silicon pattern comprises: forming a preliminary gate insulating layer and a lower silicon layer on the semiconductor substrate;forming a trench mask on the lower silicon layer;etching the lower silicon layer, the preliminary gate insulating layer, and the semiconductor substrate using the trench mask as an etch mask to form trenches defining the active region, a gate insulating layer, and a lower silicon pattern disposed on the active region;forming the device isolation layer comprises: forming a preliminary device isolation layer filling the trenches;performing a planarization process exposing the trench mask to form the device isolation layer, wherein upper portions of the device isolation layer are adjacent to sides of at least a portion of the trench mask; andthe method further comprises removing the trench mask.

15. The method of claim 14, wherein the trench mask is formed from at least a first material and the device isolation layer is formed from at least a second material, wherein the first and second materials have etching selectivities relative to one another.

16. A method for forming a semiconductor device, the method comprising: forming a floating gate electrode in a cell region of a semiconductor substrate and a peripheral circuit gate electrode in a peripheral region of the semiconductor substrate by: forming first and second lower silicon patterns on a semiconductor substrate, wherein the first lower silicon pattern is formed in the cell region and the second lower silicon pattern is formed in the peripheral region; andgrowing first and second upper silicon patterns from the first and second lower silicon patterns, respectively, through selective epitaxial growth;etching a device isolation layer;sequentially forming a preliminary inter-gate insulating layer and a control gate conductive layer on the semiconductor substrate; andpatterning at least one portion of the control gate conductive layer disposed in the peripheral region and at least one portion of the preliminary inter-gate insulating layer disposed in the peripheral region to form a control gate electrode and an inter-gate insulating layer.

17. The method of claim 16, wherein: forming the first and second lower silicon patterns comprises: forming a preliminary gate insulating layer and a lower silicon layer on the semiconductor substrate;forming a trench mask on the lower silicon layer; andetching the lower silicon layer, the preliminary gate insulating layer, and the semiconductor substrate using the trench mask as an etch mask to form trenches defining first and second active regions of the semiconductor substrate, to form a first gate insulating layer and a first lower silicon pattern each disposed on the first active region, and to form a second gate insulating layer and a second lower silicon pattern each disposed on the second active region; andthe method further comprises: forming a device isolation layer having upper surfaces disposed higher than an upper surface of the first lower silicon pattern and higher than an upper surface of the second lower silicon pattern by: forming a preliminary device isolation layer filling the trenches; andperforming a planarization process to expose the trench mask and thereby form the device isolation layer, wherein upper sidewalls of the device isolation layer are disposed adjacent to sidewalls of portions of the trench mask; andremoving the trench mask to expose the upper sidewalls of the device isolation layer.

18. The method of claim 17, wherein the trench mask is formed from at least a first material and the device isolation layer is formed from at least a second material, wherein the first and second materials have etching selectivities relative to one another.

19. The method of claim 16, wherein forming the first and second lower silicon patterns comprises: forming a trench mask on the semiconductor substrate;etching the semiconductor substrate using the trench mask as an etch mask to form trenches defining first and second active regions;forming a preliminary device isolation layer filling the trench;performing a planarization process exposing the trench mask to form a device isolation layer having upper sidewalls adjacent to sidewalls of portions of the trench mask;removing the trench mask to form a first gap region exposing an upper surface of the first active region and a second gap region exposing an upper surface of the second active region;forming a first gate insulating layer on the first active region;forming a second gate insulating layer on the second active region;forming a preliminary lower silicon layer filling the first and second gap regions;performing a planarization process exposing the device isolation layer to form first and second lower silicon layers; andetching the first and second lower silicon layers to expose upper sidewalls of the device isolation layer.

20. The method of claim 19, wherein forming the trench mask comprises sequentially forming a silicon oxide layer and a silicon nitride layer.

21. The method of claim 20, wherein: removing the trench mask comprises sequentially removing the silicon nitride layer and the silicon oxide layer; andremoving the silicon oxide layer comprises etching upper sidewalls of the device isolation layer such that the first gap region is wider than the first active region over which it is disposed and second gap region is wider than the second active region over which it is disposed while removing the silicon oxide layer.

22. The method of claim 16, further comprising: after forming first and second lower silicon patterns: forming a molding layer on the semiconductor substrate; andetching the molding layer to form molding spacers adjacent to upper sidewalls of the device isolation layer, wherein the molding spacers expose a portion of an upper surface of the first lower silicon pattern and a portion of an upper surface of the second lower silicon pattern,wherein growing the first and second upper silicon patterns from the first and second lower silicon patterns, respectively, comprises growing the first and second upper silicon patterns from the exposed portion of the upper surface of the first lower silicon pattern and the exposed portion of the upper surface of the second lower silicon pattern, respectively.

23. The method of claim 22, wherein the device isolation layer is formed from at least a first material and the molding layer is formed from at least a second material, wherein the first and second materials have etching selectivities relative to one another.

24. The method of claim 23, wherein etching the device isolation layer also etches only portions of each molding spacer, thereby forming buffer insulating layer patterns on the first and second lower silicon patterns.

25. The method of claim 22, wherein etching the device isolation layer also completely removes the molding spacers.

26. The method of claim 16, further comprising forming a molding mask exposing at least a portion of an upper surface of each of the first and second lower silicon patterns, wherein growing first and second upper silicon patterns from the first and second lower silicon patterns, respectively, comprises growing the first and second upper silicon patterns from the at least a portion of the upper surface of each of the first and second lower silicon patterns exposed by the molding mask.

27. The method of claim 26, wherein the molding mask exposes a portion of the upper surface of the first lower silicon pattern and all of the upper surface of the second lower silicon pattern.

28. The method of claim 16, further comprising: after forming the floating gate electrode but before forming the preliminary inter-gate insulating layer: forming a buffer insulating layer on the semiconductor substrate; andetching the buffer insulating layer to form a buffer insulating layer pattern on an upper surface of each of at least one of the first and second lower silicon patterns, and to form a buffer spacer adjacent to a sidewall of each of the at least one of the first and second lower silicon patterns.