Patent Application
20060220112
1. Technical Field
The present invention relates generally to semiconductor device fabrication, and more particularly to a method and structure for retarding dopant-enhanced diffusion in strained silicon/silicon-germanium (SSi/SiGe) substrates by implanting a diffusion retardant in the substrate.
2. Related Art
Strained silicon (Si) complementary metal oxide semiconductor (CMOS) devices with a strained Si channel on a relaxed silicon-germanium (SiGe) buffer layer offer better device performance over conventional Si CMOS because of the enhancement in both channel electron and hole mobilities, and have been demonstrated for devices as small as about 60 nm. However, for devices at about 60 nm or below, an extension junction depth (Xj) 30 nm or below would be needed. The diffusion of a dopant in SiGe can form parasitic barriers at the heterojunction in a heterojunction bipolar transistor (HBT). More importantly, the junction slope (Xjs) near the channel region should be abrupt (<6 nm/decade), and the dopant concentration at the extension should be approximately 1 E20/cm3.
However, as described in co-pending application, entitled “Method for Slowing Down Dopant-enhanced Diffusion Substrates and Devices Fabricated Therefrom,” U.S. Ser. No. 10/627,753, filed Jul. 28, 2003, which is hereby incorporated by reference, shallow junction requirements are difficult to achieve for a dopant (e.g., arsenic) junction in N-type metal oxide semiconductor (NMOS) devices in strained Si—SiGe substrates due to significant arsenic-enhanced diffusion. That is, experimentally, it has been found that arsenic dopant diffusivity increases exponentially with the percentage of the germanium (Ge) content in the strained Si—Si1-xGex buffer layer. Thus, enhanced arsenic dopant diffusion in strained Si—SiGe substrates becomes a significant roadblock for generating ultra-shallow junctions for a small (e.g., about sub-50 nm) NMOS device in strained Si substrates where high %Ge (e.g., >about 20%) is used for higher electron and hole mobility for improved device performance. In addition, for a sub-50 nm device, the enhanced lateral arsenic dopant diffusion will short-circuit the source and drain regions of the NMOS device, and will render the device totally inoperable. That is, high arsenic dopant concentrations are immediately below the center of the gate (e.g., a polysilicon gate). This high concentration of dopant underneath the gate creates shorting due to enhanced arsenic junction diffusion from the extension junction region to the gate region. There had been no known techniques (or resulting structures) for slowing down the arsenic enhanced diffusion in strained Si/SiGe or strained Si1-xGex/Si device substrates prior to the co-pending application.
In order to address this situation, the co-pending application discloses co-implanting, i.e., implanting in series, a dopant and a species to slow diffusion. In that application, the gate was already formed and used to protect the channel. It has now been recognized, however, that the co-implantation through the strained silicon cap causes defects, which increases external resistance and leakage. In addition, due to Ge and dopant diffusion into the silicon cap and channel area, the strained Si—SiGe substrate cannot withstand high temperature anneals to remove implantation damage.
In view of the foregoing, there is a need in the art for an improved method and structure so formed to address the problems of the related art.
The invention includes methods and a structure formed for retarding diffusion of a dopant into a channel of a strained Si—SiGe CMOS device. The methods form a diffusion retardant region in a substrate including at least one diffusion retardant species such as xenon (Xe), and then form a channel over the diffusion retardant region. Each step is conducted prior to formation of a gate on the substrate. As a result, if necessary, the diffusion retardant region can be annealed and cleaned or etched to remove defects in the substrate to reduce external resistance and leakage of devices. The diffusion retardant region positioned under the channel slows down the diffusion of dopant, e.g., arsenic (As). The invention is also applicable to other substrates.
A first aspect of the invention is directed to a method of forming a semiconductor device, the method comprising the steps of: forming a diffusion retardant region in a substrate, the region including at least one diffusion retardant species; and forming a channel layer over the diffusion retardant region, wherein each step is conducted prior to formation of a gate on the substrate.
A second aspect of the invention includes a semiconductor device comprising: a semiconductor substrate; a dopant formed in the substrate to define a channel; and a region formed under the channel, the region including at least one diffusion retardant species for retarding a diffusion of the dopant during formation of a gate over the channel.
A third aspect of the invention is related to a method of forming a semiconductor device, the method comprising the steps of: prior to formation of a gate on a substrate: a) forming a region in the substrate including at least one diffusion retardant species; b) annealing the substrate; c) forming a strained silicon layer over the substrate; and forming a channel over the region in the strained silicon layer.
The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention.
The embodiments of this invention will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein:
With reference to the accompanying drawings,
In a first step, as shown in
As shown in
Next, as shown in
As shown in finished form in
Due to the formation of diffusion retardant region 130, dopant-enhanced diffusion of, e.g., arsenic, into channel 174 is retarded during high temperature annealing steps conducted during device formation. The method prevents dopant diffusion in strained Si—SiGe substrates from becoming a significant roadblock for generating ultra-shallow junctions for a small NMOS device in strained Si substrates where a high percentage high of germanium (Ge) is used (e.g., > about 20%). In addition, short-circuiting of the source and drain regions of an NMOS device for a sub-50 nm devices is avoided. Since diffusion retardant region 130 is formed prior to device formation processing, defects caused by the creation of the region can be easily removed and high temperature anneals occur prior to the formation of the channel layer 160.
In an alternative embodiment, the above-described method is carried out using a pure bulk silicon substrate 100. That is, the diffusion retardant species 120 (
The above-described methods provide a mechanism to retard dopant-enhanced diffusion.
While this invention has been described in conjunction with the specific embodiments outlined above, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the embodiments of the invention as set forth above are intended to be illustrative, not limiting. Various changes may be made without departing from the spirit and scope of the invention as defined in the following claims.
