Claims
- 1. A method of producing a semiconductor device having a thin film resistor comprising chromium, silicon and nitrogen, formed on a substrate, said method being characterized in that said thin film resistor forming process consists essentially of the steps of preparing a target consisting essentially of chromium and silicon, wherein the weight percentage of the silicon to the total weight of the chromium and silicon is 41 to 51 weight %, and reactive sputtering a substrate, utilizing said target in an atmosphere of an inert gas containing 1-2% nitrogen gas so as to form a Cr—Si—N thin film having amorphous condition and having the same energy band construction as that of metal, and further characterized in that a thermal treatment is applied to said thin film resistor after said thin film resistor is formed, wherein said thermal treatment is carried out at a temperature not exceeding 500° C., by preventing a temperature in excess of 500° C. from being applied to said thin film resistor, so as to maintain said amorphous condition of said thin film resistor.
- 2. A method of producing a semiconductor device having a thin film resistor comprising chromium, silicon and nitrogen, formed on a substrate, said method comprising:a reactive sputtering step in which a Cr—Si target, consisting essentially of chromium and silicon, and the weight percentage of the silicon to the total weight of the chromium and silicon being 41 to 51 weight %, undergoes reactive sputtering in an atmosphere of an inert gas containing 1-2% nitrogen gas, so as to form a Cr—Si—N thin film having amorphous condition and having the same energy band construction as that of metal on said substrate; a patterning step in which said Cr—Si—N thin film formed on said substrate is etched to remove said film from a surface of said substrate except for a part of said surface of said substrate on which said Cr—Si—N thin film remains; a wiring step in which first, a conductive film is formed over the entire surface of said substrate utilizing a sputtering method and successive wirings are formed by etching said conductive film; and a sintering step in which said wirings are sintered, wherein a thermal hysteresis applied to said thin film resistor after said thin film resistor has been formed on said substrate, is restricted to less than 500° C., so as to maintain said amorphous condition of said thin film resistor.
Priority Claims (3)
Number |
Date |
Country |
Kind |
63-177536 |
Jul 1988 |
JP |
|
1-92610 |
Apr 1989 |
JP |
|
1-151284 |
Jun 1989 |
JP |
|
Parent Case Info
This is a continuation of application Ser. No. 07/680,011, filed on Apr. 2, 1991, which was abandoned upon the filing hereof which is a Continuation of Ser. No. 07/379,775, filed Jul. 14, 1989 abandoned.
US Referenced Citations (10)
Foreign Referenced Citations (6)
Number |
Date |
Country |
0101632 |
Feb 1984 |
EP |
50-038200 |
Apr 1975 |
JP |
53-25442 |
Mar 1978 |
JP |
60-261101 |
Dec 1985 |
JP |
3216960 |
Sep 1988 |
JP |
8300256 |
Jan 1983 |
WO |
Non-Patent Literature Citations (4)
Entry |
Wolf et al., “Silicon processing for the VLSI Era, vol. 1, Process Technology.”, Lattice Press, 1986, pp. 331-335.* |
Wolf, “Silicon Processing for The VSLI Era”, vol. 1 Process Technology, pp. 365-367, 1986.* |
IBM Technical Disclosure Bulletin, vol. 24, No. 6, Nov. 1981 pp. 2962-2963.* |
European Search Report and Annex, Application No. 89 11 2987. |
Continuations (2)
|
Number |
Date |
Country |
Parent |
07/680011 |
Apr 1991 |
US |
Child |
08/015268 |
|
US |
Parent |
07/379775 |
Jul 1989 |
US |
Child |
07/680011 |
|
US |