1. Field of the Invention
This application is based upon and claims the benefit of the priority of Japanese patent application No. 2011-274865, filed on Dec. 15, 2011, the disclosure of which is incorporated herein in its entirety by reference thereto. This invention relates to a device (semiconductor device) including a three-state buffer.
2. Description of Related Art
A three-state buffer, also termed a tri-state buffer, has a control terminal to receive a control signal that controls output enable/output disable of the buffer. An output of the three-state buffer is set to a low impedance or a high impedance depending on the value of the control signal. When the output is enabled, the output of the three-state buffer is High or Low voltage, depending on an input signal, whereas, when the output is disabled, the output of the three-state buffer is in a high-impedance state. In this manner, the output of the three-state buffer assumes three states. The three-state buffer is used e.g., in an output buffer of an input/output circuit wherein an output of the output buffer is set in a high-impedance state when a signal is received by the input/output circuit. Alternatively, the three-state buffer may be used as a driving buffer circuit connected to such as a common bus. For example, a control terminal OE of one of a plurality of driving buffers (three-state buffers) is activated to set one driving buffer to an output enable state, whilst the control terminals of the remaining driving buffers are deactivated, with the outputs of these remaining driving buffers being set in the high-impedance states. Still alternatively, the three-state buffer may be used in such a system in which outputs of a plurality of three state buffers with different current driving capabilities are connected in common to a single output terminal, and the three state buffers to be set to the output enable are selected to variably adjust current driving capability.
Japanese Patent Kokai Publication No. JP-S61-025326A discloses a three state buffer, in which a PMOS (P-channel MOS) transistor of a CMOS (Complementary MOS) buffer has a gate connected to an output of a NAND circuit and an NMOS (N-channel MOS) transistor of the CMOS buffer has a gate connected to an output of a NOR circuit. The CMOS buffer is composed by the PMOS transistor and an NMOS transistor connected between a power supply terminal and a ground terminal. The NAND circuit receives an output control signal and a signal output from a first inverter that receives and outputs an inverted version of the data input signal. The NOR circuit receives an inverted signal of the data input signal output from the first inverter and a signal output from a second inverter that inverts the output control signal. When the output control signal is in an activated state (High) and the data input signal is High, the output of the NAND circuit is High and the output of the NOR circuit is also High. The PMOS transistor is rendered non-conductive (turned off), while the NMOS transistor is rendered conductive (turned on), and hence the data output terminal goes Low. When the data input signal is Low, the output of the NAND circuit is Low, and the output of the NOR circuit also being Low. Hence, the PMOS transistor is rendered conductive (turned on), while the NMOS transistor is rendered non-conductive (turned off), so that the data output terminal goes High. When the output control signal is in a deactivated state (Low), the output of the NAND circuit is High, and the output of the NOR circuit is Low, irrespective of the value of the data input signal, so that both the NMOS transistor and the PMOS transistor are rendered non-conductive (turned off). In this configuration, the circuit configuration of a signal path connecting to the gate terminal of the PMOS transistor (logic gate configuration) differs from that of the signal path connecting to the gate terminal of the NMOS transistor.
Japanese Patent Kokai Publication No.JP-H08-116248A discloses a three state buffer in which a PMOS transistor of a CMOS transistor output circuit has a gate connected to an output of a NAND circuit and an NMOS transistor of the CMOS transistor has a gate connected to an output of an AND circuit. The NAND circuit receives an inner output signal and an output control signal. The AND circuit receives an output of an inverter that inverts the inner output signal and the output control signal. In the subject three state buffer, the circuit configuration of a signal path connected to the gate terminal of the PMOS transistor, differs from that of a signal path connected to the gate terminal of the NMOS transistor.
Japanese Patent Kokai Publication No. JP2001-24496A, which corresponds to U.S. Pat. No. 6,236,234B1 discloses an open-drain three state buffer in which a PMOS transistor of a CMOS transistor output circuit has a gate connected to an output of a NAND circuit and an NMOS transistor of the CMOS transistor output circuit has a gate connected to an output of an AND circuit. The NAND circuit receives an inner output signal and an output control signal. The AND circuit receives an output from an inverter that outputs an inverted version of the inner output signal and the output control signal. There is also provided an NMOS transistor having a gate connected to a second power supply between a connection node of the PMOS transistor and the NMOS transistor of the CMOS output circuit and an external output terminal. In this three state buffer, the circuit configuration of a signal path connecting to the gate terminal of the PMOS transistor differs from that of a signal path connecting to the gate terminal of the NMOS transistor.
Japanese Patent Kokai Publication No. JP-H08-8714A discloses a buffer circuit in which a PMOS transistor of a CMOS inverter has a gate connected to an output of two stages of inverters that receives an output of a first NAND circuit that receives a control signal and an input signal and an NMOS transistor of the CMOS inverter has a gate connected to an output of a first inverter that inverts an output of a second NAND circuit that receives the control signal and a signal from a second inverter that receives and inverts the input signal. In the this buffer circuit, a signal path connecting to the gate terminal of the PMOS transistor and that connecting to the gate terminal of the NMOS transistor are both composed by the NAND circuits and the inverters and have the logic matched to each other. However, they differ in the connection configuration and hence differ in signal propagation characteristics from the inner output terminals.
Japanese Patent Kokai Publication No. JP-H11-274906A shows a buffer circuit in which a PMOS transistor of a CMOS inverter has a gated connected to an output of a first inverter Iv1 that inverts an output of a first NOR circuit that receives a control signal HiZ and an input signal DOB and an NMOS transistor of the CMOS inverter has a gate connected to an output of a second NOR circuit that receives the control signal HiZ and an output of a second inverter Iv2 that inverts the input signal DOB. In the subject buffer circuit, a signal path connecting to the gate terminal of the PMOS transistor and that connecting to the gate terminal of the NMOS transistor are both composed by the NOR circuits and the inverters and have the logic matched to each other. However, they differ in the connection configuration and hence differ in signal propagation characteristics from the inner output terminals.
In the three state buffers, disclosed in the above mentioned Patent Literatures, the circuit configurations as well as the connection configurations of the circuits connecting respectively to gates of PMOS and NMOS transistors of the CMOS buffer differ from each other. Thus, the inventor has discovered that there appear difference in signal propagation characteristics between the signal path connecting to the gate of the PMOS transistor and that connecting to the gate of the NMOS transistor, for example, thus producing a difference in skew there-between. In addition, there may also be produced the difference in jitter there-between due to variations in the power supply voltages, ambient temperatures or fabrication processes.
In one aspect of this disclosure, there is provided a device that includes a first power line supplied with a first voltage as a first logic level, a second power line supplied with a second voltage as a second logic level, first and second input nodes supplied with first and second signals, respectively, first and second output nodes, and first and second gate circuits. The first gate circuit is coupled to the first and second power lines, the first and second input nodes and the first output node and configured to respond to an inactive level of the first signal to bring the first output node to a first selected one of the first and second logic levels irrespective of a level of the second signal and respond to an active level of the first signal to drive the first output node to a logic level controlled by the level of the second signal. The first logic circuit includes first and second transistors that are coupled in series between the first output node and the first power line, in which the first transistor makes response to at least one of the first and second signals to change between a conductive state and a non-conductive state, and the second transistor makes no response to any one of the first and second signals to keep a conductive state. On the other hand, the second gate circuit is coupled to the first and second power lines, the first and second input nodes and the second output node and configured to respond to the inactive level of the first signal to bring the second output node to a second selected one of the first and second logic levels irrespective of the level of the second signal and respond to the active level of the first signal to drive the second output node to a logic level that is equal to the logic level of the first output node. The second logic circuit includes third and fourth transistors that are coupled in series between the second output node and the first power line, in which each of the third and fourth transistors making response to at least one of the first and second signals to change between a conductive state and a non-conductive state.
Referring to
The third NAND circuit 113 includes first and second input terminals E and F to receive a signal INB output from the inverter 104 that receives and inverts an input signal IN and the power supply voltage VDD (fixed High level), respectively. The first NAND circuit 111 includes first and second input terminals A and B to receive an output signal of the third NAND circuit 113 and an output enable signal OE, respectively. The fourth NAND circuit 114 includes first and second input terminals G and H to receive the signal INB and the output enable signal OE, respectively. The second NAND circuit 112 includes first and second input terminals C and D to receive an output signal of the fourth NAND circuit 114 and the voltage VDD (fixed High level), respectively. Outputs of the first and second NAND circuits 111 and 112 are connected to the gates nodes PB and NB of the PMOS transistor 101 and the NMOS transistor 102, respectively. A two-input type NAND circuit outputs Low, when both of the two inputs terminals thereof are High, and outputs Low, when at least one of the two inputs terminals thereof is Low. Each of the NAND circuits 112 and 113, whose one input terminal is supplied with a High level, operates as an inverter that inverts a signal at the other input terminal to output the so inverted signal.
The following describes the operation of the three state buffer of
When the output enable signal OE is High and the input signal IN is Low, with INB being High, the output of the NAND circuit 113 is Low and hence the output of the NAND circuit 111 is High to render the PMOS transistor 101 non-conductive. The output of the NAND circuit 114 is Low and hence the output of the NAND circuit 112 is High to render the NMOS transistor 102 conductive. Thus, the output OUT is Low (VSS).
When the output enable signal OE is Low, the output of the NAND circuit 111 is High to render the PMOS transistor 101 non-conductive. The output of the NAND circuit 114 is High and hence the output of the NAND circuit 112 is Low to render the NMOS transistor 102 non-conductive. The PMOS transistor 101 and the NMOS transistor 102 are both non-conductive, and the output OUT is in a high-impedance state.
There is no difference in the circuit configuration between the signal path of the signal INB and that of the output enable signal OE.
The following describes the operation the circuit of
When the output enable signal OE is High and the signal INB of the input signal IN is Low, the NMOS transistor MN0 of the NAND circuit 113 is rendered non-conductive and the PMOS transistor MP0 of the NAND circuit 113 is rendered conductive to bring the node A to a High level. Hence, PMOS transistors MP2 and MP3 are bob non-conductive and an NMOS transistor MN2 of the NAND circuit 111 conductive. This brings the node PB to a Low level to render the PMOS transistor 101 (
When the output enable signal OE is Low, an NMOS transistor MN3 of the NAND circuit 111 is rendered non-conductive and a PMOS transistor MP3 of the NAND circuit 111 is rendered conductive. This brings the node PB to a High level to render PMOS transistor 101 (
With regard to both the signal path to the gate terminal of the PMOS transistor 101 and the signal path to the gate terminal of the NMOS transistor 102, the junction capacitance, as seen from the drain node of the transistor, are equivalent to that of two parallel PMOS transistors and one NMOS transistor for both of the first stage NAND circuits 113 and 114 and the second stage NAND circuits 111 and 112.
It is seen from above that the signal path to the gate terminal of the PMOS transistor 101 and that to the gate terminal of the NMOS transistor 102 are via the identical circuit configurations, thus yielding high precision access characteristics free of differences in skew or jitter.
Referring to
The following describes the operation of the circuit of
When the output enable signal OE is High, and the input signal IN is Low, with INB being High, the output of the NOR circuit 117 is Low and hence an output of the NOR circuit 115 is High to render the PMOS transistor 101 non-conductive. An output of the NOR circuit 118 is Low and hence an output of the NOR circuit 116 is High to render the NMOS transistor 102 conductive. Thus, the output OUT is Low (VSS).
When the output enable signal OE is Low, the signal OEB is High and hence the output of the NOR circuit 116 is Low to render the NMOS transistor 102 non-conductive. The output of the NOR circuit 117 is Low and hence the output of the NOR circuit 115 is High to render the PMOS transistor 101 non-conductive. Thus, the output OUT is in a high-impedance state.
On each of signal paths connecting to the gate terminals of the PMOS transistor 101 and the NMOS transistor 102, there are provided two-stage of NAND gates in the first embodiment, while there are provided two-stage of NOR gates in the second embodiment. It is noted that any suitable logic gates, such as composite gates, may also be used with comparable beneficent effects, provided that circuits arranged respectively on the signal path connecting to the gate terminal of the PMOS transistor 101 and on the signal path connecting to the gate terminal of the NMOS transistor 102 are each composed of two stages of the logic gates of similar sorts.
The following describes the operation the circuit of
When OEB is Low and the signal INB is Low, the PMOS transistors MP0 and MP1 of the NOR circuit 117 are rendered conductive to bring the node B to a High level. Hence, an NMOS transistor MN20 of the NOR circuit 115 is rendered conductive and a PMOS transistor MP21 of the NOR circuit 115 is rendered non-conductive. This brings the node PB to a Low level to render the PMOS transistor 101 conductive. A PMOS transistor MP11 of the NAND circuit 118 is rendered conductive and an NMOS transistor MN10 of the NOR circuit 118 is rendered non-conductive. This brings the node D to a High level to render an NMOS transistor MN30 of the NOR circuit 116 conductive. This brings the node NB to a Low level to render the NMOS transistor 102 non-conductive. Thus, the output OUT is High.
When the output enable signal OE is Low, with OEB being High, a PMOS transistor MN30 of the NOR circuit 116 is rendered non-conductive and an NMOS transistor MN31 of the NOR circuit 116 is rendered conductive. This brings the node NB to a Low level to render the NMOS transistor 102 non-conductive. A PMOS transistor MP0 of the NOR circuit 117 is rendered non-conductive and an NMOS transistor MN1 of the NOR circuit 117 is rendered conductive to bring the node B to Low. An NMOS transistor of the NOR circuit 115 is rendered non-conductive and the PMOS transistor MP21 is rendered conductive. This brings the node PB to a High level to render the PMOS transistor 101 non-conductive. Thus, the output OUT is in a high-impedance state.
With regard to both the signal path to the gate terminal of the PMOS transistor 101 and the signal path to the gate terminal of the NMOS transistor 102, the junction capacitance, as seen from the drain node of the transistor, are equivalent to that of two parallel NMOS transistors and one PMOS transistor for each of the first stage NOR circuits 117 and 115 and for each of the second stage NOR circuits 118 and 116.
It is seen from above that the signal path to the gate terminal of the PMOS transistor 101 and that to the gate terminal of the NMOS transistor 102 are via the MOS transistors of the same configuration, thus yielding high precision access characteristics free of differences in skew or jitter.
In the above described first and second embodiments, the circuits provided on the signal paths connecting to the gate terminals of the PMOS transistor 101 and the NMOS transistor 102 are formed by the two-stage circuits composed by the same logic gates. However, the present invention is not limited to such configuration, as will be set out in connection with the following exemplary embodiment 3 and so on.
Referring to
The NAND gate 121A includes:
a first PMOS transistor (1:MP0) and a second PMOS transistor (2: MP2) connected in series between the power supply VDD and a first node (PB) and having gate terminals connected respectively to VSS and to an input terminal IN,
a third PMOS transistor (3:MP1) and a fourth P channel MOS transistor (4:MP3) connected in series between VDD and the first node (PB) and having gate terminals connected respectively to VSS and OE.
a fifth N channel MOS transistor (5:MN0) and a sixth N channel MOS transistor (6:MN2) connected in series between the first node (PB) and VSS and having gate terminals respectively connected to IN and to OE, and
a seventh N channel MOS transistor (7:MN1) and 15th N channel MOS transistor (15:MN3) connected in series between the first node (PB) and VSS and having gate terminals both connected to VSS.
A NOR gate 122A includes:
an eighth P channel MOS transistor (8:MP4) and a ninth P channel MOS transistor (9:MP6) connected in series between VDD and the second node (NB) and having gate terminals respectively connected to OEB and IN,
a 16th P channel MOS transistor (16:MP5) and a tenth P channel MOS transistor (10:MP7) connected in series between VDD and the second node (NB) and having gate terminals both connected to VDD,
an eleventh N channel MOS transistor (11:MN4) and a twelfth N channel MOS transistor (12:MN6) connected in series between the second node (NB) and VSS and having gate terminals respectively connected to IN and to VDD,
a 13th N channel MOS transistor (13:MN5) and a 14th NMOS transistor (14:MN7) connected in series between the second node (NB) and VSS and having gate terminals respectively connected to OEB and to VDD. In the above notation, 1:MP0 denotes that the PMOS transistor MP0 has a serial number 1 and 2:MP2 denotes that PMOS transistor MP2 has a serial number 2.
In the NAND gate 121A, when the output enable signal OE is High and the input signal IN is High, the NMOS transistor MN0 is rendered conductive and the PMOS transistors MP2 and MP3 are rendered non-conductive. This sets PB to Low to render the PMOS transistor 101 conductive. In the NOR gate 122A, the PMOS transistor MP4 is rendered conductive (turned on), the PMOS transistor MP6 is rendered non-conductive (turned off) and the NMOS transistor MN4 is rendered conductive (turned on). Thus, NB is Low, so that the NMOS transistor 102 is rendered non-conductive and hence the output OUT is High.
When the output enable signal OE is High and the input signal IN is Low, the PMOS transistor MP2 is rendered conductive (turned on), and the NMOS transistor MN0 is rendered non-conductive (turned off) in the NAND gate 121A. This sets PB to High to turn off the PMOS transistor 102. The PMOS transistor MP4 is rendered conductive (turned on), the PMOS transistor MP6 is rendered conductive (turned on) and the NMOS transistor MN4 is rendered non-conductive (turned off) in the NOR gate 122A. Thus, the node NB is High, so that the NMOS transistor 102 is rendered conductive (turned on), and hence the output OUT is High.
In the NAND gate 121A, when the output enable signal OE is Low, the PMOS transistor MP3 is rendered conductive (turned on). This sets the PB to High to render the PMOS transistor 101 conductive. In the NOR gate 122A, the NMOS transistor MN5 is rendered conductive (turned on) to set the NB to Low. Hence, the NMOS transistor 102 is rendered non-conductive (turned off) so that the output Out is set in a high-impedance state.
The junction capacitances of both the signal path to the gate terminal of the PMOS transistor 101 and the signal path to the gate terminal of the NMOS transistor 102, as seen from the drain, are equivalent to those of two parallel PMOS transistors and two parallel NMOS transistors. The layout may be made the same. Hence, there is produced no difference in parasitic loads.
Referring to
Referring to
When the output enable signal OE is High, the cascode-connected PMOS transistors MP1 and MP3 are respectively in on and off state in the NAND gate 121C having an output connected to the gate terminal of the PMOS transistor 101, and the cascade-connected PMOS transistors MP5 and MP7 are respectively in on and off states in the NOR gate 122C having an output connected to the gate terminal of the NMOS transistor 102. The two sets of cascade-connected PMOS transistors in the NAND gate 121C and the NOR gate 122C are thus equivalent to each other.
When the output enable signal OE is High, in the NOR gate 122C connected to the gate terminal of the NMOS transistor 102, the cascode-connected NMOS transistors MN5 and MN7 are in on and off states, respectively. On the other hand, in the NAND gate 121C connected to the gate terminal of the PMOS transistor 101, the cascode-connected NMOS transistors MN1 and MN3 are in on and off states, respectively. Hence, two sets of cascode-connected NMOS transistors in the NAND gate 121C and the NOR gate 122C are thus equivalent to each other. Thus, a parasitic load as seen from the first node (PB) is of the same configuration as that seen from the second node (NB).
Referring to
The technical concept of the present Application may be applied to a semiconductor device having a signal transmitting circuit. The circuit format in each circuit block as well as the format of the other control signal generating circuits, disclosed in the drawings, is not limited to the format disclosed in the exemplary embodiments. The technical concept of the semiconductor device of the present invention may be applied to a variety of semiconductor devices. For example, the technical concept of the semiconductor device of the present invention may be applied to such semiconductor devices as a CPU (Central Processing Unit), an MCU (Micro Control Unit), a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an ASSP (Application Specific Standard Product) or memories. The semiconductor devices, to which the present invention is applied, may be in the form of, for example, an SOC (system-on-chip), an MCP (multi-chip package) or POP (package-on-package). The present invention may be applied to any of the semiconductor devices having these product or package forms. It is sufficient for the transistor to be a field-effect transistor (Field Effect Transistor). That is, the present invention may be applied to a variety of FETs, namely a MIS (Metal-Insulator Semiconductor) or a TFT (Thin Film Transistor) besides the MOS (Metal Oxide Semiconductor). Part of the transistors in the device may be bipolar transistors. A PMOS transistor (P channel MOS transistor) and an NMOS transistor (N channel MOS transistor) are representative examples of a transistor of a first conductivity type and a transistor of a second conductivity type, respectively.
It is to be noticed that a wide variety of combination or selections of a variety of elements disclosed, inclusive of the elements of respective claims, elements of exemplary embodiments or elements of the drawings may be attempted within the scope of the claims of the present invention. The present invention may encompass a wide variety of modifications or corrections that may occur to those skilled in the art in accordance with the entire disclosure of the present invention, inclusive of claim and the technical concept of the present invention.
Number | Date | Country | Kind |
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2011-274865 | Dec 2011 | JP | national |