Patent Application
20240244846
This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0006962, filed in the Korean Intellectual Property Office on Jan. 17, 2023, the entire contents of which are incorporated herein by reference.
Embodiments relate to a semiconductor device, a manufacturing method thereof, and an electronic system including the semiconductor device.
In an electronic system implementing data storage, a semiconductor device may be capable of storing high-capacity data. Accordingly, a method for increasing data storage capacity of a semiconductor device is being researched. One method for increasing the data storage capacity of a semiconductor device may include a semiconductor device including three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells.
The embodiments may be realized by providing a semiconductor device including a substrate; a stack structure including an interlayer insulating layer and a gate electrode which are alternately stacked on the substrate; a channel layer extending in a direction crossing the substrate through the stack structure; and a gate dielectric layer between the gate electrode and the channel layer, the gate dielectric layer including a tunneling layer, a charge storage layer, and a blocking layer sequentially on the channel layer, wherein the tunneling layer includes a carbon-containing layer including carbon, and the tunneling layer is positioned closer to the channel layer than it is to the charge storage layer.
The embodiments may be realized by providing a semiconductor device including a main substrate; a semiconductor device on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate, wherein the semiconductor device includes a circuit region including a peripheral circuit structure on a first substrate and a cell region including a memory cell structure on a second substrate, the cell region includes a stack structure including an interlayer insulating layer and a gate electrode which are alternately stacked on the second substrate, a channel layer extending through the stack structure and extending in a direction crossing the second substrate, and a gate dielectric layer between the gate electrode and the channel layer to include a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel layer, and the tunneling layer includes a carbon-containing layer including carbon, the tunneling layer being closer to the channel layer than to the charge storage layer.
The embodiments may be realized by providing a manufacturing method of a semiconductor device including a stack structure including an interlayer insulating layer and a gate electrode which are alternately stacked on a substrate, a channel layer extending through the stack structure and extending in a direction crossing the substrate, and a gate dielectric layer between the gate electrode and the channel layer, the gate dielectric layer including a tunneling layer, a charge storage layer, and a blocking layer sequentially on the channel layer, the method including forming the tunneling layer such that forming the tunneling layer includes forming a carbon-containing layer that includes carbon and is closer to the channel layer than to the charge storage layer.
Features will be apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:
Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment will be described in detail with reference to
Referring to
Herein, the circuit region 200 may include a peripheral circuit structure on a first substrate 210, and the cell region 100 may include a gate stack structure 120 and a channel structure CH on a cell array region 102 of the second substrate 110 as a memory cell structure. The circuit region 200 may include a first wire portion 230 electrically connected to the peripheral circuit structure, and the cell region 100 may include a second wire portion 180 electrically connected to the memory cell structure.
In an implementation, the cell region 100 may be on the circuit region 200. In an implementation, an area corresponding to the circuit region 200 may not need to be secured separately from the cell region 100, and an area of the semiconductor device 10 may be reduced. In an implementation, the circuit region 200 may be next to (e.g., laterally adjacent to) the cell region 100. Numerous other variations are possible.
The circuit region 200 may include the first substrate 210, and a circuit element 220 and the first wire portion 230 on the first substrate 210.
The first substrate 210 may be a semiconductor substrate including a semiconductor material. In an implementation, the first substrate 210 may be a semiconductor substrate made of a semiconductor material or may be a semiconductor substrate on which a semiconductor layer is formed on a base substrate. In an implementation, the first substrate 210 may include, e.g., monocrystalline or polycrystalline silicon, epitaxial silicon, germanium, silicon-germanium, silicon on insulator (SOI), or germanium on insulator (GOI). As used herein, the term “or” is not an exclusive term, e.g., “A or B” would include A, B, or A and B.
The circuit element 220 on the first substrate 210 may include any of various circuit elements that control the operation of the memory cell structure in the cell region 100. In an implementation, the circuit element 220 may include peripheral circuit structures such as a decoder circuit (reference numeral 1110 in
The circuit element 220 may include, e.g., a transistor. In an implementation, the peripheral circuit element 220 may include not only active elements such as transistors, but also passive elements such as capacitors, resistors, or inductors.
The first wire portion 230 on the first substrate 210 may be electrically connected to the circuit element 220. In an implementation, the first wire portion may include a plurality of wiring layers 236 spaced apart with a first insulating layer 232 therebetween and connected to form a desired path by a contact via 234. The wiring layer 236 or the contact via 234 may include any of various conductive materials, and the first insulating layer 232 may include any of various insulating materials.
The cell region 100 may include the cell array region 102 and a connecting region 104. The gate stack structure 120 and the channel structure CH may be on the second substrate 110 in the cell array region 102. In the connecting region 104, a structure for connecting the gate stack structure 120 or the channel structure CH in the cell array region 102 to the circuit region 200 or an external circuit may be positioned.
In an implementation, the second substrate 110 may be a semiconductor substrate including a semiconductor material. In an implementation, the second substrate 110 may be a semiconductor substrate made of a semiconductor material or may be a semiconductor substrate on which a semiconductor layer is on a base substrate. In an implementation, the second substrate 110 may include silicon, germanium, silicon-germanium, silicon on insulator, or germanium on insulator. Herein, the semiconductor material included in the second substrate 110 may be doped with a P-type or N-type impurity, and for example, an n-type impurity (e.g., phosphorus (P), arsenic (As), or the like) may be doped.
In the cell array region 102, the gate stack structure 120 including cell insulating layers 132 and gate electrodes 130 alternately stacked on the first surface (e.g., a front surface or an upper surface) of the second substrate 110, and the channel structure CH extending in a direction crossing the second substrate 110 through the gate stack structure 120 may be formed.
In an implementation, horizontal conductive layers 112 and 114 may be between the second substrate 110 and the gate stack structure 120 in the cell array region 102. The horizontal conductive layers 112 and 114 may serve to electrically connect the channel structure CH and the second substrate 110. In an implementation, the horizontal conductive layers 112 and 114 may include a first horizontal conductive layer 112 on the first surface of the second substrate 110, and may further include a second horizontal conductive layer 114 on the first horizontal conductive layer 112. The first horizontal conductive layer 112 may not be provided and a horizontal insulating layer 116 may be between the second substrate 110 and the gate stack structure 120 in a portion of the connecting region 104. In a manufacturing process, a portion of the horizontal insulating layer 116 may be replaced with the first horizontal conductive layer 112, and another portion of the horizontal insulating layer 116 located in the connecting region 104 may remain in the connecting region 104.
The first horizontal conductive layer 112 may function as a portion of a common source line of the semiconductor device 10. In an implementation, the first horizontal conductive layer 112 and the second substrate 110 may function as the common source line. As illustrated in the enlarged view of
The first and second horizontal conductive layers 112 and 114 may include a semiconductor material (e.g., polycrystalline silicon). In an implementation, the first horizontal conductive layer 112 may be a polycrystalline silicon layer doped with impurities, and the second horizontal conductive layer 114 may be a polycrystalline silicon layer doped with impurities or a layer including impurities diffused from the first horizontal conductive layer 112. In an implementation, the second horizontal conductive layer 114 may be made of an insulating material. In an implementation, the second horizontal conductive layer 114 may not be provided separately.
The gate stack structure 120 in which the cell insulating layers 132 and the gate electrodes 130 may be alternately stacked may be positioned on the second substrate 110 (e.g., on the first and second horizontal conductive layers 112 and 114 on the second substrate 110).
In an implementation, the gate stack structure 120 may include a plurality of gate stack structures 120a and 120b sequentially stacked on the second substrate 110. A number of stacked gate electrodes 130 may be increased, and a number of memory cells may be increased with a stable structure. In an implementation, the gate stack structure 120 may include the first and second gate stack structures 120a and 120b, thereby increasing data storage capacity and simplifying the structure. In an implementation, the gate stack structure 120 may include one gate stack structure or three or more gate stack structures.
In the gate stack structure 120, the gate electrode 130 may include a lower gate electrode 130L, a memory cell gate electrode 130M, and an upper gate electrode 130U sequentially on the second substrate 110. The lower gate electrode 130L may be a gate electrode of a ground select transistor, the memory cell gate electrode 130M may constitute a memory cell, and the upper gate electrode 130U may be a gate electrode of a string select transistor. A number of memory cell gate electrodes 130M may be determined according to data storage capacity of the semiconductor device 10. In an implementation, one or two or more lower gate electrodes 130L and upper gate electrodes 130U may be provided, and it may have a same structure as that of the memory cell gate electrode 130M or a different structure. A portion of the gate electrode 130, e.g., the memory cell gate electrode 130M adjacent to the lower gate electrode 130L and the upper gate electrode 130U, may be a dummy gate electrode.
The cell insulating layers 132 may include an interlayer insulating layer 132m below the gate electrode 130 or between two adjacent gate electrodes 130 in first and second gate stack structures 120a and 120b, and upper insulating layers 132a and 132b at upper portions of the first and second gate stack structures 120a and 120b. In an implementation, the upper insulating layers 132a and 132b may include a first upper insulating layer 132a at an upper portion of the first gate stack structure 120a, and a second upper insulating layer 132b at upper portion of the second gate stack structure 120b. In an implementation, the first upper insulating layer 132a may be an intermediate insulating layer between the first gate stack structure 120a and the second gate stack structure 120b, and the second upper insulating layer 132b may be an uppermost insulating layer at an uppermost portion of the gate stack structure 120. The second upper insulating layer 132b may form part or all of a cell region insulating layer positioned at an entire upper portion of the cell region 100. In an implementation, thicknesses of the cell insulating layers 132 may not all be the same. In an implementation, the thicknesses of the upper insulating layers 132a and 132b may be greater than the thickness of the interlayer insulating layer 132m.
For simplicity of illustration, the cell insulating layer 132 in the connecting region 104 has a boundary between the first stack structure 120a and the second stack structure 120b. In an implementation, in the connecting region 104, a plurality of insulating layers may have any of various stack structures.
The gate electrode 130 may include any of various conductive materials. In an implementation, the gate electrode 130 may include a metal material such as tungsten (W), copper (Cu), or aluminum (Al). In an implementation, the gate electrode 130 may include polycrystalline silicon, a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), or the like), or a combination thereof. In an implementation, outside the gate electrode 130, an insulating film made of an insulating material may be positioned, or a portion of the gate dielectric layer 150 may be positioned. The cell insulating layer 132 may include any of various insulating materials. In an implementation, the cell insulating layer 132 may include a silicon oxide, a silicon nitride, a silicon oxynitride, a low dielectric constant material having a lower dielectric constant than the silicon oxide, or a combination thereof.
In an implementation, the channel structure CH extending in a direction crossing the second substrate 110 (e.g., a vertical direction perpendicular to the second substrate 110 or Z-axis direction in the drawing) may extend through the gate stack structure 120.
In an implementation, the channel structure CH may include a channel layer 140 and a gate dielectric layer 150 on the channel layer 140 between the gate electrode 130 and the channel layer 140. The channel structure CH may further include a core insulating layer 142 inside the channel layer 140, and a channel pad 144 on the channel layer 140 or the gate dielectric layer 150.
Each channel structure CH may form one memory cell string, and a plurality of channel structures CH may be spaced apart from each other while forming rows and columns in a plan view. In an implementation, the channel structures CH may be arranged in any of various forms such as a lattice form or a zigzag form in a plan view. The channel structures CH may each have a columnar shape. In an implementation, when the channel structure CH is viewed in a cross-sectional view, it may have an inclined side surface such that its width narrows as it approaches the second substrate 110 according to an aspect ratio.
The core insulating layer 142 may be in a central region of the channel structure CH, and the channel layer 140 may surround sidewalls of the core insulating layer 142. In an implementation, the core insulating layer 142 may have a columnar shape (e.g., a cylindrical shape or a polygonal columnar shape), and the channel layer 140 may have a planar shape such as an annular shape. In an implementation, the core insulating layer 142 may not be provided and the channel layer 140 may have a columnar shape (e.g., a cylindrical shape or a polygonal columnar shape).
The channel layer 140 may include a semiconductor material, e.g., polycrystalline silicon. The core insulating layer 142 may include any of various insulating materials. In an implementation, the core insulating layer 142 may include a silicon oxide, a silicon nitride, a silicon oxynitride, or a combination thereof.
The gate dielectric layer 150 between the gate electrode 130 and the channel layer 140 may include a tunneling layer 152, a charge storage layer 154, and a blocking layer 156 sequentially on (e.g., stacked or layered outwardly from) the channel layer 140.
In an implementation, the tunneling layer 152 may be a layer through which charges are tunneled according to a voltage applied to the gate electrode 130, and may include an insulating material capable of tunneling charges. In an implementation, the tunneling layer 152 may include a carbon-containing layer (reference numeral 152f in
The charge storage layer 154 between the tunneling layer 152 and the blocking layer 156 may be a data storage region. In an implementation, the charge storage layer 154 may include a silicon nitride capable of trapping charges, and may be formed of, e.g., a silicon nitride layer. When the charge storage layer 154 is made of a silicon nitride, retention may be excellent and it may be advantageous for integration, compared to being made of polycrystalline silicon.
The blocking layer 156 may be between the charge storage layer 154 and the gate electrode 130. The blocking layer 156 may include an insulating material capable of preventing an undesirable flow of charges into the gate electrode 130. In an implementation, the blocking layer 156 may include a silicon oxide, a silicon nitride, a silicon oxynitride, a high dielectric constant material, or a combination thereof.
Herein, the high dielectric constant material indicates a dielectric material having a higher dielectric constant than that of the silicon oxide. The high dielectric constant material may include, e.g., an aluminum oxide (Al2O3), a tantalum oxide (Ta2O3), a titanium oxide (TiO2), a yttrium oxide (Y2O3), a zirconium oxide (ZrO2), a zirconium silicon oxide (ZrSixOy), a hafnium oxide (HfO2), a hafnium silicon oxide (HfSixOy), a lanthanum oxide (La2O3), a lanthanum aluminum oxide (LaAlxOy), a lanthanum hafnium oxide (LaHfxOy), a hafnium aluminum oxide (HfAlxOy), a praseodymium oxide (Pr2O3), or a combination thereof.
A channel pad 144 may be on the channel layer 140 or the gate dielectric layer 150. The channel pad 144 may cover an upper surface of the core insulating layer 142 and may be electrically connected to the channel layer 140. The channel pad 144 may include a conductive material, e.g., polycrystalline silicon doped with impurities.
As described above, when the gate stack structure 120 includes a plurality of gate stack structures 120a and 120b stacked on each other, the channel structure CH may include a plurality of channel structures CH1 and CH2 extending through the gate stack structures 120a and 120b, respectively. In an implementation, when the gate stack structures 120 include the first and second gate stack structures 120a and 120b, the channel structures CH may include first and second channel structures CH1 and CH2 extending through them, respectively.
The first channel structure CH1 and the second channel structure CH2 may be connected to each other. Each of the first channel structure CH1 and the second channel structure CH2 may have an inclined side surface such that its width becomes narrower closer to the second substrate 110 according to an aspect ratio when viewed in a cross-sectional view. In an implementation, as illustrated in
In
In an implementation, the channel pad 144 may be on the gate stack structure 120 at an upper portion among the plurality of gate stack structures 120 (e.g., a channel structure CH such as a second channel structure CH2) in the second gate stack structure 120b). In an implementation, the channel pad 144 may be on each of the first channel structure CH1 and the second channel structure CH2. In this case, the channel pad 144 of the first channel structure CH1 may be connected to the channel layer 140 of the second channel structure CH2.
In an implementation, the gate stack structure 120 may extend in a direction crossing the second substrate 110 (e.g., a vertical direction, i.e., a Z-axis direction in the drawing) to be partitioned in plural in a plan view by a separating structure 146 extending the gate stack structure 120.
In an implementation, the separating structure 146 may extend to the second substrate 110 through the gate electrode 130 and the cell insulating layer 132. In a plan view, the separating structure 146 may extend in one direction (Y-axis direction in the drawing), and may be provided in plural so as to be spaced apart from each other at a predetermined interval in a crossing direction (X-axis direction in the drawing) crossing the one direction. In an implementation, in a plan view, the gate stack structures 120 may each extend in one direction (Y-axis direction in the drawing) and may be spaced apart from each other at a predetermined interval in the crossing direction (X-axis direction in the drawing). The gate stack structures 120 partitioned by the separating structure 146 may constitute one memory cell block.
In an implementation, the separating structure 146 may have an inclined side surface of which width decreases toward the second substrate 110 when viewed in a cross-sectional view due to a high aspect ratio. In an implementation, a side surface of the separating structure 146 may be perpendicular to the second substrate 110. In an implementation, as illustrated in
The separating structure 146 may be filled with a variety of insulating materials. In an implementation, the separating structure 146 may include an insulating material such as a silicon oxide, a silicon nitride, or a silicon oxynitride.
An upper separating region 148 may be at an upper portion of the gate stack structure 120. In a plan view, the upper separating region 148 may extend in one direction (Y-axis direction in the drawing), and may be provided in plural so as to be spaced apart from each other at a predetermined interval in a crossing direction (X-axis direction in the drawing) crossing the one direction.
The upper separating region 148 may be formed by extending through one or a plurality of gate electrodes 130 including the upper gate electrode 130U positioned between the separating structures 146. The upper separating region 148 may separate, e.g., three gate electrodes 130 from each other in the crossing direction (X-axis direction in the drawing). In an implementation, a number of gate electrodes 130 separated by the upper separating region 148 may vary. The upper separating region 148 may have a form filled with an insulating material. In an implementation, the upper separating region 148 may include an insulating material such as a silicon oxide, a silicon nitride, or a silicon oxynitride.
The connecting region 104 and the second wire portion 180 may connect the gate stack structure 120 and the channel structure CH in the cell array region 102 to the circuit region 200 or an external circuit.
Herein, the second wire portion 180 may include all members electrically connecting the gate electrode 130, the channel structure CH, the horizontal conductive layers 112 and 114, or the second substrate 110 to the circuit region 200 or an external circuit. In an implementation, the second wire portion 180 may include a bitline 182, a gate contact portion 184, a source contact portion 186, a through plug 188, and contact vias 180a respectively connected to them, and a connecting wire 190 connecting them.
The bitline 182 may be on the cell insulating layer 132 of the gate stack structure 120 formed in the cell array region 102. The bitline 182 may extend (e.g., lengthwise) in the cross direction (X-axis direction in the drawing) crossing one direction in which the gate electrode 130 extends. The bitline 182 may be electrically connected to the channel structure CH, e.g., the channel pad 144, through the contact via 180a, e.g., a bit line contact via.
The connecting region 104 may be positioned around the cell array region 102 and a portion of the second wire portion 180 may be positioned. The connecting region 104 may include members for connection with the gate electrode 130, the horizontal conductive layers 112 and 114, or the second substrate 110, and the circuit region 200. In an implementation, the connecting region 104 may include a portion where an input and output pad and an input and output connecting wire are formed.
In an implementation, the gate electrodes 130 may be extended and positioned in one direction (Y-axis direction in the drawing) in the connecting region 104, and extended lengths of the gate electrodes 130 in the connecting region 104 may sequentially decrease as a distance from the second substrate 110 increases. In an implementation, the gate electrodes 130 may be positioned while having a stepped shape in the connecting region 104. In an implementation, the gate electrodes 130 may have a stepped shape in one direction or in a plurality of directions. In the connecting region 104, a plurality of gate contact portions 184 may be electrically connected to the respective gate electrodes 130 extending to the connecting region 104 through the cell insulating layer 132.
In the connecting region 104, the source contact portion 186 may extend through the cell insulating layer 132 to be electrically connected to the horizontal conductive layers 112 and 114 or the second substrate 110, and the through plug 188 may extend through the gate stack structure 120 or may be positioned outside the gate stack structure 120 to be electrically connected to the first wire portion 230 of the circuit region 200.
The connecting wire 190 may be in the cell array region 102 or the connecting region 104. The bitline 182, the gate contact portion 184, the source contact portion 186, and/or the through plug 188 may be electrically connected to the connecting wire 190. In an implementation, the gate contact portion 184, the source contact portion 186, or the through plug 188 may be connected to the connecting wire 190 through the contact via 180a.
In an implementation, as illustrated in
As described above, the bitline 182, the gate electrode 130, the horizontal conductive layers 112 and 114, or the second substrate 110 connected to the channel structure CH may be electrically connected to the circuit element 220 of the circuit region 200 by the second wire portion 180 and the first wire portion 230.
In an implementation, as illustrated in
In an implementation, the gate dielectric layer 150 may include the tunneling layer 152, the charge storage layer 154, and the blocking layer 156 sequentially on the channel layer 140 and between the channel layer 140 and the gate electrode 130. In an implementation, the tunneling layer 152 may include a carbon-containing layer (reference numeral 152f in
Referring to
The first tunneling layer 152a adjacent to the channel layer 140 or the third tunneling layer 152c adjacent to the charge storage layer 154 may have a material or composition having a smaller dielectric constant and greater bandgap energy than those of the second tunneling layer 152b.
The first tunneling layer 152a or the third tunneling layer 152c may have a relatively small dielectric constant and a relatively large bandgap energy, to help prevent the charge stored in the charge storage layer 154 from undesirably escaping when no voltage is applied to the gate electrode 130 (e.g., when maintaining data). In an implementation, storage stability may be improved by the first tunneling layer 152a or the third tunneling layer 152c.
The second tunneling layer 152b having a relatively large dielectric constant and relatively small bandgap energy compared to the first tunneling layer 152a and the third tunneling layer 152c may have excellent insulating characteristics. Accordingly, even if a total thickness of the tunneling layer 152 including the second tunneling layer 152b were to be reduced, excellent insulating characteristics may be maintained, thereby reducing the thickness of the tunneling layer 152. Then, an operating speed may be improved by reducing an operating voltage, and distribution of a threshold voltage may be improved by reducing a leakage current.
In an implementation, the tunneling layer 152 may include the first tunneling layer 152a, the second tunneling layer 152b, and the third tunneling layer 152c having different materials or compositions, so as to help reduce the operating voltage, to help improve the operating speed, and to help reduce the leakage current while improving the storage stability. In an implementation, the tunneling layer 152 may have a structure capable of effectively improving various characteristics.
In an implementation, the first tunneling layer 152a may include the carbon-containing layer 152f made of a silicon oxide material including silicon and oxygen and including carbon. In an implementation, the carbon-containing layer 152f may include a silicon oxycarbide (SiOC) including silicon, oxygen, and carbon. In an implementation, the carbon-containing layer 152f may be a hydrogenated silicon oxycarbide layer including hydrogenated silicon oxycarbide (SiOC:H) in which hydrogen is bonded to silicon or silicon oxycarbide. When hydrogen is bonded, defects may be reduced. For reference, the chemical formula SiOC:H for the above-described hydrogenated silicon oxycarbide is based on elements included in the hydrogenated silicon oxycarbide, and does not indicate a specific chemical quantitative ratio.
The carbon-containing layer 152f may have a lower dielectric constant than that of a silicon oxide by including carbon in a silicon oxide-based material. As such, the carbon-containing layer 152f having a low dielectric constant (low-k) may react sensitively to an electric field when a voltage is applied. Accordingly, the carbon-containing layer 152f may be an electric field concentration layer in which an electric field is concentrated. As such, when the electric field is concentrated on the carbon-containing layer 152f, a magnitude of a gradient of an energy level in an FN tunneling region (reference numeral FN1 in
As such, an energy band diagram may be adjusted as desired such that charge tunneling may easily occur through the carbon-containing layer 152f. As a result, an operation speed and durability of the semiconductor device 10 may be improved.
Moreover, within a certain range, as the carbon content increases, a breakdown voltage (BV) and a breakdown time (Tbd) of the carbon-containing layer 152f may increase, thereby reducing a leakage current.
In an implementation, the carbon-containing layer 152f including hydrogenated silicon oxycarbide may include, e.g., 0.2 at % to 10 at % of carbon. If carbon were to be included in an amount of less than 0.2 at %, an effect of carbon may not be sufficient. If carbon were to be included in an amount exceeding 10 at %, the carbon may be agglomerated to form a current path, whereby an effect of increasing the breakdown voltage by the carbon may be rather reduced.
Whether carbon is included in the carbon-containing layer 152f, the content of carbon, and the like may be determined by any of various composition detection methods. In an implementation, they may be determined by energy dispersive X-ray spectroscopy (EDS), electron energy loss spectroscopy (EELS), or the like.
In an implementation, a thickness T1 of the first tunneling layer 152a may be smaller than a thickness T2 of the second tunneling layer 152b, e.g., 5 nm or less (e.g., 0.1 nm to 5 nm). If the thickness T1 of the first tunneling layer 152a were to exceed 5 nm, the operation speed could be lowered or a relatively high operation voltage could be required, which may not be advantageous in terms of durability. If the thickness T1 of the first tunneling layer 152a were to be less than 0.1 nm, storage stability could be deteriorated. Accordingly, the thickness of the carbon-containing layer 152f constituting part or all of the first tunneling layer 152a may be smaller than the thickness T2 of the second tunneling layer 152b, and may have a thickness of, e.g., 5 nm or less (more specifically, 0.1 nm to 5 nm). In an implementation, the thickness of the carbon-containing layer 152f may be 2 nm or less to effectively implement an effect of the carbon-containing layer 152f.
In an implementation, the carbon-containing layer 152f may be made of a silicon oxide material, and thus storage stability may be excellently maintained, and it may have a lower dielectric constant than that of a silicon oxide by including carbon, thereby improving an operation speed, durability, and reliability.
In an implementation, the first tunneling layer 152a may have a single-layered structure including the carbon-containing layer 152f. In an implementation, the carbon-containing layer 152f may be in contact (e.g., direct contact) with the channel layer 140 and the second tunneling layer 152b. Accordingly, a structure of the first tunneling layer 152a may be simplified, and an effect of the carbon-containing layer 152f may be maximized. Various embodiments of the first tunneling layer 152a including the carbon-containing layer 152f will be described below in more detail with reference to
The second tunneling layer 152b on the first tunneling layer 152a may include a silicon oxynitride (SiON) including silicon, oxygen, and nitrogen. The silicon oxynitride may have excellent insulating characteristics and has a lower trap density than that of the silicon oxide, which may help reduce a leakage current due to traps during data retention. In an implementation, the second tunneling layer 152b may include a hydrogenated silicon oxynitride (SiON:H) in which hydrogen is bonded to the silicon oxynitride. For reference, the chemical formula SiON:H for the above-described hydrogenated silicon oxynitride is based on elements included in the hydrogenated silicon oxynitride, and does not indicate a specific chemical quantitative ratio.
The thickness T2 of the second tunneling layer 152b may be greater than each of the thickness T1 of the first tunneling layer 152a and the thickness T3 of the third tunneling layer 152c. In an implementation, the thickness T2 of the second tunneling layer 152b may be 10 nm or less (e.g., 1 nm to 10 nm). If the thickness of the second tunneling layer 152b were to exceed 10 nm, the thickness of the tunneling layer 152 could increase, so that it could be difficult to sufficiently realize an effect of reducing the operation voltage and improving the operating speed. If the thickness of the second tunneling layer 152b were to be too thin (e.g., less than 1 nm), it could be difficult for the tunneling layer 152 to have excellent insulating characteristics.
The third tunneling layer 152c may include a silicon oxynitride including silicon, oxygen, and nitrogen as basic materials, and may have a different composition from that of the second tunneling layer 152b. In an implementation, the third tunneling layer 152c may have a lower nitrogen content than that of the second tunneling layer 152b. In an implementation, the third tunneling layer 152c may include a hydrogenated silicon oxynitride in which hydrogen is bonded to the silicon oxynitride including silicon, oxygen, and nitrogen. In an implementation, a material of the third tunneling layer 152c may be different from that of the second tunneling layer 152b. In an implementation, the third tunneling layer 152c may be made of a silicon oxide. In an implementation, the third tunneling layer 152c may not be separately provided (e.g., may be omitted).
The thickness T3 of the third tunneling layer 152c may be smaller than the thickness T2 of the second tunneling layer 152b, may be equal to the thickness T1 of the first tunneling layer 152a, or may be smaller or greater than the thickness T1 of the first tunneling layer 152a. In an implementation, the thickness T3 of the third tunneling layer 152c may be 5 nm or less (e.g., 0.1 nm to 5 nm). This is a range considering the effect of the third tunneling layer 152c.
As described above, in an embodiment, the first tunneling layer 152a between the channel layer 140 and the second tunneling layer 152b (having a largest thickness T2 in the tunneling layer 152) may include the carbon-containing layer 152f, and the carbon-containing layer 152f may be closer to the channel layer 140 than it is to the charge storage layer 154. In an implementation, a distance between the carbon-containing layer 152f and the channel layer 140 may be smaller than a distance between the carbon-containing layer 152f and the charge storage layer 154. In the tunneling layer 152, the first tunneling layer 152a may be adjacent to the channel layer 140 to have a great influence on charge tunneling, and the first tunneling layer 152a may include the carbon-containing layer 152f so that charge tunneling can easily occur.
A reason why tunneling of charges can occur more easily when the first tunneling layer 152a includes the carbon-containing layer 152f as described above will be described in more detail below with reference to
In
Referring to
Referring to
The erasing operation is presented as an example in
According to the embodiment, the carbon-containing layer 152f having a relatively low dielectric constant may include carbon at a portion that is adjacent to the channel layer 140 rather than the charge storage layer 154 in the tunneling layer 152 and functioning as an electric field concentration layer may be provided, thereby facilitating charge tunneling. Accordingly, the operation speed and durability may be improved. In an implementation, the carbon-containing layer 152f may include a silicon oxycarbide, and thus reliability may be improved by increasing a breakdown voltage and reducing a leakage current.
An example of a manufacturing method for manufacturing the semiconductor device 10 having the above structure will be described in detail with reference to
Referring to
Herein, the sacrificial insulating layer 130s may be a layer replaced with a gate electrode (reference numeral 130 of
The horizontal insulating layer 116 or the sacrificial insulating layer 130s may be formed of a different material from that of the cell insulating layer 132. In an implementation, the cell insulating layer 132 may include a silicon oxide, a silicon nitride, a silicon oxynitride, a low dielectric constant material, or the like, and the sacrificial insulating layer 130s may include one of silicon, silicon oxide, silicon carbide, silicon nitride, or the like, and may be made of a different material from that of the cell insulating layer 132.
The penetrating portion CHH may be formed while extending through the stack structure 120s to provide a space in which a channel structure (reference numeral CH in
In an implementation, the stack structure 120s may include a first stack structure and a second stack structure corresponding to the first gate stack structure (reference numeral 120a in
In an implementation, the first stack structure may be formed and the first through portion may be formed, and then the second stack structure may be formed and the second through portion may be formed. In an implementation, the first stack structure and the second stack structure may be formed, and then the first through portion may be formed through the second through portion after the second through portion is formed. In an implementation, a forming process and a forming order of the stacking structure and the through portion may be modified in various ways.
At least a portion of the blocking layer 156, the charge storage layer 154, the third tunneling layer 152c, and the second tunneling layer 152b may be sequentially formed in the through portion CHH. At least a portion of the blocking layer 156, the charge storage layer 154, the third tunneling layer 152c, and the second tunneling layer 152b may be formed using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process.
In an implementation, an upper separating region (reference numeral 148 in
Subsequently, as illustrated in
In an implementation, a carbon doping process of doping carbon into the base tunneling layer 152s may be performed by a plasma assisted doping (PLAD) process.
The plasma assisted doping process will be described in more detail below with reference to
Referring to
The chamber 310 may provide an internal space for performing the plasma assisted doping process. The chamber 310 may include a gas supply unit 312 for supplying doping gas to the internal space of the chamber 310 and a vacuum unit 314 for vacuuming the internal space of the chamber 310.
The first electrode 322 and the second electrode 324 facing each other may be in the internal space of the chamber 310. The first electrode 322 and the second electrode 324 may function as a lower electrode and an upper electrode that excite the doping gas to a plasma state. In addition, a workpiece W to be doped may be positioned on the first electrode 322, and the first electrode 322 may function as a support for supporting the workpiece W. A bias voltage may be supplied to the first electrode 322 by the first power supply 332, and a ground voltage may be supplied to the second electrode 324 by the second power supply 334. In an implementation, the bias voltage may be provided to the first electrode 322 in the form of a pulse.
The meter 340 for measuring a dose of ions or radicals in plasma may be in the chamber 310. In an implementation, in order to improve accuracy, the meter 340 may be in a periphery of the first electrode 322 where the workpiece W is positioned.
As illustrated in
In an implementation, in the plasma assisted doping process, the base tunneling layer 152s may be doped with carbon including a carbon supply material using the doping gas to form the carbon-containing layer 152f. In an implementation, the doping gas may include a carbonized hydrogen (hydrocarbon) gas and a carrier gas (or dilution gas) as a carbon supply material. In an implementation, methane (CH4) gas may be used as the hydrocarbon gas, and argon (Ar) gas or hydrogen (H2) gas may be used as the carrier gas. The carbon supply material may be included at 10 vol % or less with respect to 100 vol % of the total doping gas, and a bias voltage may be 1 kV or less, and RF power may be 3,000 W or less. The dose measured by the meter 340 may be 2×1016 pcs/cm2 or less. This is an example of a process condition for the carbon-containing layer 152f to include 0.2 at % to 10 at % of carbon.
In an implementation, a doping depth of carbon doped in the carbon-containing layer 152f may be related to the bias voltage, and a content of carbon doped in the carbon-containing layer 152f may be related to a ratio of the carbon supply gas to the carrier gas and a process time. If the ratio of the carbon supply gas were to be too high, carbon may not be doped and may be deposited on a surface thereof. An amount of carbon doped into the carbon-containing layer 152f may be controlled by lowering the ratio of the carbon supply gas to a predetermined ratio or less and adjusting the process time. In an implementation, the process time of the plasma assisted doping process may be adjusted such that the carbon-containing layer 152f may include 0.2 at % to 10 at % of carbon.
This plasma assisted doping process may generate a large amount of ions at low energy and may dope carbon to have a desired doping concentration and doping depth may be suitably applied to form the carbon-containing layer 152f in the semiconductor device 10.
Subsequently, as illustrated in
In an implementation, the channel layer 140 may be on the gate dielectric layer 150 within the through portion CHH. A material constituting the channel layer 140 may be deposited to a first thickness, and then a crystallization process may be performed, and the channel layer 140 may be formed by partially etching the channel layer 140 to have a second thickness that is smaller than the first thickness. The core insulating layer 142 may be on the channel layer 140 and fill the through portion CHH.
Subsequently, as illustrated in
In an implementation, an opening may be formed to extend through a stacking structure in which the sacrificial insulating layer 130s and the cell insulating layer 132 are stacked (reference numeral 120s in
In addition, an insulating material may be filled in the opening to form the separating structure 146. Thereafter, an upper wire structure connected to the channel structure CH may be further formed.
In an implementation, the tunneling layer 152 adjacent to the channel layer 140 and including a carbon-containing layer 152f including an electric field concentration layer may be stably formed through a simple process.
In an implementation, the base tunneling layer 152s may be doped with carbon using a plasma assisted doping process to form the carbon-containing layer 152f. In an implementation, the carbon-containing layer 152f may be on the second tunneling layer 152b by using a deposition process of depositing a carbon-containing layer instead of the processes illustrated in
Further, in the above-described embodiment, in the plasma assisted doping process, in the embodiment, an entire thickness of the base tunneling layer 152s may be doped with carbon to entirely change the base tunneling layer 152s to the carbon-containing layer 152f. Accordingly, the first tunneling layer 152a may have a single-layer structure including the carbon-containing layer 152f.
A semiconductor device according to various embodiments will be described in more detail with reference to
Referring to
In an implementation, the base tunneling layer 152s may be formed of a layer that is based on a same material as that of the carbon-containing layer 152f but is not doped with carbon. In an implementation, the base tunneling layer 152s may be formed of a silicon oxide layer including a silicon oxide, e.g., a hydrogenated silicon oxide (SiOx:H).
The carbon-containing layer 152f may be adjacent to (e.g., in contact with) the channel layer 140, and the base tunneling layer 152s may be adjacent to (e.g., in contact with) the second tunneling layer 152b. In an implementation, when the energy bandgap is relatively small and an electric field is applied at a portion adjacent to the channel layer 140, the carbon-containing layer 152f forming a wide FN tunneling region is positioned so that charge tunneling may easily occur. In an implementation, the base tunneling layer 152s may be adjacent to the second tunneling layer 152b, and it is possible to prevent the carbon included in the carbon-containing layer 152f from undesirably affecting the second tunneling layer 152b.
In an implementation, a thickness of the carbon-containing layer 152f may be greater than that of the base tunneling layer 152s. Then, an effect of the carbon-containing layer 152f may be fully implemented. In an implementation, the thickness of the carbon-containing layer 152f may be equal to or smaller than that of the base tunneling layer 152s.
In an implementation, a portion of the base tunneling layer 152s in the thickness direction may be doped with carbon to form the carbon-containing layer 152f to form the first tunneling layer 152 having the above structure. In an implementation, in the initially formed base tunneling layer 152s, a carbon-nondoped remaining portion and a carbon-doped portion may constitute the base tunneling layer 152s and the carbon-containing layer 152f of the first tunneling layer 152a, respectively. In an implementation, in the plasma assisted doping process described with reference to
In an implementation, the first tunneling layer 152a having the above structure may be formed by sequentially forming the base tunneling layer 152s and the carbon-containing layer 152f by an atomic layer deposition process. In this case, the base tunneling layer 152s and the carbon-containing layer 152f may be formed in a continuous process using a same device, thereby simplifying the manufacturing process.
Referring to
In this case, the base tunneling layer 152s may be adjacent to (e.g., in contact with) the channel layer 140, and the carbon-containing layer 152f may be adjacent to (e.g., in contact with) the second tunneling layer 152b. In an implementation, the base tunneling layer 152s may be adjacent to the channel layer 140, interface characteristics between the channel layer 140 and the first tunneling layer 152a may be improved, and storage stability may be improved. In an implementation, when an energy bandgap is relatively small and an electric field is applied, tunneling of charges may be facilitated through the carbon-containing layer 152f forming the wide FN tunneling region.
In an implementation, a thickness of the carbon-containing layer 152f may be greater than that of the base tunneling layer 152s. Then, an effect of the carbon-containing layer 152f may be fully implemented. In an implementation, the thickness of the carbon-containing layer 152f may be equal to or smaller than that of the base tunneling layer 152s.
In an implementation, after forming a silicon oxide layer, carbon may be doped to form a carbon-containing layer 152f, and then another silicon oxide layer may be additionally formed to form the first tunneling layer 152 having the above structure. In this case, another silicon oxide layer may constitute the base tunneling layer 152s. In an implementation, a plasma assisted doping process may be used for doping carbon. Accordingly, the carbon-containing layer 152f may be doped with carbon at a desired doping concentration and a doping depth.
In an implementation, the first tunneling layer 152a having the above structure may be formed by sequentially forming the carbon-containing layer 152f and the base tunneling layer 152s by an atomic layer deposition process. In this case, the carbon-containing layer 152f and the base tunneling layer 152s may be formed in a continuous process using a same device, thereby simplifying the manufacturing process.
Referring to
In an implementation, the first carbon-containing layer 152g and the second carbon-containing layer 152h may have different carbon contents. In an implementation, a carbon content of the first carbon-containing layer 152g closer or proximate to the channel layer 140 may be greater than a carbon content of the second carbon-containing layer 152h closer or proximate to the second tunneling layer 152b. In an implementation, the first carbon-containing layer 152g having a larger FN tunneling region may be closer to the channel layer 140, and the first carbon-containing layer 152g and the second carbon-containing layer 152h may be positioned such that an energy band gap gradually increases from the channel layer 140 toward the second tunneling layer 152b. Accordingly, charge tunneling may be performed more smoothly.
In an implementation, a base tunneling layer 152s may be further included between the carbon-containing layer 152f and the second tunneling layer 152b. Then, the first carbon-containing layer 152g, the second carbon-containing layer 152h, and the base tunneling layer 152s may be disposed such that the energy band gap gradually increases from the channel layer 140 toward the second tunneling layer 152b.
In an implementation, the base tunneling layer 152s may be between the channel layer 140 and the carbon-containing layer 152f. In an implementation, the base tunneling layer 152s may be at opposite sides of the carbon-containing layer 152f. In an implementation, the carbon-containing layer 152f may be at opposite sides of the base tunneling layer 152s. In an implementation, at least one of the carbon-containing layers 152f at opposite sides of the base tunneling layer 152s may include a plurality of carbon-containing layers 152g and 152h as illustrated in
In an implementation, a thickness of the carbon-containing layer 152f may be greater than that of the base tunneling layer 152s. In an implementation, the carbon-containing layer 152f may include a plurality of layers, may be stably formed, and an effect of the carbon-containing layer 152f may be sufficiently implemented. In an implementation, the thickness of the carbon-containing layer 152f may be smaller than that of the base tunneling layer 152s.
In an implementation, the carbon-containing layer 152f may include two layers having different compositions (e.g., different carbon contents). In an implementation, the carbon-containing layer 152f may include three or more layers having different compositions (e.g., different carbon contents). In an implementation, the carbon content of the carbon-containing layer 152f may decrease or increase gradually or stepwise in a direction from the channel layer 140 toward the second tunneling layer 152b.
In an implementation, the carbon-containing layer 152f including a plurality of layers may be formed using a plasma assisted doping process, or may be formed by changing process conditions in an atomic layer deposition process.
Hereinafter, Experimental Examples will be described with reference to
In semiconductor devices according to Experimental Examples 1 and 2, the first tunneling layer included a carbon-containing layer made of silicon oxycarbide. A carbon content of the carbon-containing layer according to Experimental Example 2 was greater than that of the carbon-containing layer according to Experimental Example 1. In the semiconductor device according to a Comparative Example, the first tunneling layer was formed of a silicon oxide that did not include carbon. The Comparative Example had a same structure as Experimental Example 1 and 2 except for a first tunneling layer.
A dielectric constant of the first tunneling layer was measured in the semiconductor devices according to Experimental Examples 1 and 2 and the Comparative Example, and results thereof are illustrated in
Referring to
In the semiconductor devices according to Experimental Examples 1 and 2 and the Comparative Example, leakage current density (Jg) was measured while changing a gate voltage, and results thereof are shown in
Referring to
After 10,000 cycles of operation, in the semiconductor device according to the Comparative Example and Experimental Example 1, a drain current according to the gate voltage was measured and results thereof are illustrated in
Referring to
In the semiconductor devices according to the Comparative Example and Experimental Examples 1 and 2, a breakdown time (Tbd) to a total charge amount (Qbd) of breakdown occurs was measured, and results thereof are illustrated in
Referring to
In the above description, it has been exemplified that the gate contact portion 184 extends through the cell insulating layer 132 to reach the gate electrode 130 and to be connected to the gate electrode 130 in the connecting region 104. In an implementation, the gate contact portion 184 may extend through the cell insulating layer 132 and the gate electrode 130, and extend to the first wire portion 230 in the circuit region 200. In this case, the gate contact portion 184 may include a pad corresponding to the gate electrode 130 to be connected among the gate electrodes 130 included in the gate stack structure 120, and may be insulated from the other gate electrode 130 with an insulating material.
An additional embodiment different from the above-described embodiment will be described in detail with reference to
Referring to
The circuit region 200a may have a first junction structure 238 on a surface facing the cell region 100a on the first substrate 210, the circuit element 220, and the first wire portion 230.
The cell region 100a may include a second junction structure 194 on a surface facing the circuit region 200a on the second substrate 110, the gate stack structure 120, the channel structure CH, and the second wire portion 180.
The second substrate 110a may be a semiconductor substrate including a semiconductor material. In an implementation, the second substrate 110a may be a semiconductor substrate made of a semiconductor material or may be a semiconductor substrate on which a semiconductor layer is formed on a base substrate. In an implementation, the second substrate 110a may be formed of single crystal or polycrystalline silicon, germanium, silicon-germanium, silicon-on-insulator, or germanium-on-insulator.
In the gate stack structure 120, the gate electrode 130 may include the lower gate electrode 130L, the memory cell gate electrode 130M, and the upper gate electrode 130U sequentially on the second substrate 110a toward the circuit region 200a from the second substrate 110a. In an implementation, as illustrated in
In an implementation, the channel pad 144 and the second wire portion 180 on the gate stack structure 120 may be adjacent to the circuit region 200a. In an implementation, the second junction structure 194 electrically connected to the second wire portion 180 may be on a surface facing the circuit region 200a. A region other than the second junction structure 194 may be covered by an insulating layer 196. In an implementation, in the cell region 100a, the second wire portion 180 and the second junction structure 194 may face the circuit region 200a.
In an implementation, the first junction structure 238 or the second junction structure 194 and the first junction structure 238 of the circuit region 200a may be made of aluminum, copper, tungsten, or an alloy including the same. In an implementation, the first and second junction structures 238 and 194 may include copper, and the cell region 100a and the circuit region 200a may be bonded by copper-to-copper bonding (directly contacted and bonded).
In an implementation, as illustrated in
The semiconductor device 20 according to an example may include an input/output pad 198 and an input and output connecting wire 198a electrically connected thereto. The input and output connecting wire 198a may be electrically connected to a portion of the second junction structure 194. The input/output pad 198 may be on, e.g., an insulating layer 198b covering an outer surface of the second substrate 110a. In an implementation, a separate input and output pad electrically connected to the circuit region 200a may be provided.
In an implementation, the circuit region 200a and the cell region 100a may respectively be portions corresponding to a first structure 1100F and a second structure 1100S of a semiconductor device 1100 included in an electronic system 1000 illustrated in
An example of an electronic system including the aforementioned semiconductor device will be described in detail.
Referring to
The semiconductor device 1100 may be a non-volatile memory device, and may be, e.g., a NAND flash memory device described with reference to
The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an implementation, the first structure 1100F may be next to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bitline BL, a common source line CSL, a word line WL, first and second gate upper lines UL1 and UL2, and first and second gate lower lines LL1 and LL2, and a memory cell string CSTR between the bitline BL and the common source line CSL.
In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bitline BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. A number of lower transistors LT1 and LT2 and a number of upper transistors UT1 and UT2 may be variously modified according to another embodiment.
In an implementation, the lower transistors LT1 and LT2 may include ground selective transistors, and the upper transistors UT1 and UT2 may include string selective transistors. The first and second gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.
The common source line CSL, the first and second gate lower lines LL1 and LL2, the word line WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first connecting wire 1115 extending from the first structure 1100F to the second structure 1100S. The bitline BL may be electrically connected to the page buffer 1120 through a second connecting wire 1125 extending to the second structure 1100S in the first structure 1100F.
In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may execute a control operation on at least one memory cell transistor selected from among the memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through an input and output pad 1101 electrically connected to the logic circuit 1130. The input and output pad 1101 may be electrically connected to the logic circuit 1130 through an input and output connecting wire 1135 extending from the first structure 1100F to the second structure 1100S.
The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In an implementation, the electronic system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the semiconductor devices 1100.
The processor 1210 may control an overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate according to predetermined firmware, and may access the semiconductor devices 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor devices 1100. A control command for controlling the semiconductor device 1100, data to be recorded in the memory cell transistor MCT of the semiconductor device 1100, and data to be read from the memory cell transistor MCT of the semiconductor device 1100 may be transmitted through the NAND interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor devices 1100 in response to the control command.
Referring to
The main substrate 2001 may include a connector 2006 including a plurality of pins coupled to an external host. A number and disposition of the pins in the connector 2006 may vary depending on a communication interface between the electronic system 2000 and the external host. In an implementation, the electronic system 2000 may communicate with the external host according to any one of interfaces such as a universal flash storage (USB), a peripheral component interconnect express (PCI-Express), a serial advanced technology attachment (SATA), M-Phy for universal flash storage (UFS), or the like. In an implementation, the electronic system 2000 may operate with power supplied from an external host through the connector 2006. The electronic system 2000 may further include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and semiconductor package 2003.
The controller 2002 may record data in the semiconductor package 2003, or may read data from the semiconductor package 2003, and may improve an operation speed of the electronic system 2000.
The DRAM 2004 may be a buffer memory for buffering a speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may also operate as a kind of cache memory, and may provide a space for temporarily storing data in the control operation for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.
The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. The first and second semiconductor packages 2003a and 2003b may be semiconductor packages each including a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on a lower surface of each semiconductor chip 2200, a connecting structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chip 2200 and the connecting structure 2400 on the package substrate 2100.
The package substrate 2100 may be a printed circuit board including a package upper pad 2130. Each semiconductor chip 2200 may include an input and output pad 2210. The input and output pad 2210 may correspond to the input and output pad 1101 of
In an implementation, the connecting structure 2400 may be a bonding wire electrically connecting the input and output pad 2210 and the package upper pad 2130. In an implementation, the semiconductor chips 2200 may be electrically connected to each other by using a bonded wire method, and may be electrically connected to the package upper pad 2130 of the package substrate 2100 in each of the first and second semiconductor packages 2003a and 2003b. In an implementation, the semiconductor chips 2200 may be electrically connected to each other by a connecting structure including a through silicon via (TSV) instead of the bonding wire connecting structure 2400 in each of the first and second semiconductor packages 2003a and 2003b.
In an implementation, the controller 2002 and the semiconductor chip 2200 may be included in one package. In an implementation, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate that is different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other by a wire positioned on the interposer substrate.
Referring to
The semiconductor chip 2200 may each include a semiconductor substrate 3010, and a first structure 3100 and a second structure 3200 stacked in turn on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral wire 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 and a separating structure 3230 through the gate stack structure 3210, a bitline 3240 electrically connected to the channel structure 3220, and a gate connecting wire electrically connected to a word line (reference sign WL of
In an implementation, in the semiconductor chip 2200 or the semiconductor device, the tunneling layer 152 may have an excellent operation speed, durability, and reliability by having the carbon-containing layer 152f in a portion adjacent to the channel layer 140.
Each of the semiconductor chips 2200 may include a through wire 3245 that is electrically connected to the peripheral wire 3110 of the first structure 3100 and extends into the second structure 3200. The through wire 3245 may extend through the gate stack structure 3210, and may be further positioned outside the gate stack structure 3210. Each semiconductor chip 2200 may further include an input and output connecting wire 3265 electrically connected to the peripheral wire 3110 of the first structure 3100 and an input and output pad 2210 electrically connected to the input and output connecting wire 3265 extending into the second structure 3200.
In an implementation, a plurality of semiconductor chips 2200 in the semiconductor package 2003 may be electrically connected to each other by a connecting structure 2400 having a form of a bonding wire. In an implementation, the semiconductor chips 2200 or a plurality of portions constituting the semiconductor chips 2200 may be electrically connected by a connecting structure including a through silicon via (TSV).
Referring to
The first structure 4100 may include a peripheral circuit region including a peripheral wire 4110 and a first junction structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a channel structure 4220 and a separating structure 4230 extending through the gate stack structure 4210, and a second junction structure 4250 electrically connected to the word line (reference numeral WL in
In an implementation, in the semiconductor chip 2200a or the semiconductor device, the tunneling layer 152 may have an excellent operation speed, durability, and reliability by having the carbon-containing layer 152f in a portion adjacent to the channel layer 140.
Each of the semiconductor chips 2200a may further include an input and output pad 2210 and an input and output connecting wire 4265 under the input and output pad 2210. The input and output connecting wire 4265 may be electrically connected to a portion of the second junction structure 4250.
In an implementation, a plurality of semiconductor chips 2200 in the semiconductor package 2003 may be electrically connected to each other by a connecting structure 2400 having a form of a bonding wire. In an implementation, the semiconductor chips 2200 or a plurality of portions constituting the semiconductor chips 2200 may be electrically connected by a connecting structure including the through silicon via (TSV).
One or more embodiments may provide a semiconductor device capable of improving an operating speed, durability, and reliability.
According to an embodiment, the carbon-containing layer having a relatively low dielectric constant may include carbon at a portion that is adjacent to the channel layer rather than the charge storage layer in the tunneling layer and functioning as an electric field concentration layer may be provided, thereby facilitating charge tunneling. Accordingly, the operation speed and durability may be improved. In this case, the carbon-containing layer may be made of a silicon oxycarbide, and thus reliability may be improved by increasing a breakdown voltage and reducing a leakage current.
In accordance with the manufacturing method of the semiconductor device according to the embodiment, the above-described tunneling layer including the carbon-containing layer may be stably formed through a simple process. Herein, when a carbon-containing layer is formed using a plasma assisted doping process, carbon may be doped to have a desired doping concentration and a doping depth.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0006962 | Jan 2023 | KR | national |
