Patent Application
20210013375
The present disclosure relates to a semiconductor device package, and more particularly, to a semiconductor device package including a trench.
In a semiconductor device package (e.g., an optical device), a die or chip (e.g., a light emitting device) is disposed on a carrier and a lid is attached to the carrier to cover the die. The lid may be electrically connected to the carrier through conductive pillars. The conductive pillars are attached to the transparent lid through a conductive glue or tape. However, during the manufacturing process, voids may exist in the conductive glue or tape, which may adversely affect the electrical performance of the semiconductor device package, even causing a failure of the semiconductor device package.
In some embodiments, a semiconductor device package includes a carrier, a conductive pillar, an adhesive layer and a package body. The conductive pillar is disposed on the carrier. The conductive pillar has a top surface facing away from the carrier. The adhesive layer is disposed on the top surface of the conductive pillar. The package body is disposed on the carrier. The package body has a top surface facing away from the carrier. The top surface has a first portion and a second portion. The first portion and the second portion of the top surface of the package body are discontinuous.
In some embodiments, a semiconductor device package includes a carrier, a conductive pillar, a package body, and an adhesive layer. The conductive pillar disposed on the carrier. The conductive pillar having a top surface facing away from the carrier. The package body is disposed on the carrier. The package body defines a cavity to expose a portion of the carrier and a trench connected to the cavity. The adhesive layer is disposed on the top surface of the conductive pillar. At least a portion of a sidewall of the adhesive layer is exposed from the trench of the package body.
In some embodiments, a semiconductor device package includes a carrier, a conductive pillar, a package body and an adhesive layer. The conductive pillar is disposed on the carrier. The conductive pillar has a top surface facing away from the carrier. The package body is disposed on the carrier. The package body defines a cavity to expose a portion of the carrier, a first trench connected to the cavity and a second trench connected to the external of the semiconductor device package. The adhesive layer is disposed on the top surface of the conductive pillar and between the first trench and the second trench.
Aspects of some embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that various structures may not be drawn to scale, and dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.
Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. The present disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings.
The carrier 10 may include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate. The carrier 10 may include an interconnection structure, such as a plurality of conductive traces or a through via. In some embodiments, the carrier 10 includes a ceramic material or a metal plate. In some embodiments, the carrier 10 may include a substrate, such as an organic substrate or a leadframe. In some embodiments, the carrier 10 may include a two-layer substrate which includes a core layer and a conductive material and/or structure disposed on an upper surface and a bottom surface of the carrier 10. The conductive material and/or structure may include a plurality of traces.
The electronic component 11 is disposed on the carrier 10. The electronic component 11 may include an emitting die or other optical die. For example, the electronic component 11 may include a light-emitting diode (LED), a laser diode, a vertical-cavity surface-emitting laser (VCSEL) or another device that may include one or more semiconductor layers. The semiconductor layers may include silicon, silicon carbide, gallium nitride, or any other semiconductor materials. The electronic component 11 can be connected to the carrier 10 by way of flip-chip or wire-bond techniques, for example. In some embodiments, the electronic component 11 includes an LED die bonded on the carrier 10 via a die bonding material. The LED die includes at least one wire-bonding pad. The LED die is electrically connected to the carrier 10 by a conductive wire, one end of which is bonded to the wire-bonding pad of the LED die and another end of which is bonded to a wire-bonding pad of the carrier 10. The electronic component 11 has an active region (or light emitting area) facing toward the lid 14. In other embodiments, the electronic component 11 may include a light detector or sensor (e.g., a PIN diode, a photo-diode, a photo-transistor or the like). In some embodiments, the electronic component may include any semiconductor dies or chips other than optical components.
The conductive pillar (e.g., copper pillar or copper post) 13 is disposed on the carrier 10. The conductive pillar 13 is disposed between the carrier 10 and the lid 14 and electrically connects the lid 14 with the carrier 10. The conductive pillar 13 is attached or bonded to the lid 14 through the adhesive layer 15. In some embodiments, the adhesive layer 15 includes a conducting material, such as sliver paste, solder paste or the like. The conductive pillar 13 may be a solid cylindrical post, a solid square post, or a solid post with a suitable shape. In some embodiments, the number of the conductive pillar 13 can be changed depending on different design specifications.
The lid 14 is disposed on the adhesive layer 15 and the package body 12. For example, the lid 14 is disposed on a coplanar surface defined by a surface 151 of the adhesive layer 15 and a surface 121 of the package body 12. The lid 14 includes a patterned conductive layer (or a conductive trace). The patterned conductive layer is disposed on a lower surface of the lid 14 (e.g. facing the carrier 10). The patterned conductive layer may be embedded in and exposed by the lower surface of the lid 14. The patterned conductive layer is electrically connected to the carrier 10 via the conductive pillar 13 and the adhesive layer 15. The lid 14 may include a transparent material. The lid 14 may include a conductive material or a dielectric material. In some embodiments, the lid 14 may include a glass, a transparent metal (e.g. an indium-tin-oxide (ITO) or an indium-zinc-oxide (IZO)), or a plastic. In some embodiments, the lid 14 may be a shield (e.g., an electromagnetic interference (EMI) shield) configured to prevent the electronic component 11 from being interfered by electromagnetic radiation/wave from the outside of the semiconductor device package 1.
In some embodiments, the lid 14 is also attached or bonded to the package body 12 through an adhesive layer. For example, as shown in
The package body (or encapsulant) 12 is disposed on the carrier 10. The package body 12 defines a cavity 12c to accommodate the electronic component 11. The package body 12 covers a portion of the conductive pillar 13 and a portion of the adhesive layer 15. The package body 12 also defines a trench (or trenches) 12t to expose a portion of a sidewall 132 of the conductive pillar 13 and a portion of a sidewall 152 of the adhesive layer 15. As shown in
During some of the process (e.g., reflow, cure or the like) for manufacturing a semiconductor device package, voids may be generated in the adhesive layer (or adjacent to an interface between the adhesive layer and the conductive pillar), which would adversely affect the electrical performance of the semiconductor device package, even causing a failure of the semiconductor device package. In some embodiments, the above issues may be mitigated by low-temperature multi-stage baking the adhesive layer and the conductive pillar. However, this can eliminate the voids adjacent to the center of the adhesive layer, but the voids adjacent to the periphery of the adhesive layer cannot be fully eliminated. In addition, the low-temperature multi-stage baking operation would increase the manufacturing cost and time. In accordance with the embodiments in
In the description of some embodiments, a component provided “on” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.
In the description of some embodiments, a component characterized as “light transmitting” or “transparent” can refer to such a component as having a light transmittance of at least 80%, such as at least 85% or at least 90%, over a relevant wavelength or a relevant range of wavelengths, such as a peak infrared wavelength or a range of infrared wavelengths emitted by a light emitter. In the description of some embodiments, a component characterized as “light shielding,” “light blocking,” or “opaque” can refer to such a component as having a light transmittance of no greater than 20%, such as no greater than 15% or no greater than 10%, over a relevant wavelength or a relevant range of wavelengths, such as a peak infrared wavelength or a range of infrared wavelengths emitted by a light emitter.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It can be understood that such range formats are used for convenience and brevity, and should be understood flexibly to include not only numerical values explicitly specified as limits of a range, but also all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.
As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.
While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made, and equivalents may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus, due to variables in manufacturing processes and such. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.
