The present application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-258906 filed on Sep. 6, 2004, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention generally relates to methods of controlling semiconductor devices and data writing, and particularly relates to a method of controlling a semiconductor device provided with a circuit for controlling a data setting to a register and a method of controlling data writing to a register.
2. Description of the Related Art
In semiconductor chips, a CPU and various resources are provided as circuits implemented by use of semiconductors. The semiconductor circuits such as the CPU and resources are provided with one or more registers for the purpose of defining operation modes. Desired settings are made to control the operations. If users set prohibited set values to the registers, or if the prohibited set values are accidentally set due to noise, for example, the semiconductor circuits malfunction, which may result in the loss of control of chip operations.
The resource circuits include a clock generation circuit, a timer circuit, an A/D converter, a communication macro, etc. In a resource circuit such as a communication macro that operates in synchronization with a clock, the range of the clock for providing proper operations is predefined. For example, a clock frequency falling within the range from 10 MHz to 50 MHz, for example, guarantees proper operations. In such a case, if the clock frequency is accidentally set to 100 MHz, the resource circuits end up operating outside the guaranteed range, resulting in the semiconductor chip being at the risk of going out of control. A further example may be an A/D converter in which proper conversion speed is 1-mega samplings per second. If the conversion speed is set to 10-mega samplings, proper A/D conversion cannot be attained.
As a technology for prohibiting an incorrect setting to a register, Patent Document 1 provides a key data register to which the same address as that of a set register is assigned. An unlocking instruction signal is generated only when the same data as predetermined data is written to the key data register, making it possible to write to the set register. This removes ease with which writing is done to the set register, thereby preventing accidental writing to the set register.
[Patent Document 1] Japanese Patent Application Publication No. 2003-150448
The construction disclosed in Patent Document 1 requires that an unlocking process be performed by following predetermined procedures at the time of writing to the register. This results in complicated control procedures. Also, the processing time required for the unlocking process cannot be ignored if rewriting to the register is frequently performed. Further, if the user intends to set the register, but attempts to write a prohibited set value by mistake, the writing of such prohibited set value is accepted through the unlocking process as if there was no problem. Namely, the value of the key data register serving as a key is checked, but the set value to be written to the register is not checked. That is, no proper prevention is given in the case where an attempt is made to write an incorrect set value.
Accordingly, there is a need for a semiconductor device which can reliably prevent a prohibited set value from being written to a register.
It is a general object of the present invention to provide a semiconductor device that substantially obviates one or more problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be presented in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages in accordance with the purpose of the invention, the invention provides a semiconductor device which includes a data hold circuit configured to acquire data from a data bus and hold the data therein in response to assertion of a write signal, a prohibited set value hold circuit configured to store a predetermined prohibited set value, and a comparison circuit coupled to the data hold circuit and the prohibited set value hold circuit, and configured to assert a prohibition signal in response to a match between the prohibited set value stored in the prohibited set value hold circuit and the data held in the data hold circuit, the assertion of the prohibition signal preventing the data from being written to a predetermined register.
According to another aspect of the present invention, a method of controlling writing of data to a register includes the steps of transmitting the data to a data bus so as to write the data to the register, monitoring the data bus by comparing the data appearing on the data bus with a prohibited set value defined for the register, and prohibiting the writing of the data to the register in response to detection of a match by said comparing between the data and the prohibited set value.
According to at least one embodiment of the invention, the write data is compared with the prohibited set value, and the prohibition signal is asserted in response to the match therebetween. Provision is further made such that the assertion of the prohibition signal prohibits the data from being written to the predetermined register. This can prevent the writing of a predetermined prohibited set value from being performed with respect to the predetermined register.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings; in which
In the following, embodiments of the present invention will be described with reference to the accompanying drawings.
The registers subject to the monitoring are not limited to the registers provided in the resource 11 or the resource 12. If another bus master is capable of writing to a register inside the CPU 10, such a register of the CPU 10 may also be subject to the monitoring. Namely, when data is written to a predetermined address by a write signal, an address signal, and a data signal through the bus 14 in the semiconductor device of
The monitor circuit 13 asserts a reset signal in response to the detection of writing of a predetermined prohibited set value to the register having a predetermined address. In response to the assertion of the reset signal, all the circuits of the semiconductor device of
The decoder 23 decodes an address signal on the address bus of the bus 14. When the address signal matches the address of a register subject to monitoring, the decoder 23 asserts a read signal to the prohibited set value storage circuit 22, and asserts a comparison result output signal to the comparison circuit 24.
The prohibited set value storage circuit 22 includes a register that stores a prohibited set value of the register subject to the monitoring. Upon the assertion of the read signal supplied from the decoder 23, the prohibited set value storage circuit 22 supplies the prohibited set value stored in the built-in register to the comparison circuit 24.
The comparison circuit 24 compares the write data supplied from the data hold circuit 21 with the prohibited set value supplied from the prohibited set value storage circuit 22. If the write data and the prohibited set value are identical, and if the comparison result output signal supplied from the decoder 23 is asserted, the comparison circuit 24 asserts a reset signal serving as its output. In response to the assertion of the reset signal, all the circuits in the semiconductor device of
The OR circuit 32 obtains a logical sum between all the bits of the results of exclusive logical sum and the comparison result output signal supplied from the decoder 23. The comparison result output signal is a negative logic signal that assumes a LOW level in the asserted state, and becomes LOW when the write address and the address subject to monitoring are identical. The OR circuit 32 thus outputs a LOW reset signal only if the write data and the prohibited set value are completely identical and if the write address and the address subject to the monitoring are identical. This reset signal is a negative logic signal that assumes a LOW level in the asserted state. In response to the LOW output, the resetting of each circuit is performed.
The output of the prohibited set value storage circuit 22 always assumes some value. If this value and the write data coincide with each other by accident, the EOR circuit 31 ends up producing the same output as when the write data and the prohibited set value are completely identical. In order to prevent the reset signal from being asserted in such a case, therefore, provision such as the OR circuit 32 of
With the provision described in the above embodiment, it is possible to reset all the circuits in the semiconductor device by use of the reset signal if the writing of a predetermined prohibited set value is performed to the register having a predetermined address, thereby preventing the writing of the predetermined prohibited set value to the register having the predetermined address. In the construction of
The address information hold circuit 41 acquires an address signal on the address bus of the bus 14 for storage in a built-in register in response to the assertion of a write signal. The data information hold circuit 42 acquires a data signal on the data bus of the bus 14 for storage in a built-in register in response to the assertion of a write signal. When the operation of the monitor circuits 13 as described above detects the writing of a predetermined prohibited set value to the register having a predetermined address, each circuit of the semiconductor device is reset. The built-in registers of the address information hold circuit 41 and the data information hold circuit 42 are configured such that they are not initialized by this resetting operation.
After the resetting, an address signal on the address bus of the bus 14 is set to select the address assigned to the address information hold circuit 41, with assertion of a read signal. This makes it possible to read the data contents of the address information hold circuit 41 (i.e., to read the address value that has caused the resetting). By the sake token, an address signal on the address bus of the bus 14 is set to select the address assigned to the data information hold circuit 42, with assertion of a read signal. This makes it possible to read the data contents of the data information hold circuit 42 (i.e., to read the write data value that has caused the resetting). Here, the address assigned to the data information hold circuit 42 needs to be different from addresses assigned to other registers provided in the semiconductor device. If the same address is assigned, data collision occurs at the time of data reading. The same applies in the case of the address information hold circuit 41.
The address information hold circuit 41 may be configured in the same manner as the data information hold circuit 42. In the case of the address information hold circuit 41, however, the stored content is an address signal, so that the register 51 of
The prohibited set value storage circuit 22 of
The decoder 23 decodes an address signal on the address bus of the bus 14 (
In this manner, the prohibited set value storage circuit 22 shown in
The prohibited set value storage circuit 22 having the configuration as described above, however, can only monitor a single prohibited set value per monitored register. The number of prohibited set values is not limited to one for one register subject to monitoring. Any one of the plurality of prohibited set values, if written, may cause malfunction. In some cases, thus, it is preferable to provide a configuration in which a plurality of prohibited set values can be monitored for each register subject to monitoring.
The monitor circuit 13a of
The data hold circuit 21 acquires data on the data bus for storage in a built-in register in response to the assertion of a write signal. The stored data is supplied to the comparison circuits 24a through 24c. This data is write data that is to be written to any given register in the semiconductor device regardless of the address of this register.
The prohibited set value registers 71 and 72 store two prohibited set values for the register subject to monitoring provided at the address XX. The prohibited set value registers 73, 74, and 75 store three prohibited set values for the register subject to monitoring provided at the address XX+1. The prohibited set value register 76 store one prohibited set value for the register subject to monitoring provided at the address XX+2. Although the addresses are provided as consecutive addresses in this example, there is no need that these addresses are consecutive. That is, the addresses may as well be any addresses subject to monitoring.
The decoders 23a and 23b decode an address signal on the address bus of the bus 14 (
The comparison circuit 24a through 24c compares the write data supplied from the data hold circuit 21 with the prohibited set values supplied from the corresponding prohibited set value registers. If the write data and any one of the prohibited set values are identical, the comparison circuits 24a through 24c assert the reset signals serving as their outputs. These reset signals are positive logic signals. The OR circuit 79 obtains a logical sum between the reset signals supplied from the comparison circuits 24a through 24c. This provides for the reset signal output from the OR circuit 79 to be asserted if writing is performed with respect to any one of the one or more prohibited set values provided for any one of the registers subject for monitoring. In response to the assertion of this reset signal, all the circuits in the semiconductor device of
In the configuration of
Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.
The above embodiments have been described with respect to a configuration in which a reset signal is generated in response to the detection of the writing of a prohibited set value to a register subject to monitoring. Alternatively, a mask signal may be generated in place of the reset signal, and this mask signal may be used to prevent writing to a register subject to monitoring. In this case, a conventional configuration would results in data being written to a register subject to monitoring once a write signal is asserted with the write data signal and the address signal indicative of the write destination being supplied to the bus. To prevent this, the register subject to monitoring may be configured to latch the data at delayed timing. Provision is then made such that the register latches the data if the mask signal is not asserted, and refrains from latching the data if the mask signal is asserted.
Number | Date | Country | Kind |
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2004-258906 | Sep 2004 | JP | national |